JPS6337885A - Memory card - Google Patents

Abstract

PURPOSE:To mount plural chips without increasing the number of terminals of a connector by providing a register latching memory chip selection data and selecting data based on the selection data latched in the register. CONSTITUTION:When the memory chip selection data is externally outputted, the data is fed to a data bus 13 via a connector 12. A register 31 latches memory chip selection data transferred to a bus 13 and outputs the latched data to a decoder 22. The decoder 22 selects plural memory chips 11a-11c based on the memory chip selection data from the register 31. Thus, when any of the chips 11a-11c is selected, a write signal or a read signal is inputted to the selected memory chip. Thus, only the latch signal in the register 31 is inputted externally. Thus, the increase the number of signal lines is only one line, a register control signal line 32.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a memory card with a built-in memory chip.

(Prior art) Conventionally, in so-called memory cartridges or thin card-shaped memory cards that are mounted in a cartridge shape and have a structure that is convenient for removal from the main unit, memory chips are generally used for miniaturization. Currently, it is only equipped with

FIG. 2 is a schematic configuration diagram of a memory card formed in a card shape, in which a memory chip 11 and a connector 12 are directly connected by a data bus 13, an address bus 14, and a control bus 15, and are housed in a case 16. There is.

In a memory card formed in this way, when viewed from the main body side (not shown), the memory is directly connected, so it cannot be controlled using the access time of the memory itself. , it is possible to realize faster processing speed.

However, in the memory card with the above configuration, when the memory capacity becomes large, the Wa
S memory chips 11a, 11b, . . . must be installed. In this case, the memory chip 11a of Kazuo,
An expansion address signal 1i 121 and a decoder 22 are required to select and control 11b, . . .

Here, the expansion address signal I! The number 21 must be increased according to the required capacity (number of memory chips).

That is, for example, if two memory chips are built-in, only one expansion address signal line 21 is required, but if there are more memory chips, the expansion address signal line 21 is connected to the memory chip. will have to increase as the number increases.

Therefore, as shown in FIG.
, 11b, . . . , connectors 12 must also be prepared in accordance with the increase in the number of expansion address signal lines 21, resulting in an increase in the size of the entire card.

Note that in order to solve the above-mentioned problems, in order to maintain compatibility with small-capacity memory cards, the hardware must be designed with maximum capacity in mind, which raises the problem of increased costs.

Furthermore, if a control circuit is built-in, it will take time to receive data from the main unit, and the control circuit will have to be made into a custom IC for miniaturization, which will further increase costs. .

(Problems to be Solved by the Invention) As mentioned above, in conventional memory cards, as the number of memory chips increases due to the increase in memory capacity 1, the number of connector terminals increases and the size of the card becomes smaller. There was a limit.

Furthermore, in order to reduce the number of terminals on this connector, we have constructed hardware that takes into account the maximum capacity.
When one circuit was built-in, there was a drawback that it required a lot of effort.

The present invention was made in view of the above points, and it is possible to handle an increase in memory capacity by connecting multiple memory chips without increasing the number of connector terminals, at low cost, and without reducing transfer speed. The purpose of the present invention is to provide a memory card that can be equipped with.

[Structure of the Invention] (Means for Solving the Problems) That is, in the memory card of the present invention, for example,
When connected to the address bus or data bus of multiple memory chips, and when memory chip selection data for selecting the memory chip is transferred from the outside to the same address bus or data bus, this memory chip selection data is transferred. The device is provided with a register that latches the memory chip, and is configured to select one of the plurality of memory chips based on the memory chip selection data latched in the register.

(Function) In the memory card configured as described above,
Memory chip selection data from outside is now transferred to the data bus or address bus, this memory chip selection data is latched in the above register, and multiple memory chips are selected based on this latched memory chip selection data. Which one will be selected.

Therefore, the increase in the number of terminals in the connector can be reduced to just the signal line for controlling the registers mentioned above.
It is possible to realize a memory card that can mount a plurality of memory chips at low cost and without reducing transfer speed.

(Embodiment) A memory card according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the circuit configuration of the memory card of the present invention, and like FIG.
, llb, 11c are memory chips, 12 is a connector for electrical connection with the outside (not shown), 13.14
．． 15c, a data bus, an address bus, and a control bus that connect the memory chips 11a, 11b, . . . and the connector 12;

Further, 22 is a decoder for selecting the memory chips 11a, 11b, . . . , and 16 is a case for organizing the whole.

That is, in FIG. 1, 31 is a register for memory expansion, and this register 31 latches memory chip selection data transferred to the data bus 13, and outputs this latched memory chip selection data to the decoder 22. It has the function of

Further, 32 is a register control signal line, and this register control signal l132 connects the connector 12 and the register 31, and supplies a latch signal from the outside to the register.

The operation of the memory card having the above configuration will be described below. That is, first, when memory chip selection data is output from the outside, this memory chip selection data is supplied to the data bus 13 via the connector 12. Here, a latch signal is output from the outside simultaneously with the output of this memory chip selection data, and this latch signal is supplied to the register 31 via the register control signal line 32.

Therefore, upon input of this latch signal, the register 31 latches the memory chip selection data transferred to the data bus 13 and outputs the latched memory chip selection data to the decoder 22.

The decoder 22 selects a plurality of memory chips 11a and 11b based on memory chip selection data from the register 31.
..., but in this case, decoder 2
2 performs a decoded output in synchronization with a write signal or a read signal for the memory chips 11a, Ilb, . . . transferred from the outside via the control bus 15.

In this way, when one of the memory chips 11a, 11b, . . . is selected, a write signal or a read signal is input to the selected memory chip via the control bus 15. For example, if a write signal is output from the control bus 15, data transferred from the data bus 13 is written to the address specified by the address bus 14.

In this way, the memory card with the above configuration has a built-in register 31 for mounting a plurality of memory chips 11a, 11b, etc., and only the latch signal of this register 31 is input from the outside. There is. Therefore, the number of signal lines required for expansion is only one, the register ill IE signal line 32.

Therefore, for example, if the number of data lines is 8 bits, 2
56 types of memory selection are possible, and in other words, it is possible to control the memory capacity up to 256 times the memory capacity corresponding to the number of address signals without increasing the number of terminals of the connector 12.

Note that it is also possible to use the range directly accessed by an external CPU (central processing unit) as an address line, and use it as a register for so-called page selection for expansion purposes. As a concrete example, if a ROM with JIS Kanji character patterns registered is mounted on a card and connected to an 8-bit CPU bus, and the address range that can be directly accessed is, for example, 16 kilobytes, the page The register can consist of 6 bits. Therefore, in FIG. 1, it is also possible to connect the register 31 to the address bus 14 as a page select register to select a memory chip.

As described above, according to the present invention, even when a plurality of memory chips are mounted due to an increase in memory capacity, one of them
The only hardware required for this function is a register and a decoder, and it can be constructed using a general-purpose IC at a low cost, and it is possible to select a memory chip without reducing the transfer speed.

[Effects of the Invention] As described above, according to the present invention, memory chip selection data is connected to the address buses or data buses of a plurality of memory chips, and is used to select the memory chip on the address bus or the data bus. is provided with a register that latches the memory chip selection data when the memory chip selection data is transferred from the outside, and is configured to select one of the plurality of memory chips based on the memory chip selection data latched in the register. As a result, it is possible to realize a memory card that can mount a plurality of memory chips without increasing the number of connector terminals, at low cost, and without reducing transfer speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a memory card according to an embodiment of the present invention, FIG. 2 is a block diagram showing a schematic configuration of a memory card formed into a card shape, and FIG. 3 is a block diagram showing a schematic configuration of a memory card formed in a card shape. FIG. 2 is a block diagram showing a circuit configuration. +1a, 11b111c...Memory chip, 12...
- Connector, 13...Data bus, 14...Address bus, 15...Control bus, 22...Decoder, 31...Register, 32...Register control signal line. Applicant's agent Patent attorney Takehiko Suzue Figure 2 Figure 3

Claims (1)

[Claims] A connector for making an electrical connection with the outside, a plurality of memory chips connected to the outside by the connector, and a memory chip for selecting the memory chip transferred from the outside via the connector. A memory card comprising: a register that latches memory chip selection data; and a decoder that selects one of the plurality of memory chips based on the memory chip selection data latched in the register.