JPS6337718A - Analog/digital converter - Google Patents

Abstract

PURPOSE:To convert an analog voltage into a digital value with high accuracy even when an input voltage is close to the ground voltage as to a single power source by making a connection with a specific constant voltage source when the input voltage approximates the ground voltage. CONSTITUTION:When the input voltage is lower than 1/2<n+1>Vref, a switch SP is connected to V1 in a period T1, but connected to V2 in a period T2. Therefore, the output of an operational amplifier is Vref according to the charge of capacitor Cp since Sr is closed in the period T1. Then, V1> V2, so an increase by the difference between Qp2 and Qp1 is made in the period T2. Charges corresponding to (Qp2-Qp1 ; move from on the CF, and consequently the output voltage V0' of the operational amplifier rises by the difference V0 from a conventional value V0, so this quantity is selected properly to prevent the MOSFET of the output stage of the operational amplifier from deviating from its saturation area, so that high-accuracy A/D conversion is made possible even when the input voltage is almost the ground voltage.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to an analog/digital converter (A/D converter) that converts an analog voltage into a digital value, and more particularly, to a series-parallel type A/D converter. This relates to an A/D converter called an A/D converter.

(Prior art) The conventional serial-parallel A/D converter shown in Figure 3 is known (see Proceedings of the 1985 IEICE General National Conference 437 "Series-Parallel A/D Conversion System"). Consider").

FIG. 3 shows an example in which the first stage is a 4-bit parallel type A/D converter, and the operation will be explained below using this example.

The input voltage VIN is first A/D converted by a 4-bit parallel type A/D converter in the first stage, and the upper 4 pits are output. At this time, the switch is closed and the output voltage of the rA'R amplifier is connected to the inverting input terminal, and this point is virtual ground, so it becomes the reference voltage Vrar and there is no charge on the capacitor C2.

In addition, the switches S and ~SiS are connected to the input terminals, and the capacitors C and ~C16 are connected to C(V, -r V'N
) is stored. Here capacitor 00~C1
, have equal capacitance values C. Next, the switches are opened and the switches 80 to S18 are connected to the reference voltage or ground depending on the output of each first stage comparator depending on the input voltage.

However, S and St are then always connected to the reference voltage. S, ~S when input voltage VIN is from O to Veer
All ISs are connected to the ground side, so C2 has a charge Q given by the following equation.

QF-16C (V, -r VIN) 14CV1.
.

-2C'/, -r-16CVIN
-(1) In this case, the output voltage V of the operational amplifier satisfies the following formula.

Qr-Ct (V2., -V,)...
・(Since it is CF-2C, from equations (9 and (r), V is as follows.

Criteria 'if, , 83-S1. is connected to ground.

Therefore, (υ, (Similar to the equation, QF-3CV, , -16CVIN-CF(V, , -
V, ) - (4) Ss is the reference voltage, 84 ~ S L & is connected to ground, and by writing a formula similar to 4), the number of switches connected to Vo increases one by one, and the input voltage becomes ↑V, It will look like this:

All switches are connected to base d, 71'C voltage, output voltage ■. becomes as follows.

0), (9), (6), (7), and (8), the range of the output voltage V of the operational amplifier is as follows.

...G(D The second stage parallel type A/D converter inputs the output voltage of this operational amplifier and performs A/D conversion.

0) to (8) can be rewritten as follows.

Va-8V+s.

0≦V, N<AV Vo”8V+N, '↓ (I X) AV≦VIN (1+M) ΔVV *-
8 (VIN”V).

(2-,1()AV<VIN<(2+%)AV　1゜ However, AV --V5. t The second stage A/D conversion also uses the same reference voltage V1. .

Since A/D conversion is performed in the range of grounding and V + a t using
The second stage A/D conversion is executed within the range of SB. Therefore 1
The LSB of the output of the A/D conversion in the first stage and the MSB of the A/D conversion result in the second stage have the same digit and are converted by 1 bit overlapping each other, which requires a compensator. In order to operate as shown in equation (12), the switches S and ~S18 are switched using the output of the first stage comparator, but by converting one bit overlapping, the offset voltage of the comparator is used as the output of the first stage comparator. %LSB of parallel A/D converter resolution
It is acceptable up to

A two-stage series-parallel type A/D converter has been described above as a prior art, but by adding a set of an amplifier, a capacitor array, and a parallel type A/D converter, a three-stage series-parallel type A/D converter can be obtained. It is also possible to configure a /D converter, and a multi-stage configuration is also possible in principle.

(Problems to be Solved by the Invention) In order to convert the series-parallel type A/D converter mentioned in the section (prior art) into an IC using CMO5 technology, it is easy to use it in terms of compatibility with other devices. 15V'? J source is advantageous.

On the other hand, the input of the second-stage A/D converter is the output voltage of the operational amplifier, and this value is the same as the example in which the first stage is a 4-bit parallel type A/D converter described in the section (Prior art). Then (9) to (1
1) Take a range as shown in the formula. Input power formula (10), (11
) The output voltage of the amplifier, V, is %Vrmf as given by equation 0), and V, − as given by equation (9).
8V and N, which ranges from O to X V r * r. If we change this to -boat fishing, if the first stage is a 01-bit parallel type A/D converter, the input voltage is V+s & the output voltage of the operational amplifier is ■. The following relationship holds true within the range.

V o -2"'-' V Is (13) When trying to convert such a series-parallel type A/D converter into an IC with a single power supply using MO5 technology, the following problem exists. Namely, the following problem exists. , when the input voltage VIN is close to 0, the output voltage V of the operational amplifier is also close to 0, and the MOSFETs forming the output stage of the operational amplifier are out of the saturation region, and (13
) formula no longer holds true.

Let's consider this with a concrete example.

Considering the operational amplifier shown in FIG. 4, the output voltage must be V, ≧V, Vt in order for the MO5FETM in the output stage to be in the saturation region. Here, V is the gate voltage of M, and vl is the threshold voltage of the MOSFET. On the other hand, in an example of an 8-pit series-parallel A/D converter where the first stage is a 4-bit parallel A/D converter, the reference voltage is 2.5.
6 V, and if the input voltage is 0.02 V, the output voltage of the operational amplifier will be 0.16 V from equation (13). Therefore, the V of M must be set so that -VT≦0.16 V. In some cases, it may be possible with careful design, but with higher viscosity A/D converters ■.≧V,
V? It becomes difficult to do so. For example, in the case of a 10-bit series-parallel A/D converter configured in three stages using a 4-pit parallel A/D converter in the first stage, if the reference voltage is set to 2.56V, the I LSB will be 0.0025V. (!: When the input voltage is 0.005V, the output voltage of the operational amplifier is 0.
．． Must be 04V, V, -V, r≦0.04
It is actually quite difficult to set the value to V. If we consider something with even higher precision, it becomes impossible. As described above, with the conventional technology, it is impossible to A/D convert an input voltage close to the ground voltage with high accuracy using a single-M, source.

(Objective of the Invention) In view of the above points, an object of the present invention is to provide a series-parallel type A/D converter that can convert an analog voltage into a digital value with high viscosity even with an input voltage close to the ground voltage using a single power supply. That's true.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides means that includes a first parallel type A/D converter that converts the voltage from analog to digital, and a A calculation part that converts the conversion result of the parallel A/D converter 1 into an analog value again, subtracts it from the input voltage, doubles that value by a certain value, and outputs it, and converts the output voltage of the calculation part to an analog value. a second parallel type A/D converter for converting from
The output result of the parallel type A/D converter and the second parallel type A
In a series/parallel type A/D converter equipped with a processing unit that adds or subtracts the output result of the /D converter: and the inverting input terminal is connected to the first node.
The 10th switch and the 1st switch are connected in parallel between the node and the output terminal.
If the resolution of the operational amplifier connected to the capacitor and the first parallel A/D converter is n bits, one end is commonly connected to the first node, and the other end is connected to the input terminal and the reference, respectively. 2nd to 2nd (2n
1+1) of 2n1 capacitors from the second to (2n1+1) connected to one switch, and a capacitor (2n1) with one end connected to the first node and the other end switching between the reference voltage and ground. (2n1+2) switch connected to the (2n1+2) switch, and if the value of the first capacitor is multiplied by 2, the second to (2n1+2)
The value of each of the 2n1 capacitors in 1) is C; the operation of the calculation part is controlled by first and second clocks whose "1" parts do not overlap, and the first switch is controlled by the first clock. The second and third switches are connected to the input terminals while the second clock is "0" and open for the period "O", and the second and third switches are connected to the input terminals while the second clock is "0", and the second and third switches are connected to the input terminals while the second clock is "0". connected to a reference voltage, and from the fourth to the second n1+1 C
F) (2" - 2) switches are connected to the input terminal while the second clock is "0" and constitute the first parallel A/D converter when the second clock is "1"; The switches are switched according to the output of the device, and when the reference voltage Vlor is set, the remaining (2"-3) switches are connected to the ground, and when the two switches are connected to the reference voltage, the remaining (2"-3) switches are connected to the reference voltage.
-4) switches are connected to ground, and each connected switch increases one by one, and the input voltage is applied to the (2n1)th switch.
+2) switch is connected to the first constant voltage source if the clock whose input voltage is 1 is "1". If the second clock is "1", the second clock is connected to a second constant voltage source.

(Principle and Embodiments of the Invention) FIG. 1 is a block diagram showing an embodiment of the invention. This is an example in which 4-pit parallel type A/D converters are used in the first and second stages. FIG. 2 is a damping diagram showing a clock for operating the embodiment of FIG. 1. The following description will be made based on FIGS. 1 and 2. In FIG. 1, the features of this embodiment that are different from the prior art are a capacitor Cp and a switch S.

The switch SP switches between two voltage terminals vI and ■.

(2) and V are constant voltages and can be selected to any value as long as V + > V x. The switches and capacitors other than S and Cp operate as in the prior art. That is, during the period T1 in which the first clock φ1 is "1", S is closed and S, ~5
llB is connected to the input terminal. When φ1 becomes "O", S opens, and the period T when the second clock -2 becomes "1"
, S, and Sss are switched between the reference voltage Veor and ground under the same conditions as described in the (Prior Art) section.

(n is the resolution of the first-stage A/D converter, which is nl-4 in the example of FIG. 1), then φ1, ≠.
Regardless of whether it is 1" or 0, if it is always connected to vl, the charge on capacitor C2 will always remain the same, so it will not affect the output voltage V of the operational amplifier, as shown in (prior art). The second and subsequent equations of Equation 0, Equation (11), and Equation (12), as well as Equation (14) and Equation (15) shown in (Problems to be Solved by the Invention) hold true.

If it is smaller, switch SP is not connected to vI in period T, but is connected to the right in period T.

Therefore, one load on capacitor C2 is for periods T and T.

Then, Qpt-cp(v,,r-vI) ('r+)
・(,16)Qpt-Cp(v,,r-vn)
('rn) ・ (17) In the 0 period T, since Sr is closed, the output of the operational amplifier is V + at - vs > Va, so in the period T, the difference between Qp and Qpt is Qpt - Qpt - Cp(V+Va)
= (18) increases on Cp. The switches S, ~SI& connected to C0~C1& operate in the same way as before, so the charges on C0~C1 are unchanged from the conventional case, so the charge of (Qpx - Qpt) is from on C7. As a result, the output voltage v, ゛ of the operational amplifier is different from the conventional value and becomes the conventional value V, expressed by equation (13).
If the difference (V, -V,') from .DELTA.V is .DELTA.V, then the following equation holds true.

Qpt Qpt −CFΔV,
- As can be seen from equations (19) and (21), the output voltage of the operational amplifier increases by the amount expressed by equation 2c), so if this amount is selected appropriately, the MOSF of the output stage of the operational amplifier
ET will not deviate from the saturation region, and highly accurate A/D conversion is possible even when the input voltage is close to the ground pressure. However, since the second-stage A/D converter uses the voltage expressed by equation (21) as the input voltage, a digital value corresponding to equation 2c) must be subtracted from the A/D conversion result. This is executed by the digital processing section using the output of the first stage comparator. Try applying specific numbers.

V, -V so that there is no need to add an extra power supply
1@rx■ Let -0 and C, -2c e Select the unit capacity C in this system as cp 2c) 2~(
22) The formula is as follows.

In this way, the output voltage of the operational amplifier becomes as shown in equation (25), allowing highly accurate A/D conversion regardless of the value of the input voltage. However, in this case, two stages of subtraction must be performed.

(Effects of the Invention) As described above, by using the present invention, a series-parallel type A/D converter that can convert a low analog voltage close to 0 into a digital value with high precision, which is difficult to realize with conventional technology, can be realized. can be provided.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a timing diagram showing a clock used in the embodiment shown in Fig. 1, and Fig. 3 is a block diagram showing a conventional serial-parallel type A/D converter. ,
FIG. 4 is a circuit diagram showing an example of an operational amplifier used in a series-parallel type A/D converter.

Claims (1)

[Claims] A first parallel A/D converter that converts an input voltage from analog to digital, and a conversion result of the first parallel A/D converter that is converted back into an analog value and inputted. an arithmetic section that subtracts the voltage from the voltage, doubles the value by a predetermined value, and outputs the result; a second parallel A/D converter that converts the output voltage of the arithmetic section from analog to digital; The output result of the parallel type A/D converter and the second parallel type A/D converter
In a series-parallel analog/digital converter comprising a processing section that adds or subtracts the output results of the D converter: The calculation section has a non-inverting input terminal connected to a reference voltage and an inverting input terminal connected to a first node. an operational amplifier connected to the first node and having a first switch and a first capacitor connected in parallel between the first node and the output terminal; and the first parallel type A/D.
If the resolution of the converter is n_1 pits, one end is commonly connected to the first node, and the other end is connected to the second to (2^n^1+
1) 2^n^1 capacitors from the second to (2^n^1+1) connected to the 2^n^1 switch, and one end connected to the first node and the other end a (2^n^1+2)-th capacitor connected to a (2^n^1+2)-th switch that switches between the reference voltage and ground;
If the value of the first capacitor is 2c, the values of the 2-1 capacitors from the second to (2^n^1+1) are each C; the operation of the calculation part is as follows: The first switch is controlled by non-overlapping first and second clocks, the first switch is closed when the first clock is "1" and is open when the first clock is "0", and the second and third switches are controlled by the second clock. The second clock is connected to the input terminal during the period of "0" and connected to the reference voltage during the period of "1", and the (2^n^1-2) clocks from the fourth to the second^n^1+1 are connected to the input terminal. The switch is connected to the input terminal during the period when the second clock is "0", and during the period when the second clock is "1", the switch changes according to the output of the comparator constituting the first parallel type A/D converter. and set the reference voltage to V_
If r_e_f, the input voltage is from the ground voltage (3/2^
All up to n^1^+^1)V_r_e_f are connected to ground, and the input voltage is (3/2^n^1^+^1)V_r
From _e_f (5/2^n^1^+^1)V_r_e_
Up to f, one switch is connected to the reference voltage and the remaining (2
The ^n^1-3) switches are connected to ground, and the input voltage varies from (5/2^n^1^+^1)V_r_e_f to (
7/2^n^1^+^1) Up to V_r_e_f, two switches are connected to the reference voltage and the rest (2^n^1-4)
The switches are connected to ground and the input voltage is below (1/
2^n^1) Each time V_r_e_f increases, the number of switches connected to the reference voltage increases one by one, and the input voltage becomes (2
^n^1^+^1-3/2^n^1^+^1) V_r_
Everything above e_f is connected to the reference voltage, and the
^n^1+2) switch has an input voltage of (1/2^n^)
1^+^1) Above V_r_e_f, it is always connected to the first constant voltage source and the input voltage changes from ground to (1/2^n^1^+
^1) During V_r_e_f, the first clock is “
If the second clock is "1", it is connected to the first constant voltage source, and if the second clock is "1", it is connected to the second constant voltage source. .