JPS6336752Y2 - - Google Patents
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- Publication number
- JPS6336752Y2 JPS6336752Y2 JP1986072888U JP7288886U JPS6336752Y2 JP S6336752 Y2 JPS6336752 Y2 JP S6336752Y2 JP 1986072888 U JP1986072888 U JP 1986072888U JP 7288886 U JP7288886 U JP 7288886U JP S6336752 Y2 JPS6336752 Y2 JP S6336752Y2
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- Japan
- Prior art keywords
- circuit
- state
- frequency
- stage
- detection
- Prior art date
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Links
- 238000001514 detection method Methods 0.000 claims description 23
- 230000010355 oscillation Effects 0.000 claims description 14
- 230000007246 mechanism Effects 0.000 claims description 5
- 239000003990 capacitor Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 206010048669 Terminal state Diseases 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
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- Electric Clocks (AREA)
Description
【考案の詳細な説明】
本考案は、基準発振回路の信号を分周回路で分
周し、その出力により計時機構を駆動し、時刻を
表示する電子時計においてて、前記分周回路の出
力信号を希望の周波数に調整するデイジタル周波
数調整回路に関するものである。[Detailed Description of the Invention] The present invention provides an electronic timepiece in which a signal from a reference oscillation circuit is divided by a frequency dividing circuit, and the output thereof drives a timekeeping mechanism to display the time. This invention relates to a digital frequency adjustment circuit that adjusts the frequency to a desired frequency.
本考案の目的は、分周回路の分周比をデイジタ
ル的に調整する事により、基準発振回路及び計時
動作には何の影響も与えず、広範囲にわたる進
み・遅れの調整が可能な回路を提供する事にあ
る。 The purpose of this invention is to provide a circuit that allows for a wide range of lead/lag adjustment without affecting the reference oscillation circuit or timekeeping operation by digitally adjusting the frequency division ratio of the frequency divider circuit. It's about doing.
従来の周波数調整装置は、発振回路内に設けら
れており、第１図に示すような発振回路で、可変
コンデンサー１を調整する事により、発振周波数
を連続的に変化させていた。しかし、この方式で
は、可変できる範囲に限界があり、水晶振動子を
固有振動数とずらせて振動させる事は、発振回路
の安定性を損なう事になり、又水晶振動子自体の
周波数設定誤差を製造時に、小さく追い込む事は
コストアツプの要因となつていた。 A conventional frequency adjustment device is provided within an oscillation circuit, and the oscillation frequency is continuously changed by adjusting a variable capacitor 1 in the oscillation circuit as shown in FIG. However, with this method, there is a limit to the range that can be varied, and making the crystal oscillator vibrate at a deviation from its natural frequency will impair the stability of the oscillation circuit, and will also reduce the frequency setting error of the crystal oscillator itself. Making the product smaller during manufacturing was a factor in increasing costs.
本考案は、これらの欠点を除去し、容易に周波
数調整の可能な回路構成を提供する事にある。 The object of the present invention is to eliminate these drawbacks and provide a circuit configuration that allows easy frequency adjustment.
以下に図面を用いて詳細に説明する。 This will be explained in detail below using the drawings.
第２図に示すのが本考案による一実施例の回路
図であり、５は発振回路、６は1/2分周回路、７
はセツト端子付1/2分周回路、８はリセツト端子
付1/2分周回路、９はＮ段分周回路、１０は分周
段の特定の状態を検出する検出回路、１１，１
２，１３は分周段７，８にプリセツトするデータ
ーを設定する設定端子、１４はラツチ回路、１
５，１６，１７，１８はANDゲートである。第
７図にセツト端子付1/2分周回路の構成図を示す。
リセツト端子付1/2分周回路もほぼ同様の回路構
成で実現できる。 FIG. 2 is a circuit diagram of an embodiment of the present invention, in which 5 is an oscillation circuit, 6 is a 1/2 frequency divider circuit, and 7 is a circuit diagram of an embodiment of the present invention.
1 is a 1/2 frequency divider circuit with a set terminal, 8 is a 1/2 frequency divider circuit with a reset terminal, 9 is an N-stage frequency divider circuit, 10 is a detection circuit that detects a specific state of the frequency division stage, 11, 1
2 and 13 are setting terminals for setting data to be preset in frequency dividing stages 7 and 8; 14 is a latch circuit;
5, 16, 17, and 18 are AND gates. Figure 7 shows the configuration of a 1/2 frequency divider circuit with a set terminal.
A 1/2 frequency divider circuit with a reset terminal can also be realized with almost the same circuit configuration.
上記構成において、１４，１５，１６，１７，
１８によつて分周段にデーターを書き込むための
書き込み制御回路を構成している。この第２図の
発振回路５から出力される信号の周波数と本来必
要とする周波数とは差があり、これを補正するた
めに書き込み制御回路により、設定端子で設定さ
れているデーターを分周回路７，８に書き込み、
発振周波数の進み・遅れを調整する。 In the above configuration, 14, 15, 16, 17,
18 constitutes a write control circuit for writing data into the frequency dividing stage. There is a difference between the frequency of the signal output from the oscillation circuit 5 in Fig. 2 and the originally required frequency. Write on 7 and 8,
Adjust the lead/lag of the oscillation frequency.
分周段にデーターを書き込む事によつて、出力
信号の進み・遅れを調整する原理を第３図を用い
て以下に説明する。 The principle of adjusting the lead/lag of an output signal by writing data to the frequency dividing stage will be explained below with reference to FIG.
第３図に示すのは、第２図の分周段７，８の出
力状態を示す論理状態表である。 FIG. 3 shows a logic state table showing the output states of frequency dividing stages 7 and 8 of FIG.
分周段７，８の出力状態が、Q2，Q3，Q4，Q5
の順に「０」、「０」、「１」、「０」の状態を検出
し、その時分周段７，８に出力が「１」、「１」、
「０」、「０」になるように書き込めば、論理状態
が１ステツプ戻される事になり、分周段の出力は
遅れとなり、分周段７，８に出力が「１」、「０」、
「１」、「０」となるよう書き込めば、１ステツプ
論理状態は進み、分周段出力は進みとなる。この
ように、検出器で検出する状態と異なつた論理状
態を分周器に書き込む事により自由に進み・遅れ
を調整する事ができる。これを実際に実現した回
路図が第２図である。検出回路１０は、Ｎ段分周
回路９の出力信号が、論理レベル「１」の時、初
期状態にもどされ、Ｎ段分周回路９の出力信号が
「１」から「０」となつた時、つまり計時動作が
なされた時に、検出信号待期状態となり、その状
態から必然的に１クロツク以上はなれて分周段８
のQ4が「１」となつた時に検出回路１０は、
「１」となり、その時ラツチ回路１４とANDゲー
ト１５で微分信号が形成され、ANDゲート１５
から出力される。この信号が、分周段にデーター
を書き込むための書き込み指令信号であり、この
信号が「１」となると、ANDゲート１６，１７，
１８を通して設定端子１１，１２，１３のデータ
ーが、分周段７，８に書き込まれる。したがつ
て、分周段にデーターを書き込む緩急調整が計時
処理回路へ何ら悪影響を及ぼすことはない。例え
ば設定端子１１，１２，１３が「１」、「１」、
「１」の場合、ANDゲート１６，１７，１８は出
力「１」となり、Q2，Q3は「１」、「１」となり、
分周段８は、リセツト端子に、ANDゲート１８
の出力が加えられるためQ4，Q5は「０」、「０」
となり、分周段は「０」、「０」、「１」、「０」から
「１」、「１」、「０」、「０」となつて１ステツプ、
論理状態が戻され、分周段出力は１ステツプの遅
れとなる。そして、この検出回路１０はNORゲ
ートのＲ−Ｓフリツプフロツプで構成されている
ため、一度検出してしまうと、Ｎ段分周回路９の
信号が「１」にならないと初期状態に戻らないた
め、ANDゲート１５から出力される書き込み指
令信号は、Ｎ段分周回路の出力が「１」から
「０」になつて、分周段８のQ4が最初に「１」に
なつた時のみを、つまり、プリセツトされる分周
段が論理φの状態を検出する事になる。第２図に
示す実施例では、検出する状態はQ2，Q3，Q4，
Q5が「０」、「０」、「１」、「０」であるが、Q4出
力だけを検出すれば、目的の状態を検出する事が
できる。しかし、検出状態が上記に説明したよう
な特殊な状態ではなく、一般的な状態でもAND
ゲートにその状態を表わす分周段の出力を入力
し、そのANDゲートの出力を検出器１０に入力
すれば容易に検出する事ができる。 The output states of frequency dividing stages 7 and 8 are Q 2 , Q 3 , Q 4 , Q 5
The state of "0", "0", "1", "0" is detected in the order of "0", "0", "1", "0", and the output is "1", "1", "1",
If you write it so that it becomes "0" or "0", the logic state will be returned by one step, and the output of the frequency division stage will be delayed, and the output to frequency division stages 7 and 8 will become "1" or "0". ,
If you write "1" and "0", the logic state will advance by one step, and the output of the frequency dividing stage will advance. In this way, by writing a logic state different from the state detected by the detector into the frequency divider, the lead/delay can be adjusted freely. A circuit diagram that actually realizes this is shown in FIG. The detection circuit 10 is returned to the initial state when the output signal of the N-stage frequency divider circuit 9 is at the logic level "1", and the output signal of the N-stage frequency divider circuit 9 changes from "1" to "0". When the time, that is, the time measurement operation is performed, the detection signal wait state is entered, and the frequency dividing stage 8 inevitably deviates from that state by one or more clocks.
When Q4 becomes "1", the detection circuit 10
becomes "1", and at that time, a differential signal is formed by the latch circuit 14 and the AND gate 15, and the AND gate 15
is output from. This signal is a write command signal for writing data to the frequency dividing stage, and when this signal becomes "1", AND gates 16, 17,
The data on the setting terminals 11, 12, and 13 are written to the frequency dividing stages 7 and 8 through the circuit 18. Therefore, the speed adjustment of writing data into the frequency dividing stage does not have any adverse effect on the timekeeping processing circuit. For example, setting terminals 11, 12, 13 are "1", "1",
In the case of "1", AND gates 16, 17, 18 output "1", Q 2 and Q 3 become "1", "1",
The frequency dividing stage 8 connects the AND gate 18 to the reset terminal.
Since the output of is added, Q 4 and Q 5 are "0" and "0"
So, the frequency dividing stage changes from "0", "0", "1", "0" to "1", "1", "0", "0" in one step,
The logic state is returned and the divider stage output is delayed by one step. Since this detection circuit 10 is composed of a NOR gate R-S flip-flop, once it is detected, it will not return to its initial state unless the signal of the N-stage frequency divider circuit 9 becomes "1". The write command signal output from the AND gate 15 is generated only when the output of the N-stage frequency divider circuit changes from "1" to "0" and Q4 of the frequency divider stage 8 becomes "1" for the first time. That is, the preset frequency dividing stage detects the state of logic φ. In the embodiment shown in FIG. 2, the states to be detected are Q 2 , Q 3 , Q 4 ,
Although Q5 is "0", "0", "1", or "0", the desired state can be detected by detecting only the Q4 output. However, even if the detection state is not a special state as explained above, but a general state, AND
It can be easily detected by inputting the output of the frequency dividing stage representing the state to the gate and inputting the output of the AND gate to the detector 10.
第２図に示す実施例で、検出回路１０に加えら
れるＮ段分周回路９の出力信号10秒周期の信号と
し、1/2分周回路６の出力信号を16384Hzとする
と、進み・遅れを調整できる最小の値は、
１／16384×86400×１／10≒0.53秒／日
となる。又、第２図の実施例では３本の設定端子
を有しているため、2.11秒／日の遅れから1.58
秒／日の進みまで調整できる事になる。 In the embodiment shown in FIG. 2, if the output signal of the N-stage frequency divider 9 applied to the detection circuit 10 is a signal with a period of 10 seconds, and the output signal of the 1/2 frequency divider 6 is 16384 Hz, then the lead/lag is The minimum value that can be adjusted is 1/16384 x 86400 x 1/10 ≒ 0.53 seconds/day. In addition, since the embodiment shown in Fig. 2 has three setting terminals, the delay is reduced from 2.11 seconds/day to 1.58 seconds/day.
This means that you can adjust the progress of seconds/day.
第４図に示すのは、第２図に示した実施例に加
えて、微調整用に設定端子１９，２０，２１，２
２，２３の５本を加えたものであり、この第４図
の回路の動作は上記に説明したものと同一である
ので省略するが、微調整用の検出回路２５に入力
されるＮ段分周回路の出力信号は120秒周期信号
であり、検出状態は、Q2，Q3，Q4，Q5，Q6，Q7
が「０」、「０」、「０」、「０」、「０」、「１」を
検出
しており、微調の最小ステツプは
１／16384×86400×１／120≒0.44秒／日
という値になる。この第４図に示すように粗調整
と微調整を各々単独に調整可能な構成も容易に実
現する事ができる。この第４図で２４は、リゼツ
ト・セツト端子付1/2分周回路であり、２８，２
９は粗調整用の書き込みデーターと微調整用の書
き込みデーターが扱われるため、AND−ORゲー
ト構成となる。 In addition to the embodiment shown in FIG. 2, FIG. 4 shows setting terminals 19, 20, 21, 2 for fine adjustment.
The operation of the circuit shown in FIG. 4 is the same as that explained above, so it will be omitted, but the N stages input to the detection circuit 25 for fine adjustment will be omitted. The output signal of the circuit is a 120 second periodic signal, and the detection states are Q 2 , Q 3 , Q 4 , Q 5 , Q 6 , Q 7
detects "0", "0", "0", "0", "0", and "1", and the minimum fine adjustment step is 1/16384 x 86400 x 1/120 ≒ 0.44 seconds/day. Becomes a value. As shown in FIG. 4, a configuration in which coarse adjustment and fine adjustment can be adjusted independently can also be easily realized. In this figure, 24 is a 1/2 frequency divider circuit with reset/set terminals, and 28, 2
9 handles write data for coarse adjustment and write data for fine adjustment, so it has an AND-OR gate configuration.
本考案の回路構成では、分周段に設定するデー
ターを決定する設定端子は、上記に説明した方式
だけでなく、色々な形を取る事ができる。例えば
第６図に示す回転式のスイツチで状態を決めても
良いし、設定用カウンターを設け、その出力を設
定端子としても良い。又、第５図に示すように設
定端子１１，１２，１３の状態を、コード変換回
路を通して、その出力で状態を決定しても同様に
可能であり、分周段にデーターを書き込むタイミ
ングを決定する検出回路の分周段検出状態も、必
要に応じて自由に変更する事が可能である。 In the circuit configuration of the present invention, the setting terminal that determines the data to be set in the frequency dividing stage can take various forms in addition to the method described above. For example, the state may be determined by a rotary switch shown in FIG. 6, or a setting counter may be provided and its output may be used as a setting terminal. Furthermore, as shown in Fig. 5, it is also possible to determine the states of the setting terminals 11, 12, and 13 by passing them through a code conversion circuit and using the output thereof, and determining the timing at which data is written to the frequency dividing stage. The detection state of the frequency division stage of the detection circuit can also be changed freely as necessary.
以上、説明したように本考案を採用すれば、基
準発振回路には何ら影響を与えずに容易に高精度
の電子時計を実現する事ができ、回路構成は、従
来の分周段の内、必要な段数だけプリセツト機構
を設け、書き込み制御回路、検出回路と設定端子
の追加という簡単な回路構成によつて実現でき、
電子時計の高精度化の実現に対して、大きな利点
をもたらすものである。また、本願考案はプリセ
ツト機構が論理１のみを書き込めば良く、論理φ
は書き込まなくても良いので非常に簡単であり、
また検出も１ビツトの検出で可能となるため構成
が簡単であるという効果も有する。 As explained above, by adopting the present invention, it is possible to easily realize a high-precision electronic clock without affecting the reference oscillation circuit, and the circuit configuration is based on the conventional frequency dividing stage. This can be achieved with a simple circuit configuration by providing the required number of preset mechanisms and adding a write control circuit, detection circuit, and setting terminal.
This brings great advantages to the realization of high precision electronic watches. In addition, in the present invention, the preset mechanism only needs to write logic 1, and logic φ
is very easy as there is no need to write it,
Furthermore, since detection is possible by detecting one bit, the configuration is simple.
そして、Q2，Q3のプリセツトデーターにより
緩急量が決まつており、進み、遅ねはQ4をリセ
ツトすると遅れ方向の修正になり、なにもしない
と進み方向の修正になる。このように、進み方向
または遅れ方向の修正をするためには、リセツト
する回路だけで実現できる。また、例えばプリセ
ツトされる分周段のＱ出力が全て０であることを
検出した時に、設定端子に設定されているデータ
ーをプリセツトする構成にすれば、分周段をリセ
ツトする必要がない。よつて、非常に回路構成が
簡単であるという効果も有する。 The preset data of Q 2 and Q 3 determines the amount of speed and speed, and resetting Q 4 will cause a correction in the direction of lag, and if nothing is done, it will be a correction in the direction of advance. In this way, correction in the advance direction or the delay direction can be realized using only a reset circuit. Further, if the configuration is such that, for example, when it is detected that the Q outputs of the frequency dividing stage to be preset are all 0, the data set in the setting terminal is preset, there is no need to reset the frequency dividing stage. Therefore, it also has the effect that the circuit configuration is extremely simple.
さらに、本願考案は計時動作からデーターを書
き込むタイミングまでは確実に１クロツク以上離
れているので、データーの書き込み・プリセツト
は計時処理する回路に何ら悪影響を及ぼすもので
はないので、非常に信頼性の高い緩急調整を行え
るという効果も有するものである。 Furthermore, in the present invention, there is definitely a gap of at least one clock from the time measurement operation to the timing at which data is written, so data writing and presetting do not have any negative effect on the circuit that performs time measurement processing, making it extremely reliable. It also has the effect of being able to adjust the speed and speed.
第１図…従来の発振回路、第２図…本考案によ
る一実施例、第３図…第２図分周段７，８の出力
論理状態表、第４図…粗調整を行う回路の実施
例。
１……可変コンデンサー、２……発振用コンデ
ンサー、３……水晶振動子、４……コンデンサ
ー、５……発振回路、６……1/2分周回路、７…
…セツト端子付1/2分周回路、８……リセツト端
子付1/2分周回路、９……Ｎ段分周回路、１０…
…検出回路、１１，１２，１３……設定端子、１
４……ラツチ回路、１５，１６，１７，１８……
ANDゲート、１９，２０，２１，２２，２３…
…設定端子、２４……セツト・リセツト端子付1/
２分周回路、２５……検出回路、２６……ラツチ
回路、２７，３０，３１，３２……ANDゲート、
２８，２９……AND−ORゲート。
第５図ａ…設定端子の状態をコード変換して使
用する場合の実施例、第５図ｂ…第５図ａのコー
ド変換の真理値表、第６図…回転式スイツチによ
り設定端子状態を決める実施例。
３３……コード変換回路、３４……回転式スイ
ツチ。
第７図…セツト端子付1/2分周回路の一例。
３５……クロツクドインバーター、３６……
NORゲート、３７……インバーター。
Fig. 1: Conventional oscillation circuit, Fig. 2: An embodiment according to the present invention, Fig. 3: Fig. 2: Output logic state table of frequency dividing stages 7 and 8, Fig. 4: Implementation of circuit for coarse adjustment example. 1... Variable capacitor, 2... Oscillation capacitor, 3... Crystal resonator, 4... Capacitor, 5... Oscillation circuit, 6... 1/2 frequency dividing circuit, 7...
...1/2 frequency divider circuit with set terminal, 8...1/2 frequency divider circuit with reset terminal, 9...N stage frequency divider circuit, 10...
...Detection circuit, 11, 12, 13...Setting terminal, 1
4...Latch circuit, 15, 16, 17, 18...
AND gate, 19, 20, 21, 22, 23...
...setting terminal, 24...with set/reset terminal 1/
2 frequency divider circuit, 25...detection circuit, 26...latch circuit, 27, 30, 31, 32...AND gate,
28, 29...AND-OR gate. Fig. 5a...Example when the setting terminal state is used after converting the code, Fig. 5b...Truth table for code conversion of Fig. 5a, Fig. 6...Setting terminal state is changed using a rotary switch. Examples to decide. 33...Code conversion circuit, 34...Rotary switch. Figure 7: An example of a 1/2 divider circuit with a set terminal. 35...Clocked inverter, 36...
NOR gate, 37...inverter.
Claims (1)
回路から出力される前記時間基準信号を分周す
る分周回路及び前記分周回路からの出力信号に
より計時機構を駆動する電子時計において、 (b) 前記分周回路からの出力信号に基づき緩急量
及び緩急方向を前記分周回路へ設定するタイミ
ングを決定する検出出力信号を出力する検出回
路と、 (c) 前記検出回路からの前記検出出力信号に応じ
て前記分周回路へ前記緩急量及び前記緩急方向
を設定するゲート手段とを有し、 (d) 前記分周回路は、設定端子に設定された前記
分周回路の前記緩急量を決定するデーターをプ
リセツトする機構を持つ少なくとも２段以上の
分周段からなる第１分周段と、前記第１分周段
よりも後段に接続され、前記分周回路の前記緩
急方向を進みの方向または遅れの方向に設定す
る第２分周段とからなり、 (e) 前記検出回路は、前記第２分周段よりも後段
に接続された任意分周段からの第１の状態の出
力信号により初期状態となり、前記第１の状態
とは反対の第２の状態の出力信号により検出信
号待期状態となり、かつ前記検出信号待期状態
となつてから最初の前記第２分周段からの第１
の状態の出力信号を検出し前記検出出力信号を
出力する構成であり、 (f) 前記ゲート手段は、前記検出出力信号に応じ
て前記第１分周段に前記緩急量を決定するデー
タをプリセツトし、かつ前記第２分周段に前記
緩急方向を設定する構成であることを特徴とす
る電子時計。[Claims for Utility Model Registration] (a) An oscillator circuit that outputs a time reference signal, a frequency divider circuit that divides the frequency of the time reference signal output from the oscillation circuit, and a timekeeping mechanism using the output signal from the frequency divider circuit. (b) a detection circuit that outputs a detection output signal that determines the timing for setting the adjustment amount and the adjustment direction to the frequency division circuit based on the output signal from the frequency division circuit; (c) (d) the frequency dividing circuit has a gate means for setting the adjustment amount and the adjustment direction to the frequency division circuit in accordance with the detection output signal from the detection circuit; a first frequency dividing stage consisting of at least two or more frequency dividing stages having a mechanism for presetting data for determining the adjustment amount of the frequency dividing circuit; and a second frequency division stage that sets the speed/slow direction of the circuit to an advance direction or a delay direction, (e) the detection circuit includes an arbitrary frequency division stage connected to a stage subsequent to the second frequency division stage. The state is set to the initial state by the output signal of the first state from the first state, the state is set to the detection signal waiting state by the output signal of the second state opposite to the first state, and the first state is set after the state is set to the detection signal waiting state. from said second divider stage of
(f) The gate means presets data for determining the adjustment amount in the first frequency dividing stage according to the detection output signal. An electronic timepiece characterized in that the speeding and slowing direction is set in the second frequency dividing stage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986072888U JPS6336752Y2 (en) | 1986-05-15 | 1986-05-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986072888U JPS6336752Y2 (en) | 1986-05-15 | 1986-05-15 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS621437U JPS621437U (en) | 1987-01-07 |
| JPS6336752Y2 true JPS6336752Y2 (en) | 1988-09-29 |
Family
ID=30611726
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986072888U Expired JPS6336752Y2 (en) | 1986-05-15 | 1986-05-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6336752Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011237239A (en) * | 2010-05-10 | 2011-11-24 | Seiko Epson Corp | Electronic apparatus with timer function and control method of the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5174670A (en) * | 1974-12-23 | 1976-06-28 | Seiko Instr & Electronics | |
| JPS5181165A (en) * | 1975-01-13 | 1976-07-15 | Suwa Seikosha Kk |
-
1986
- 1986-05-15 JP JP1986072888U patent/JPS6336752Y2/ja not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5174670A (en) * | 1974-12-23 | 1976-06-28 | Seiko Instr & Electronics | |
| JPS5181165A (en) * | 1975-01-13 | 1976-07-15 | Suwa Seikosha Kk |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011237239A (en) * | 2010-05-10 | 2011-11-24 | Seiko Epson Corp | Electronic apparatus with timer function and control method of the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS621437U (en) | 1987-01-07 |
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