JPS6336347A - Data buffer circuit - Google Patents

Abstract

PURPOSE:To control an input/output device that makes 1 byte width data transfer and an input/output device that makes 2 byte width data transfer by one input/output control device by providing a byte width changing means and a byte width change instruction means. CONSTITUTION:A byte width changing means 1A consists of selectors 12, 13 that make switching of data transfer according to an instruction of a byte width change instruction means 1B, a register that accumulates input data while shifting them successively, a driver 16 that sends out data to bus in bus 3, and a receiver 17 that receives data from bus out bus 4. Inputted and outputted data having specified byte width are stored successively in the register and data having byte width having byte width of specified times are inputted and outputted. The byte width change instruction means 1B issues an instruction whether intermediation of supplying and receiving of data is to be made while changing byte width by the byte width changing means or intermediation of supplying and receiving of data is to be made without changing byte width of data.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Use] The present invention relates to a data buffer circuit that is interposed between a higher-level device and a lower-level device and mediates the exchange of data by storing temporary data.

[Conventional technology]

FIG. 4 is a diagram showing a conventional data buffer circuit.
In the figure, 1 is a data buffer circuit that temporarily stores data and mediates the exchange of data, 2a is an input/output device as a lower-level device, 2b is an input-output control device as a higher-level device, and 3 is from the input/output device 2a. 4 is a bus-out bus for outputting data from the data buffer circuit 1 to the input/output device 2a, and 5 is a bus-in bus for outputting data from the data buffer circuit 1 to the data buffer circuit 1 via the pass-in bus 3. A receiver receives input data, and 6 is a bus out bus 4 from the data buffer circuit 1.
7 is a read data bus for sending data from the input/output device 2a to the input/output control device 2b as a host device, and 8 is the input/output control device 2b. A write data bus for sending data from to the input/output device 2a; 9 is the input/output device 2a;
a selector that switches data transfer depending on whether data sent from the input/output control device 2b is outputted to the input/output control device 2b or data sent from the input/output control device 2b is outputted to the input/output device 2a as a lower device; 10.1
1 is a register for temporarily storing data in case X.

Next, we will discuss the operation.

Input/output control device 2 as a higher-level device than input/output device 2a
During read data transfer, which is data transfer to bus 3. Receiver 5. It is transmitted through the selector 9 and set in the register 10 by a data transfer request signal from the input/output device 2a.

If register 11 is empty, the data will be transferred to register 1 immediately.
It is set to 1 and transmitted to the read data bus 7 and sent to the input/output control device 2b as a host device.

During write data transfer, which is data transfer from the host device to the input/output device 2a, the data is transferred to the write data bus 8. The data passes through the selector 9 and is set in the register 11 via the register 10 if the registers 10 and 11 are empty.

When there is a data transfer request from the input/output device 2a, the data in the register 11 is transmitted to the input/output device 2 via the driver 6 and the bus-out bus 4. If in this case register 1
If there is data in 0, it is moved to register 11. At the same time, if there is data on the write delta bus, it passes through the selector 9 and is set in the register IO.

[Problem that the invention seeks to solve]

Since the conventional data buffer circuit is configured as described above, the data transfer between the data buffer circuit and the input/output device is, for example, if 1-byte-wide data is input/output, 1-byte-wide data is transferred. There was a problem that only one person could do.

This invention was made to solve the above-mentioned problems, and it is possible to transfer 2-byte-wide data even if 1-byte-wide data is manually transferred, and it is also possible to transfer 1-byte-wide data by hand. The object of the present invention is to obtain a data buffer circuit capable of switching between 2-byte data transfer and data transfer.

[Means for solving problems]

Therefore, the data buffer circuit 1 according to the present invention sequentially stores input/output data having a predetermined byte width in a register, and inputs/outputs data having a predetermined number of byte widths of the predetermined byte width. Width conversion means 4A,
Byte width change instruction means IB for instructing whether to mediate data exchange by changing the byte width of data by byte width conversion means IA, or mediate data exchange without changing the byte width of data; It is characterized by having the following.

[Effect]

The byte width conversion means IA in this invention manually stores data of a predetermined byte width in a 1m-order register, and when outputting data, outputs it as data having a byte width that is a predetermined number of times the byte width of the input data. do. in this case,
The byte width change instruction means IB is the byte width conversion means IA.
This instructs whether to change the byte width of the data or output it without changing the byte width.

〔Example〕

FIG. 1 is a diagram showing an embodiment of the present invention.
11 is the same component as the conventional one, and IA is a byte width for sequentially storing input/output data having a predetermined byte width in a register and inputting/outputting data having a predetermined number of byte widths of the above predetermined byte width. The conversion means, 1B, is a byte width change that instructs whether to change the byte width of data and mediate data exchange by using a byte width conversion means, or to mediate data exchange without changing the data byte width. It is a means of instruction.

Here, the byte width conversion means IA includes selectors 12 and 13 that switch data transfer according to instructions from the byte width change instruction means IB, a register that sequentially shifts and accumulates input data, and a register that stores input data while sequentially shifting it, and a register that stores input data while sequentially shifting it. A driver 16 and a bus out bus 4 that receive incoming data.
and a receiver 17 that sends data to.

Next, the byte width of the data input to the data buffer circuit 1 is 1 byte, and the byte width of the data output from the data buffer circuit 1 is 2 bytes that is a predetermined number of times the above 1 byte or the same byte as the above 1 byte. An example will be explained in which the byte width change instructing means IB instructs whether to change the byte width.

During a write operation, which is data transfer from a higher-level device to a lower-level device, when data arrives on the write data bus 8, it passes through the selector 9 and is set in the register 10. Note that the selector 9 faces the write data bus 8 side for write operation, the selector 12 faces the register 10 side, and the selector 13 faces the register 14 side. When the k-timeta 14 is empty, the data in the register 10 is automatically set in the register 14 via the selector 12.

When data arrives on the write data bus 8 again, if the register 10 is empty, it is set again.

At this time, register 14. Since data is set in register 10, the data in register 14 is set in register 15 via selector 13, the data in register 10 is set in register 11, and if register 11 and register 15 are empty, they are set simultaneously. .

In this way, the data arriving on the write data bus 8 is shifted and set one after another if there is space in each register of the data buffer circuit 1.

However, if there is no free space in the data buffer circuit 1, the incoming data is transferred to the write data bus 8 again.

When there is a data transfer request from the input/output device 2a, the data in the registers 11.15 passes through the drivers 6.16 and is transferred to the bus out buses 4. Two bytes are transferred to the input/output device 2a via the bus-in-bus 3. At this time, register 10.
If there is data in register 14, each data is stored in register 1.
1.15, and if there is data on the write data bus 8, that data is also set in the register 10.

In this manner, 2-byte data is transferred between the data buffer circuit 1 and the input/output device 2a.

FIG. 2 shows a transition diagram of the operational flow of data transferred from the higher-level device to the lower-level device described above.

In FIG. 2, data A arrives on the write data bus 8 at time 1+, next data B arrives at time t2, and data A is set in the register 10. In this way, time t31 +4
．． After t+;+ +6, data A and B are transferred to the pass-in bus 3. The process of being sent to the bus-out bus 4 is shown.

Next, a read operation, which is data transfer from a lower-level device to a higher-level device, will be described.

When a data transfer request is received from the input/output device 2a, 2 bytes of data arrive on the pass-in bus 3 and the bus-out bus 4. During a read operation, selector 12 faces receiver 5, selector 9 faces receiver 17, and data on pass-in bus 3 and bus-out bus 4 are set in registers 14 and 10, respectively. Driver Hi, 16
is disabled. At this time, if registers 11 and 15 are empty, the data in register 14 will be transferred to selector 1.
3, the data in register 15 and register 10 are simultaneously set in register 11.

Next, the data in register 15 is sent to +7- data bus 7, and at the same time the data in register 11 is sent to selector 13.
It is set in register 15 through . The selector 13 faces toward the register 11 when there is data in the register 11.

In this way, 2-byte wide data from the input/output device 2a is transferred one byte at a time to the input/output control device 2b as a host device.

FIG. 3 illustrates the operational flow of data transferred from the lower-level device to the higher-level device described above. In FIG. 3, data A is sent to the pass-in bus 3 and the bus-out bus 4 along with a data transfer request at time L1.

B arrives at time t2. +3. +4. +5 and the data is sent to the read data bus 7 as A and B.

Next, a case where the byte width change instruction means IB indicates 1 byte width will be described.

During a write operation, when data arrives on the write data bus 8, it is set in the register 10 and then in the register 11. For data transfer during 1 byte, register 1
4.15 is not working and driver 16 is also disabled.

When a data transfer request comes from the input/output device 2a, register 1
1 data passes through driver 6 and bus out bus 4.
is sent to the input/output device.

If there is data in register 10 at this time, that data is moved to register 11. If there is data on the write data bus 8, it passes through the selector 9 and is set in the register 10. In this way, 1-byte data is transferred to the input/output device 2a.

Next, the read operation will be described.

In this case, the byte width change instruction means IB indicates 1 byte width, so registers 10 and 11 and driver 16 do not work. Further, the selector 13 faces the register 14.

When data arrives at the bus-in-bus 3 along with a data transfer request from the input/output device 2a, it reaches the selector 12 via the receiver 5 and is set in the register 14. If the register 15 is empty, the data in the register 14 immediately passes through the selector 13, is set in the register 15, and is sent to the read data bus 7. In this way, 1-byte width data transfer from the input/output device 2a is performed.

The byte width change instruction means IB is a launch where the microprogram in the input/output control device 2b checks whether the input/output device transfers 1-byte or 2-byte data, and resets the data before transferring the data. .

Note that in the above embodiment, the device is provided to transfer data between the input/output control device and the input/output device, but it may be provided between the input/output control device and a channel that is a higher-level device thereof. .

〔Effect of the invention〕

As described above, according to the present invention, the data buffer circuit sequentially stores input/output data having a predetermined byte width in a register, and inputs/outputs data having a byte width multiple times the predetermined byte width. a byte width conversion means to change the byte width of data, and a byte that instructs whether to mediate data exchange by changing the byte width of data by the byte width conversion means, or to mediate data exchange without changing the byte width of data. Since the width change instruction means is provided, one input/output control device can control an input/output device that transfers data in 1 byte width and an input/output device that transfers 2-byte width data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the operational flow of a write operation for transferring data from a higher-level device to a lower-level device, and FIG. A diagram showing the operation flow of a read operation to transfer,
FIG. 4 is a block diagram of a conventional data buffer circuit. 1... Data buffer circuit, 2a... Input/output device (
lower order device), 2b... input/output control device (upper order device),
6.16...Driver, 5゜17...Receiver, 1
0, 11, 14.15... register, 9, 12.13
...Selector, IA...Byte width conversion means, IB.
...Bite width change instruction means. Agent Masuyoshi Oiwa (and 2 others) Figures 3 and 4 Procedural amendments (self-initiated, Showa year, month, day) 5 Data buffer circuit 3, relationship to the case of the person making the amendments Patent applicant address Chiyoda, Tokyo 2-2-3 Marunouchi Ward Name (601) Mitsubishi Electric Corporation Representative Shiki
Moriya 4, agent address: Mitsubishi Electric Corporation, 2-2-3 Marunouchi, Chiyoda-ku, Tokyo 242. -1 name (7375
) Patent attorney Masudai Oiwa, ゛, -2゜ (Contact number 03 (213)
3421 Patent Division) 5. Column for detailed explanation of the invention subject to amendment. 6. Contents of correction (1) In light 11, page 2, line 9, “Data buffer circuit 1
The phrase "to the data buffer circuit l" should be corrected to "to the data buffer circuit l." (2) On page 6, line 17 of the same book, the phrase ``Receives data sent from Bus-in-Bus 3'' is changed to [Bus-in-Bus 3
[Send data]]. (3) Same book, page 6, line 18 to line 1, line 19 [lotus 7'
The phrase ``sends data to bus 4'' is corrected to ``receives data from bus 4''. (4) In the 5th line of page 12 of the same book, "input/output device" is corrected to "input/output device."that's all

Claims (1)

[Claims] When exchanging data between a higher-level device and a lower-level device,
In the data buffer circuit that mediates the transfer of data by intervening between the higher-level device and the lower-level device by accumulating temporary data, the data buffer circuit stores data having a predetermined byte width to be input/output. a byte width conversion means for inputting and outputting data having a byte width a predetermined number of times the predetermined byte width by sequentially storing the data in a register; and a byte width conversion means for changing the byte width of the data to mediate data exchange. 1. A data buffer circuit comprising byte width change instructing means for instructing whether to perform an intermediary transfer of data without changing the byte width of the data.