JPS6336114A - Electronic interface device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention provides a sensor that is arranged between a sensor with an analog output section for detecting a physical quantity and a display unit that displays the value of the physical quantity. an electronic interface device for comparing the amplitudes of the signals at the outputs of the control generator and the sensor with an analog output for controlling the display unit; The present invention relates to an electronic interface device comprising an analog amplitude comparator for controlling the controlled generator.

Such a device is suitable for use in a vehicle, etc., and includes, for example, a fuel level sensor in a vehicle's fuel tank and a display attached to a dash board.
Suitable as a device placed between the unit.

PRIOR ART A device of the above type is already known from US Pat. No. 3,983,549.

In this type of device, a controlled generator is equipped with an oscillator, a shaping circuit, a counter, a digital-to-analog converter, and a memory. This controlled generator is adapted to send out a monotonically increasing signal, and when the value of the output signal of the control generator is the same as the value of the output signal of the sensor, the output signal of the control generator is frozen. A prohibition input section (memory in the above device) is provided.

This device has a structure that controls the sampling of the sensor's output signal periodically, and the display unit continuously displays a value equal to the sampling value of the sensor's output signal. There is.

However, such devices have the disadvantage that they are not designed to attenuate rapid barasite fluctuations that can affect physical quantities. In this case, the physical quantity mentioned above is the fuel level in the vehicle's fuel tank, and the rapid fluctuations in the sensor output signal caused by the oscillation of the fuel in the tank as the vehicle moves are not attenuated. , a display unit designed to represent the average level of the tank cannot provide a stable display value.

In order to avoid providing incorrect display values when the vehicle is tilted, the device of U.S. Pat. No. 3,983,549 prohibits updating of the display contents when the vehicle is tilted. However, even in this case, there is no signal averaging effect at the output of the sensor, so the displayed value cannot reliably represent the average fuel level. An interface device for further averaging is described in French patent application no. 8519396 by the applicant. In this device, rapid barasite fluctuations in the sensor's output signal are attenuated by a low-pass analog filter using resistors and capacitors. Considering the relatively high time constant of the filter used, it is necessary to use a large capacitor;
This increases cost and occupies more space. Furthermore, it may be desirable to temporarily change the filter parameters in order to make the operating state of the device more complete, in particular by reducing the time constant for the time following the vehicle switch-off, for example. It is also possible to make the display unit provide accurate display quickly, but this would require more relays, further increasing the cost and space occupancy of the device. To overcome these drawbacks, the analog filter described above can also be replaced by a digital filter, in which case a filtering capacitor is no longer required, thereby increasing the flexibility of use. Such an arrangement is described in British patent application GB-A-2100487 and West German patent application DE-A-2849066, in which an analog-to-digital converter is provided at the input section and an analog-to-digital converter is provided at the output section J. A digital-to-analog converter is provided, as well as a plurality of digital comparators and a number of digital processing circuits between the converters. Such devices suffer from the drawbacks of being complex, requiring a large number of components, or requiring a significant amount of semiconductor device area in the assembled state (if formed on a single substrate). be.

The present invention overcomes the above-mentioned drawbacks and provides an apparatus that can attenuate rapid variations in physical quantities due to the averaging effect, and does not require high-capacitance capacitors or complex digital processing circuits.

(Structure of the Invention) In order to achieve the above object, in the device of the present invention, the control type generator is provided with a binary control input section for controlling the increase/decrease of the output signal, and a first up/down counter for the clock and the first clock signal is provided. wherein the binary output signal of the comparator controls up and down counts of the first up/down counter, and the binary code signal of the first up/down counter controls increase/decrease of the output signal of the generator. It is characterized by

In the device of the invention, an up-down counter filters and integrates the rapid parasite fluctuations that affect the output signal of the sensor. This has the same function as a conventional analog filter capacitor, but it is much simpler than a typical digital filter.

providing controlled means for controlling said generator;
It is preferable to send out a monotonically changing signal with its direction and speed controlled.

In this case, if necessary, an accurate display value can be quickly obtained by controlling the monotonic fluctuations of the generator's output signal at high speed until the generator's output signal becomes the same as the sensor's output signal. . This feature can be achieved, for example, by filling a tank and determining the level without having to wait for a relatively long time for the time constant of the integration performed by the first up-down counter (which then temporarily goes out of action). Effective when trying to know.

In a first embodiment of the invention, a first up-down counter having means for causing said controlled generator to generate a first pulse train, a first up-down counter having a block input for receiving said first pulse train; and a digital-to-analog converter connected to the digital output of the counter, such that the control input of the generator becomes an up-down counter control input of the second up-down counter.

A generator of the above structure can be integrated onto a relatively small semiconductor surface.

In a second embodiment, said physical quantity is the level of fuel in a vehicle, and said controlled generator generates a first pulse train of controlled repetition frequency controlled by said signed output of said first up-down counter. a second up-down counter having a clock input for receiving said first pulse train and an up-down counting control input connected to a potential for ensuring down counting control while the vehicle is running; The configuration includes a digital-to-analog converter connected to the digital output section of the up-down counter.

In this embodiment, when the vehicle is running, the second up-down counter is controlled for down counting and its digital output can only decrease.

Therefore, if desired, there is no need to provide special circuitry to disable the increase during vehicle changes; even then, the displayed value seen by the driver does not increase, and the average fuel level will only decrease. Particularly when the vehicle suddenly changes direction, such an increase may actually occur due to the barascite effect, so in the case of the first embodiment, such an increase is prevented. It is necessary to prevent this from being transmitted to the display unit.

and the physical quantity is the fuel level of the vehicle, and the vehicle is equipped with another sensor in the form of an electronic tachometer and a flow meter, and the another sensor generates the second pulse train. Preferably, the means for generating the first pulse train is configured such that the repetition frequency of the first pulse train is a linear function of the repetition frequency of the second pulse train. .

As a result, as the moving speed of the vehicle increases and the amount of fuel consumed increases, the display value is updated at a higher rate.

(Embodiments) Next, two embodiments of the interface device according to the present invention will be described based on the drawings.

In FIG. 1, an electrical interface device (interface) is arranged between a sensor for sensing a physical quantity and a display unit. In the embodiment, the display is provided in a motor vehicle to display the amount of fuel remaining in the fuel tank.

A level sensor, not shown as it is of known construction, is mounted on the fuel tank and is adapted to send an analog electrical signal EA representative of the fuel level in the fuel tank to a first input of the interface.

Further sensors, such as electronic tachometers or flow meters (not shown as they are of well known construction), are also provided, from which a pulse train CTE/D is supplied to a second input of the interface.
It is designed to send M.

The repetition frequency of the pulse train increases as the engine speed increases and the instantaneous fuel consumption increases.

The binary signal APC is a signal formed in a manner known in the art, which is at a low level while the ignition of the vehicle is not switched on and is at a high level when the ignition of the vehicle is switched on. It is configured to be sent to the input section.

Additionally, although detailed construction is well known and therefore not shown for ease of explanation and illustration, all electronic circuits and elements of the interface are always powered by the vehicle's battery and such The power supply continues even when the vehicle is stopped and the ignition is switched off. The interface is made of an integrated circuit using CMO3 technology, which consumes very little power, so even if you keep it powered all the time, the battery will never run out.

When the interface is powered, the aforementioned signal EA is applied to its three inputs.

Signals 5ASSN, AC are delivered from three outputs of the interface in response to CTE/DM, APC. As will be explained in detail later, the signal SA is an analog signal and is used to control an analog input display unit, for example of the moving coil type. Signal SN is a digital signal and is used, for example, to control a 7-segment type digital display unit. Signal AC is a signal for supplying power to the tank level sensor.

Next, the configuration of the interface will be explained. An input receiving the signal APC is connected to a time base 200. In the example, time base 200 includes six binary clock signals HA, HBSHC, H having six different frequencies.
D, HE, HF and 5 binary signals ACSTM
,C,DRV.

TRV is sent out, and their temporal changes are related to the signal APC as described below.

The input receiving the signal EA is the "+" input of an analog amplitude comparator 1, whose "-" input is connected to the output delivering the signal SA.

The first up/down counter 2 receives a clock signal H
A tarlock input receives the signal A, a reset input receives the signal C, an up/down count control input receives the binary output signal SC of the comparator, and an output for the binary signal SI.

The divider circuit 300 with shift is provided with three input sections, and they are connected to a clock signal IC and a clock signal H.
E and the signal CTE/DM,
Also provided is an output section for sending out the signal SDD. Signal SD
D is a pulse train whose repetition frequency f is the signal CTE
/DM repetition DD frequency f. It is a linear function of TE/DM, and in the illustrated embodiment, the relationship is as follows.

fSDD″″ 1/N (fCTE/DM−fHC) In the above formula, N is a natural integer, and fHC is the frequency of the clock signal HC.

The switching circuit 100 receives a signal C55C.

There are five inputs receiving S L HB, SDD and two outputs delivering signals 5CCD, SAC. As will be explained later, the output section that sends out the signal 5CCD can be selectively switched between an input section that receives the signal SC and an input section that receives the signal SI, and similarly, the output section that sends out the signal SAC can be switched between an input section that receives the signal SC and an input section that receives the signal SI. part and signal SD
It is possible to alternatively and directly switch to an input receiving D.

The second up/down counter 3 includes a clock input section that receives the signal SAC, a reset input section that receives the signal C, an up/down count control input section that receives the signal 5CCD, and a digital signal SNC that will be described later. A (parallel) digital input section and a (parallel in the embodiment) digital output section are provided for sending the digital signal SNA onto the parallel bus.

The digital-to-analog converter 4 has a (parallel in the embodiment) digital input for receiving the signal SNA and a signal SA.
An analog output section is provided to send out the .

Fuel increase/decrease detection and barasite increase blocking circuit 4
00 has three binary inputs receiving the signal TMSDRVSTRV, a (parallel in the embodiment) digital input receiving the signal SNA, and the aforementioned digital signal SNC.
and two digital output sections (parallel in the embodiment) for sending out the digital signal SNB. Above signal S
The output of the NC is connected to the parallel digital input of the second up/down counter 3.

Furthermore, the scale factor adaptation circuit 500 is provided with two binary inputs for receiving the tarok signals HD and HF, a (parallel) digital input for receiving the signal SNB, and a (parallel) digital output for sending out the signal SN. be.

Before explaining the above-mentioned circuit in more detail, the operation of each part of the above-mentioned interface except for the increase/decrease detection and parasite increase blocking circuit 400 and the scale factor adaptation circuit 500 will be explained.

In FIG. 5, the rising edge of the signal APC means that the vehicle's ignition has been switched on, and in response to this signal the time base 200 changes the signal AC to a high level, thereby causing the level sensor is energized and causes the signal C to briefly change to a high level, thereby forming a pulse called a conversion pulse (so called for reasons explained below). The conversion pulse of signal C resets the up-down counter 2.3 and also sends a command to the switching circuit 100 to switch the sending output of signal 5CCD to the receiving input of signal SC and
The sending output section of C is switched to the receiving input section of signal HD. Since the up/down counter 3 is reset immediately after the conversion pulse C, the signals SNA and SA become O.

Signal EA is positive because the level sensor is powered, so signal SC is at a high level. Therefore, the signal 5CCD is at a high level, and the up/down counter 3 counts the pulses of the signal sAc, ie, the signal HB.

Digital signal SNA and analog signal SA are signal SA
The output signal SC of the comparator simply changes in an upward direction at a rate controlled by the frequency of the clock signal HB until it reaches a low level, with EA equal to the signal EA. In fact, at that point, the switching circuit 100, in response to the falling edge of the signal SC, switches the output delivering the signal 5CCD to the input receiving the signal Sl, and the output delivering the signal SAC to the input receiving the signal SDD. Switch to the receiving input section. Furthermore, as will be described later, the pulse repetition frequency of the signal SDD is very small compared to the pulse repetition frequency of the signal HB, and the signals SNA and SA change very slowly without being affected. Next (actually, instantaneously as described below)
a state signal SNA representative of the fuel level in the tank immediately after the conversion has taken place and the ignition has been switched on;
SA is obtained. In the embodiment, the digital-to-analog converter 4 is an 8-bit converter and therefore has 256 levels, and the frequency of the clock signal HB is 256.
It is 011z. This conversion takes place over a period of 10 seconds when the tank is full, and otherwise takes place over a period of less than 10 seconds when there is fuel remaining.

In the exemplary embodiment, the clock frequency of the signal HA is 10 Hz, so that during the switching time the up/down counter 2 counts at most one pulse.

While the vehicle is running, the fuel in the tank fluctuates, so signal EA
is affected by rapid barasite fluctuations, and its average value changes relatively slowly depending on engine fuel consumption. Signal SC is at a high level for positive variations of signal EA and is at a low level for negative variations. The signal SC is
Since the up-down counter 2 controls the up-counting and down-counting of the pulses of the signal HA, the signal of the value counted by the up-down counter 2 will change after a certain time.
It will represent the average variation of signal EA. In particular, if this signal is negative, because of the average, the signal EA will then remain less than the signal SA as it decreases. This is obtained from the signal SI. The signal SI is obtained by recopying the signal 5CCD, and the second up-down counter 3 controls the up-counting and down-counting of the pulses of the signal SAC, and therefore controls the increase and decrease of the signals SNA and SA. . Signal SAC echoes signal SDD, the repetition frequency of which is controlled by signal CTE/DM and corresponds approximately to one pulse every 20 minutes when the engine is idling and while the engine is running at maximum speed. corresponds to approximately 20 pulses every second.

Therefore, the drift of the signal SA increases as the engine speed increases, which allows it to be adjusted more rapidly as the fuel consumption rate increases.

The signal SNA or SA is determined depending on whether the display unit used is a digital type or an analog type, but the displayed value according to the signal SNA or SA follows the gradual level fluctuation of the tank, and in that case, the signal Rapid variations in the EA are not transmitted due to the accumulation effect (or averaging) of the first up-down counter. The reason why such a result is obtained is that the signal Sl of the sign of the value counted by the first up/down counter 2 controls the up counting or down counting of the second up/down counter 3. More specifically, the shift divider circuit 300, the up/down counter 3 and the digital-to-analog converter 4 connected in cascade form a controllable generator, which in the example embodiment displays via the signal SNA. It has an analog output for controlling the unit and for sending out a signal SA, which signal SA can be increased or decreased depending on the value of the signal applied to the binary up-down counting control input of the up-down counter 3; ,
This can be said to be because, in the exemplary embodiment, the output of the controllable generator receiving the signal SI becomes a binary input controlling the increase or decrease of the signal SA.

Similarly, the purpose of the switching circuit 100 is to perform rapid switching by controlling the aforementioned controllable generator to convert a monotonically varying signal (an increasing signal in the example) to the value of the clock frequency of the signal HB. The purpose is to send out at a speed controlled by.

Next, increase/decrease detection and barasite increase blocking circuit 4
00 and the scale factor adaptation circuit 500 will be described in detail.

During operation of the vehicle, the purpose of the circuit 400 is to deliver an output signal SNB equal to the signal SNA, except when the signal SNA increases due to balascite action alone, and this balascite increase Since it is not communicated on the SAB, the increase will not appear in the displayed value seen by the vehicle operator; he will only know that the average fuel level has decreased.

Circuit 500 adapts a scale factor to signal SNB so that the value displayed on the digital display unit downstream of circuit 500 will directly represent liters, British gallons, and US gallons.

Circuit 400 also performs other functions when the vehicle is stopped. When stopped, as shown in FIG. 5, the time base 200 maintains the signal AC at a high level for six seconds in the exemplary embodiment after the signal APC goes low, in other words, the ignition is switched off. The signal AC is maintained at a high level for 6 seconds. The level sensor is powered for 6 seconds after the vehicle is stopped. During this time (5 seconds after stopping in the example), the time base performs a rapid changeover by generating a signal C with the same pulse waveform as the signal generated when the ignition is switched on. The time base then directs the circuit 400 to generate a pulse-type signal TM, in the exemplary embodiment 6 seconds after the vehicle has stopped, and to store in an internal register the value SA obtained after the rapid changeover after the vehicle has stopped. Command. Then, while the vehicle is stationary for a period of time, the entire interface remains powered, as described above, without any negative impact on the vehicle's battery due to the low power consumption of the circuit. Of course, the display unit consumes a considerable amount of power, but when the vehicle is stopped the power supply to the display unit is cut off in a known manner.

While the vehicle is stopped, fuel may be supplied to or drained from the vehicle's fuel tank.

When the ignition is switched on again and the vehicle begins to move, the pulse of signal C causes a rapid changeover, as described above. Immediately after the pulse of signal C, the time base generates a pulsed signal DRV, which causes circuit 40
0 compares the current SNA value with the value stored in the internal register after the previous vehicle stop. If the two values are not equal, then fuel supply or discharge is occurring, in which case the time base is equal to the pulsed signal T immediately after the signal DRV.
When RV is generated, circuit 400 acts to generate signal SNB.
is the new value of the signal SNA. If no fuel supply or discharge is detected, the circuit 400 sets the signal SNC to the value of the signal SNB, thereby updating the value of the up/down counter 3. If the vehicle is parked on a slope, the value converted over 5 seconds after stopping is equal to the value at the time of starting, but such a value is incorrect for the value SNB obtained from the time average calculated during normal driving before parking. In such cases, the above features are beneficial.

In FIG. 2, a switching circuit 100 is provided with a general flip-flop 101. The flip-flop 101 is provided with an input section for receiving the signal C, a clear input section for receiving the signal SC, and an output section. The two logic switches 102, 103 are identical and each have a control input connected to the output of the flip-flop 101;
It has two signal input sections and a signal output section. Two signal inputs of switch 102 receive signals SC, SI, and its signal output delivers signal 5COD. Two signal inputs of switch 103 receive signal HBSSDD and output signal SAC from its output.

FIG. 3 shows a detailed configuration of the logic switch 102 as a circuit diagram. Two inputs of the AND gate 1022 correspond to a signal input and a control input. The two inputs of another AND gate 1023 correspond to another signal input and a control input which is inverted by an inverter 1024 .

The outputs of the AND gates 1022 and 1023 are connected to the inputs of the OR gate 1021.
The output section of is the output of the signal from the logic switch 102.

Switching circuit 100 functions as follows.

Flip-flop 101 delivers a high level at the control inputs of switches 102, 103 in response to the pulses of signal C, so that signal 5CCDSSAC each copies signal 5CSHB. flip flop 1
When the signal SC applied to the clear input of 01 goes low, the rapid conversion ends and the flip-flop 101
sends a low level to the control inputs of switches 102,103.

Each signal 5CCDSSAC performs a copy of the signal 5ISSDD.

In FIG. 4, the time base 200 includes a well-known clock 2.
01 is provided, the seven outputs of which deliver six clock signals HA, HBSHC, HD, HE, HF as well as a clock signal HG. Counter 203 counts pulses of clock signal HG. The combinary network 204 responds to the signal ATC and the parallel digital output of the counter 203 to generate a reset signal for the counter 203 and signals TM, C.

Sends out DRV, TRV, and AC. Since the combinary network 204 is conventionally well known, a detailed description thereof will be omitted.

Since the repetition frequency of the signal HG is several 11z, the time base 200 is adapted to perform a typical operation. The rising and falling edges of signal APC trigger a reset of counter 203 whose advance triggers different time delays via combinary network 204.

In FIG. 6, the shift divider circuit 300 has two
flip-flops 306 and 307 are provided. These flip-flops trip to the front side in the tarlock and also receive the signals CTE/DMSHC, respectively. The output of the flip-flop is connected to an OR gate 308, which in turn is connected to the clock input of a third up/down counter 309. The overflow output of counter 308 sends out signal SDD. The signal HE is sent to an inverter 301 and also to a frequency divider 302, where it is split into two and sent to the input of an OR gate 303. The other input of OR gate 303 receives signal HE2 at the output of divider 302. The output signal HE2'' of the OR gate 303 is supplied to the clock input of the flip-flop 307.

Signal HE and signal HE2 at the output of inverter 301 are supplied to AND gate 304. The output of the gate 1304 provides a signal H' which is applied to the tarlock input of flip-flop 306.

The signal HE2 is supplied to the reset input of the flip-flop 307 and also to the third up-down counter 309.
is sent to the up/down count control input of , and is also sent to the reset input of flip-flop 306 via inverter 305 .

Next, the operation of the shift divider circuit will be explained with reference to FIG.

The signal CTE/DM typically has a repetition frequency of several hundred Hz.
That's about it. As is clear from this, the clock signals HC have approximately the same size, and a signal with a higher frequency is selected as the signal HE, and in the embodiment, the frequency is set to several tens of kilometers Ilz. As is clear from the timing chart of the signals HE, HESHE2, H-1H'' shown in FIG. 7, the signal HC' at the output of the flip-flop 307 is a signal whose rising edge follows the rising edge of the signal HC. controlled by the first rising edge of H".

Similarly, the signal CTE/ at the output of flip-flop 306
DM'' is controlled by the first rising edge of signal H' whose rising edge follows the rising edge of signal CTE/DM. Note that the rising edges of signals H'', H- are always shifted in time. Considering, even if the rising edges of signals HC and CTE/DM coincide in time, the signal HC-1CTE/D
It is certain that the rising edge of M- has been shifted. The rising edges of the signals CH=, CTE/DM- correspond to the rising and falling edges of the signal HE2, respectively, but the pulses of the signal H1 and the pulses of the signal CTE/DM- do not overlap. Since the pulse of signal HC- always occurs when signal HC2 is at a low level, signal HE2 controls the down-counting of up-down counter 309, and this pulse is always down-counted. Similarly, signal CTE/DM- is always equal to signal HE2
This occurs when the signal CTE/DM- is at a high level.
pulses are always incremented. Therefore, after one second, the contents of the up-down counter 309 will be equal to the following equation.

fCTE/DM 'HC If the capacity of the up-down counter is N,
The overflow output section has a frequency f as shown in the following equation.
send out.

DD f -1/N(fCTE/DM-fHC) DD Therefore frequency f. T E / D M is shifted by fHC and divided by N or frequency fSD
D is the frequency f. It becomes a linear function of TE/DM.

For this purpose, the flip-flops 306, 307 and the OR gate 308 can be said to form a time multiplexing circuit with two inputs receiving the signal HCSCTE/DM and an output connecting the up/down counter 309. , and divider 302 and gate 301.3
03.304 controls the multiplexing circuit, and the signal CT
E/DM pulse upcounting and signal HC
It can be said that the up/down counter 309 is controlled to down-count the pulses of .

The result obtained in this way, namely the signal CTE/DM
A shifted division of the frequency of is particularly useful when the signal is delivered by an electronic tachometer, since the fuel consumption rate is not necessarily proportional to the rotational speed of the engine. Regarding that, the parameter N
By adjusting S fHc, the speed of consumption and compensation can be matched in a good manner.

In FIG. 8, an increase/decrease detection and parasite increase blocking circuit 400 is shown having three states, buffered between an input for receiving a parallel digital signal SNA and an output for delivering a parallel digital signal SNB. gate circuit 401 and output register 40
2 is provided. The circuit 400 further includes a digital comparator 408 which receives the digital signal SNA and also receives the digital signal SNB from the output register 402. The binary output of the comparator goes high when the value of the signal SNA is less than the value of the signal SNB and is connected to the input of the OR gate 407 at that level. The other input of gate 407 receives signal TRV. The output part of the OR gate 407 is connected to the input part of the AND gate 406, and the input part of the gate 406 is connected to the signal D obtained by inverting the signal DRV in the inverter 411.
Receive RV. The outputs of AND gates 406 control gate circuits 401 so that these gates remain high impedance gates with the output of AND gate 406 at a low level, and the outputs remain high impedance gates with the output of AND gate 406 at a high level. A signal SNA is written into the register 402.

The operation of the circuit described above is as follows. Most of the time, signal DRV is high and signal TRV is low. Writing the signal SNA to the output register 402 is only possible if the output signal of the comparator is at a high level, in other words, only when the value of the signal SNA is less than the value of the signal SNB. When the signal TRV or DRV goes high, such as after switching on the ignition, a different state occurs, as explained below. That is, comparator 408 and gates 407 and 406 output signals TRV and DRV.
The output register 402 and the gate circuit 401 prevent a value higher than the previously stored value from being stored.

Therefore, no balasite increase is transmitted by circuit 400.

Another gate circuit 405 is provided in the circuit 400 . The circuit 405 receives the digital signal SNA and is followed by an internal register 404. Gate circuit 405 is the same as gate circuit 401 and is controlled by signal TM. Digital comparator 403 receives digital signal SNA and registers internal register 4
04, the binary output of which is high when equal, is fed to the input of AND gate 410. Gate 410 receives signal DRV at its other input.

The output of AND gate 410 controls gate circuit 409. The gate circuit 409 is identical to the gate circuits 401 and 405 and is provided between the output register that sends out the signal SNB and the digital output that sends out the signal SNC to the second up/down counter 3.

The operation of the circuit described above is as follows. When the signal DRv changes to level 1, the output of the comparator 403 becomes a high level, which means that there has been no increase or decrease in fuel.
The value stored in the output register 402 is the value stored in the gate circuit 40
9 to the second up/down counter 3. Since this value is an average result or an integral result over a fairly long period of time, it is much more accurate than the value SNA at that point in time, especially when the vehicle is parked on a slope.

If an increase or decrease in fuel is detected, gate circuit 409 is disabled.

Of course, since the signal DRV is at a low level while the signal DRV is at a high level, the disabled state of the gate circuit 401 is maintained, thereby ensuring that the output register 4
02 is kept shut off to retain the value stored therein, which is beneficial if no increase or decrease in fuel is detected. When the signal DRV changes to high level, the signal S
The value of NA is communicated to the output register 402, which is useful if an increase or decrease in fuel is detected.

In FIG. 9, the scale factor adaptation circuit 500 is provided with a first frequency divider 503. Divider 503 performs division by a fixed number, and in this embodiment, since it is a 5-bit counter, it performs division by 32. The divider 503 is followed by a counter 502 whose digital output is fed to the input of a digital comparator 501 . Comparator 501 receives the digital signal SNB at another input. The output of the digital comparator 501 is high in the case of equality and is sent to the input of the AND gate 504. The other input of the gate 504 receives the signal HD and its output is sent to the clock input of the first divider 503. A second frequency divider 505 is adapted to perform the division by a controlled number and receives at its input the output signal from the AND gate 504. The output section of the second divider 505 is the counter 5
06, and the output part of the counter 506 is connected to the second
It is connected to segment decoding circuit 507. Circuit 507 is of well known type and is followed by control circuit 508.
is provided. The circuit 508 is also of a well-known structure, and the signal IF for the digital display unit is connected to the counter 502.
．． 503.506 to the reset input.

The second divider 505 performs division by a variable number,
In the embodiment, a counter 5051 is provided as shown in FIG. The digital output of the counter 5051 is 7 bits in the embodiment, and the digital output of the digital comparator 5052 is 7 bits.
is compared with the digital output of value M at . The above output of value M is also 7 bits and is obtained by a combinary network 5053 controlled by two switches L/G. The output of digital comparator 5052 is connected to the reset input of counter 5051 and forms the output of divider 505. Divider 505 performs division by the number M. This output section has M
The pulses are sent while the counter 5051 counts the pulses.

Since the combinary network 5053 is well known in the art, further explanation will be omitted.

The scale factor adaptation circuit described above operates as follows. In the embodiment, the block signal HF has a frequency of 11
It is 12. After being reset by this signal, the counter 502 counts the pulses sent from the divider 503. This counting continues until equality is detected and the comparator issues a blocking command on signal HD via AND gate 504. The frequency of the signal HD is approximately 10011z in the embodiment. At this point, the digital output of counter 502 is equal to the value of signal SNB, which means that n pulses of signal HD have passed through gate 504, so the relationship is:

n-32x (SNB value) The output of BCD counter 506 is equal to:

n/M Divider 505 performs division by N1.

The output SN will be equal to:

(32xM)X (value of SNB) Thus the circuit 500 adapts a scale factor equal to 32xM. Since M is controllable by switch L/G (two switches in the example), it can be controlled to at least three values corresponding respectively to liters, British gallons, and US gallons, and the interface controls switch L/G to By making adjustments, it can be applied to any vehicle.

In FIG. 11, another embodiment of an electronic interface device according to the invention has the same elements arranged in the same manner as the device described above, with the following exceptions, and which are given the same reference numerals. It is.

The input of the switching circuit 100, which receives the signal SI in the device described above, is connected in this embodiment to a constant potential V- at a low logic level.

74841 circuit 300 with shift is 74841 with shift
It has been replaced by circuit 300', which has a controllable division ratio and has an input for receiving a signal Sl for controlling the division ratio.

The increase/decrease detection and parasite increase blocking circuit 400 is replaced by the increase/decrease detection circuit 400'.

Time base 200 is a replacement for time base 200'.

Before explaining the above circuits (200, 300', 400-) in detail, the operation of the interface will first be explained.

After switching on the ignition of the vehicle there is a rapid transition phase during which the device of this embodiment acts exactly like the previously described device, during which the logic switch 102.1
03, the signal 5CCDSSAC becomes the signal 5CSHB.
, and this point is not affected by the above deformed structure.

By controlling the logic switches 102, 103, when the vehicle is running, the signals 5CCDSSAC and 5CCDSSAC respectively
-1SDD. Since the signal V- is at a low logic level, it is the potential that controls the down-counting of the counter 3, which is supplied to the control input of the second up-down counter 3. Therefore, only the digital output SNA can be reduced.

As explained below, since the analog signal SA follows the fluctuations of the signal EA as far as possible, the signal SI controls the division ratio of the shift divider circuit 300', i.e. the repetition frequency of the pulse train SDD, and thus In addition, the speed at which the digital signal SNA and analog signal SA decrease is controlled. Therefore, the signal EI is controlled by the signal S while controlling the speed.
It can be said that the decrease in A is controlled. Similar to the previously described device, these signals follow a slow decrease in the level of the fuel tank, in which case the signal output follows the rapid parasitic fluctuations of the integral effect signal EA of the first up-down counter 2 which controls the rate of decrease. It will not occur.

When the ignition is switched on, the increase/decrease detection circuit 400- operates similarly to the increase/decrease detection and parasite increase blocking circuit 400 described above. However, in the device of this embodiment, since the signal SNA only decreases when the vehicle is running, the circuit 400 is not provided with any increase blocking circuit, and such a circuit is unnecessary. It has become.

In FIG. 12, the shift-equipped 74841 circuit 300' has a controllable division ratio and includes the same elements as the shift divider circuit described above (the same reference numerals are given to them, and detailed explanations are omitted). A logic switch 310 and a flip-flop 311 are also provided.

In this embodiment, the reset input provided in the up-down counter 309 is used in place of the overflow output of the up-down counter 309, and the digital output of the up-down counter 309 is Two binary outputs Bn, Bn+p are used, corresponding to bits of n and bits of rank n+p.

The logic switch 310 is identical to the switch 102 and is provided with a control input, two signal inputs connected to the two outputs BnSBn+p, and a signal output for delivering the signal SDD.

The flip-flop 311 has an input receiving the signal SI and an output Q connected to the control input of the switch 310.
and a clock input for receiving the signal SDD.

Signal SDD is also sent to the reset input of up-down counter 310.

The operation of circuit 300' is as follows. At each time point corresponding to a rising edge of a pulse of signal SDD, flip-flop 311 makes a copy of the current signal value Sl at its output and holds it until the next rising edge. Assume that this value corresponds to the negative sign of the output of up-down counter 2. That is, it is assumed that the signal EA has remained smaller in average value than the signal SA during the previous time interval. Signal SA needs to decrease fairly rapidly. For this purpose, the logic switch 310 is such that the signal Sl controls the connection of the binary output BN to the output SDD. Output SD
The repetition frequency of D is:

5DD-1/2 (fCTE/DM-fHC) If the signal Sl has a positive sign, the signal SA must decrease rapidly, so the binary output Bn+p connected to the output SDD has a frequency such that: become.

fSDD″″ n+p 1/2 (fCTE/DM-fHC), that is, repetition frequency f is the repetition frequency f. It can be said that the slope of the linear function connected to the TDD E/DM can be controlled by the output of the up/down counter 2.

In FIG. 13, an increase/decrease detection circuit 400' has almost the same elements as the aforementioned increase/decrease detection and parasite increase blocking circuit 400, but the comparator 408, OR gate 407, and AND gate 406 of the aforementioned circuit are omitted. The difference is that In this embodiment of the device, the signal DRV for the inverter 411 at the output is fed directly to the control input of the gate circuit 401. The operation of the increase/decrease detection circuit 400 is performed by a comparator 403 and a gate circuit 4.
05, register 404, gate circuit 409, gate 4
As far as the 101 inverter 411 is concerned, the circuit 40
The operation is similar to that of 0. If no fuel increase or decrease is detected,
While signal DRV is high, signal DRV shuts off output register 402 and causes it to maintain the value stored therein. At approximately the same time that signal DRV goes low, the contents of output register 402 are always equal to signal SNA.

Time base 200' is generally identical to time base 200, but since signal TRV is not needed in this embodiment,
The only difference is that no such signal is sent out.

In the second embodiment described above, the slope of the linear function connecting the frequency of the pulse train SDD to the frequency of the pulse train CTE/DE depends on the sign output of the up-down force outer-2.

Although the slope is controlled to correspond to the highest frequency of the pulse train SDD, the slope can be changed if the amount of fuel in the fuel tank is below a certain critical level. That is, it is also possible to configure the display value to be less than the actual value when the tank is nearly empty.

Since the circuit can be modified in this manner using well-known techniques, a detailed explanation thereof will be omitted.

Of course, the interfaces of the two embodiments described above are highly complete, but the interface according to the present invention can also be configured in a simpler form. For example, a shift divider circuit 300.300-, a circuit 400.400 for increase/decrease and barasite increase blocking,
Additionally, scale factor adaptation circuit 500 is not necessarily required. Omit any (one or two) or all of them and correspondingly set the time base 200
It is also possible to simplify the process according to the invention.

If the shifted divider circuit 300.300' is omitted, the signal SDD must be replaced with a clock signal at a frequency that the compromise can reach to correct for slow and rapid roadway conditions.

If an analog display unit controlled by the output SA is used, it is not necessary to provide the circuits 400, 400', 500. Furthermore, the device according to the invention can not only be used for measuring the fuel level in a motor vehicle, but also in any application where it is desirable to filter rapid changes at two points in an electronic circuit.

Of course, it is not necessary to constantly supply power to the device, and depending on usage conditions, the power supply may be controlled by operating a switch. In this case especially the circuit 400.400-
(if you use them) you need to use non-volatile memory.

[Brief explanation of the drawing]

1 is a block diagram of a device according to a first embodiment of the present invention, FIG. 2 is a block diagram of a switching circuit of the device of FIG. 1, and FIG. 3 is a detailed diagram of a logic switch of the switching circuit of FIG. 2. 4 is a block diagram of the time base of the device shown in FIG. 1, FIG. 5 is a diagram showing a time chart of signals generated by the time base of FIG. 4, and FIG. 6 is a diagram showing the time base of the device shown in FIG. 1. 7 is a time chart of the main signal of the shifted divider circuit of FIG. 6, and FIG. 8 is an increase/decrease detection circuit for blocking parasite increase in the device of FIG. 1. Detailed schematic diagram of, No. 9
10 is a block diagram of the scale factor adaptation circuit of the apparatus shown in FIG. 1, FIG. 10 is a block diagram of the variable number divider of the scale factor adaptation circuit of FIG. 9, and FIG. 11 is a block diagram of the scale factor adaptation circuit of the device of FIG. A block diagram of the apparatus, FIG. 12 is a detailed schematic diagram of the division ratio control type shift divider circuit of the apparatus of FIG. 11, and FIG. 13 is a detailed schematic diagram of the increase/decrease detection circuit of the apparatus of FIG. 2.3... Up/down counter, 4... Digital-to-analog converter, 100... Switching circuit, 200... Time base, 300... Divider circuit, 400... Increase/decrease detection and parasite increase blocking circuit FIG, 2 FIG, '3 2CO-,. FIG, 4 FIG, 5 ° −1 1t FIG, 7

Claims (19)

[Claims] (1) In an electronic interface device disposed between a sensor with an analog output for detecting a physical quantity and a display unit for displaying the value of the physical quantity, the display unit includes an analog output. A controlled generator for control is provided, an analog amplitude comparator is provided for comparing the amplitudes of the signals at the outputs of the controlled generator and the sensor, the binary output signal of which controls the controlled generator; The generator is provided with a binary control input section for controlling the increase/decrease of the output signal, and is provided with a clock and a first up/down counter for the first clock signal, and the binary output signal of the comparator is used to count up and down the first up/down counter. , and the binary code signal of the first up/down counter controls an increase/decrease in the output signal of the generator. (2) A device according to claim 1, further comprising control type means for controlling the generator, the direction and speed of which are controlled and a monotonically varying signal is sent out. (3) means for causing the controlled generator to generate a first pulse train; a first up-down counter having a block input for receiving the first pulse train; and a digital output of the second up-down counter. 2. The apparatus according to claim 1, further comprising a connected digital-to-analog converter, the control input of said generator being an up-down counter control input of said second up-down counter. (4) A first switching circuit is provided in the control type means for controlling the generator, and the first switching circuit provides the sign output to the up-down count control input section of the second up-down counter. Alternatively, the output of the comparator is supplied, and the generator is further provided with a second switching circuit, and the second switching circuit provides the clock input of the second up-down counter with:
4. The device according to claim 3, wherein a second clock signal is supplied in place of the first pulse train. (5) the physical quantity is the level of fuel in the vehicle, and the vehicle is equipped with another sensor in the form of an electronic tachometer and a flow meter, and the another sensor emits a second pulse train. said means for generating said first pulse train such that said first pulse train has a repetition frequency equal to said second pulse train;
4. The device of claim 3, wherein the device is configured to be a linear function of the repetition frequency of the pulse train. (6) The means for generating the first pulse train receives the second pulse train and the third clock signal.
a third up/down multiplexing circuit with inputs and outputs, a clock input connected to the output of the weighting circuit and an output for delivering the first pulse train; a counter; and a control circuit connected to the multiplexing circuit and the up-down counting control input section of the third up-down counter to up-count the pulses of the second pulse train and down-count the pulses of the third clock signal. An apparatus according to claim 5. (7) The display unit is of a digital type, and the first means for storing the digital output value at any time is provided as a buffer between the digital output section of the second up-down counter and the display unit. 4. The device according to claim 3, wherein the device is arranged as a. (8) a second means for storing the value of the digital output at another arbitrary time; and a first digital means for comparing the value of the digital output with the value stored in the second means. 8. Apparatus according to claim 7, further comprising a comparator and means controlled by said digital comparator for transferring the value stored in said first means to said second up-down counter. (9) Claim 7, further comprising a controlled means configured to prevent the first storage means from storing at any time a value higher than the value stored at any preceding time. The device described in. 10. A device as claimed in claim 3, characterized in that the display unit is provided with means for adapting a controlled scale factor to the value of the digital signal to be displayed. (11) The scale factor adaptation means is provided with a first frequency division circuit that performs division by a constant number at the input section to which the fourth clock signal is supplied, and is followed by a first counter; A second frequency divider with a controlled number of divisions is provided at the input to which the clock signal is supplied, followed by a second counter, for comparing the value of the digital signal with the digital output of the first counter. a second digital comparator is provided, the second digital comparator is configured to compare the value of the digital signal with the digital output of the first counter; 8. The device according to claim 7, wherein the second counter is controlled by the second digital comparator, and the digital output of the second counter is connected to the display device. (12) the physical quantity is the fuel level of the vehicle;
means for causing the controlled generator to generate a first pulse train of a controlled repetition frequency controlled by the signed output of the first up-down counter; a clock input for receiving the first pulse train; A second up-down counter having an up-down counting control input connected to a potential ensuring counting control, and a digital-to-analog converter connected to a digital output of the second up-down counter. A device according to scope 1. (13) in said control type means for controlling said generator, instead of said potential ensuring down counting control to said up-down control input of said second up-down counter at the time of start-up of said vehicle; a first switching circuit configured to supply the output of the comparator; and upon start-up of the vehicle;
Claim 12, wherein the clock input section of the second up-down counter is provided with a second switching circuit configured to supply a second clock signal instead of the first pulse train. equipment. (14) providing the vehicle with another sensor in the form of an electronic tachometer and a flow meter, the second pulse train being generated by the other sensor; and the above for generating the first pulse train. means such that the repetition frequency of the first pulse train is a linear function of the repetition frequency of the second pulse train, the slope of the function being controllable by the signal output of the first up-down counter. Apparatus according to claim 12. (15) The means for generating the first pulse train is provided with a multiplexing circuit comprising two input sections and an output section receiving the second pulse train and a third clock signal, and the multiplexing circuit a third with a clock input and a parallel digital output connected to the above input of the
an up/down counter for supplying the two bits of the parallel digital output to a switching circuit controlled by the sign output for delivering the first pulse train; Claim 14 provides a control circuit connected to the up/down counting control input section of the 3 up/down counter, for up-counting the pulses of the second pulse train and down-counting the pulses of the third clock signal. The device described. (16) The display device is of a digital type, and the first means buffers between the digital output part of the second up-down counter and the display unit in order to store the value of the digital output at any time. 13. A device according to claim 12, provided as: (17) a second means for storing the value of the digital output at another arbitrary time; and a first digital means for comparing the value of the digital output and the value stored in the second means. 17. Apparatus according to claim 16, further comprising a comparator and means controlled by said digital comparator for transferring the value stored in said first means to said second up-down counter. 18. A device as claimed in claim 12, characterized in that the display unit is provided with means for adapting a controlled scale factor to the value of the digital signal to be displayed. (19) The scale factor adaptation means is provided with a first frequency division circuit that performs division by a constant number at the input section to which the fourth clock signal is supplied, and is followed by a first counter; A second frequency divider with a controlled number of divisions is provided at the input to which the clock signal is supplied, followed by a second counter, for comparing the value of the digital signal with the digital output of the first counter. A second digital comparator is provided, the second digital comparator being configured to compare the value of the digital signal with the digital output of the first counter, and to control the blocking of the fourth clock signal in equal cases. 19. Device according to claim 18, characterized in that it is provided under the control of two digital comparators, the digital output of said second counter being connected to said display device.