JPS633516A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To eliminate jitter of an output signal by using an area comparison circuit receiving a reception signal and the output signal of a signal generating circuit and outputting a control signal at the time of bisecting a waveform area during one period of the reception signal. CONSTITUTION:A loop filter 3, a signal generating circuit 5 and the area comparison circuit 31 used in place of a phase comparator circuit constitute the titled phase locked loop circuit. Since the area comparator circuit 31 controls control signals Pco, Mco so that the leading or trailing of an output signal 9 comes at the time bisecting the waveform area during one period of the reception signal 7, no jitter is caused even with the presence of larger or small level of the reception signal 7. The area comparator circuit 31 consists of a slicer 11, an exclusive OR gate 33, a low pass filter 39 comprising a resistor 35 and a capacitor 37, a comparator 41, an inverter 43 and AND gates 45, 47.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a phase synchronization circuit used in a digital communication system, and in particular, the present invention relates to a phase synchronization circuit used in a digital communication system, and in particular, the present invention relates to a phase synchronization circuit used in a digital communication system. This invention relates to a phase locked circuit that extracts timing signals with high precision.

(Prior Art) Generally, in a digital communication system, a transmitting side and a receiving side are connected through a transmission path, and communication is performed by sending a digital signal from the transmitting side to the receiving side. On the receiving side of such a digital communication system, a phase synchronization circuit is required to extract a timing signal from an incoming digital signal.

FIG. 9 is a block diagram showing the configuration of a conventional phase synchronization circuit. The phase synchronized circuit shown in the figure includes a phase comparison circuit 1, a loop filter 3, a signal generation circuit 5, an input terminal 7, and an output terminal 9.

The phase comparison circuit 1 includes a slicer 11 and a rising edge detection circuit 13.
, an AND gate 15, 17, and an inverter 19,
1 received word input from input terminal 7 and signal generation circuit 5
It compares the phase with the output signal output from the loop filter 3 and supplies a control signal corresponding to the phase difference to the loop filter 3. The received signal input to the input terminal 7 is sent to the slicer 11
is converted into a square wave signal by The rising edge detection circuit 13 detects the rising edge of the wave signal and outputs a rising pulse corresponding to the rising edge.

The loop filter 3 consists of a bidirectional counter 21 and an OR gate 23, and the phase comparison circuit 1 due to the influence of input noise.
This is to remove small fluctuations in the output. The positive control signal @PCO is input to the up terminal P of the bidirectional counter 21, and the negative control signal 18 NG is input to the down terminals D○ to VN.
O can be added. The bidirectional counter 21 consists of a 2N stage random walk filter.
The contents of 1 are set to [Initial]N in the initial state. When the positive control signal PCO is applied to the bidirectional counter 21 from the phase comparison circuit 1, the bidirectional counter 21 counts up, and when the negative control signal NGO is applied from the phase comparison circuit 1 to the bidirectional counter 21, the bidirectional counter 21 counts up.
performs a countdown.

When the content of the bidirectional counter 21 reaches 2N, the forward control signal FCO is applied from the bidirectional counter 21 to the signal generation circuit 5. This forward control signal FCO is the OR gate 23
is added to the bidirectional counter 21 via the bidirectional counter 21, and the contents of the bidirectional counter 21 are reset to N. Bidirectional counter 2
When the content of 1 reaches "Q', the backward control signal BCO is applied from the bidirectional counter 21 to the signal generation circuit 5. This signal is simultaneously applied to the bidirectional counter 21 via the OR gate 23, and the bidirectional counter 21 The contents of are reset to N.

The signal generation circuit 5 includes a fixed clock 25, a pulse addition/removal circuit 27, and a frequency division circuit 29. Fixed clock 25 generates a reference clock signal. Pulse addition/removal circuit 27
When forward control signal FCO is sent, one pulse is added to the reference clock signal and output, and when backward control signal BCO is sent, one pulse is removed from the reference clock signal and output. The frequency dividing circuit 29 divides the output signal of the pulse addition/removal circuit 27 by 1/R. That is, the forward control signal FC
When O is sent, the signal obtained by adding one pulse to the reference clock signal is frequency-divided by 1/R, and the output of the frequency divider circuit 29 is 36
When the phase advances by 0°/R and the backward control signal BCO is sent, the signal with one pulse removed from the reference clock signal is divided into 1/R, and the output of the frequency divider circuit 29 becomes 360'/R.
The phase is delayed. The outputs of the two frequency dividing circuits are outputted to the output terminal 9, and are also inputted to the ant gate 15 and the inverter 19 for feedback control.

(Problems to be Solved by the Invention) However, the above-described conventional phase-locked circuit has the following problems.

10 and 11 show the waveforms of the input (fi RA) of the slicer 11 in the phase comparison circuit 1, the output signal B of the rising edge detection circuit 13, and the output signal C of the output terminal 9.

Noise may be added to the input signal input from the Lina straw input terminal 7 to the slicer 11 in the transmission path.
Also, waveform distortion may occur due to band limitation. For this reason, as shown in FIG. 10(a), the amplitude of the signal input to the slicer 11 increases, or as shown in FIG. 11(a).
), the amplitude becomes small. In this case, FIGS. 10(C) and 11(C)
), this results in phase fluctuations, causing jitter in the output signal C. If the output signal C with this jitter is used as a timing signal for an identification circuit, there is a problem in that the characteristics of the recovered digital signal will deteriorate. Ta.

The present invention has been made in view of these problems, and its purpose is to provide a phase synchronized circuit that can remove jitter from the output signal and extract the evening signal No. 15 from the received signal with high precision. It's in particular.

[Disclosure of the Invention] (Means for Solving the Problems) To achieve the above object, the present invention provides a loop filter and a signal generation circuit that changes the phase of an output signal using a control signal output from the loop filter. and a control signal to the loop filter so that the output signal rises or falls at the time when the received signal and one output word of the signal generation circuit are input and the waveform area of one period of the received signal is divided into two. Features (Function) characterized in that the phase synchronized circuit of the present invention is characterized in that the output signal rises or falls at the time when the waveform area of one period of the received signal is divided into two. Therefore, no jitter occurs in the output signal whether the amplitude of the received signal is large or small.

(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 1 is a configuration block diagram of a phase-locked circuit according to one embodiment of the present invention. Elements that perform the same functions as those in the conventional example shown in FIG. Omitted.

That is, as shown in FIG. 1, in the phase locked circuit of this embodiment, an area comparison circuit 31 is provided in place of the phase comparison circuit 1 of the conventional example shown in FIG.

The area comparison circuit 31 includes a slicer 11, an exclusive OR gate 33, a low-pass filter 39 consisting of an ash remover 35 and a capacitor 37, a comparator 41, an inverter 43, and AND gates 45 and 47.

Slicer 11 converts the received signal into a rectangular wave signal. The exclusive OR gate 33 inputs the waveform of the output signal C of the signal generation circuit 5 in the low voltage section.
In the section where the output signal C is at a high potential, the waveform of the output signal C is assumed to be the inverted version of the signal F. The low-pass filter 39 outputs the exclusive OR gate 33 (
Integrate and average the signal. Comparator 41 compares the output of low-pass filter 39 and reference potential Eref, and when the output of loop filter 41 is greater than reference potential Eref, the output becomes high level. AND gate 45 opens when the output of comparator 41 is low, and AND gate 47 opens when the output of comparator 41 is high.

Next, the operation of this circuit will be explained. FIGS. 2(a) to 2(C1) and FIGS. 3(a) to (g) are waveform diagrams of signals at various parts in the area comparison circuit 31 of this embodiment.

When the signals E and C are as shown in FIGS. 2(a) and 2(b), the output of the exclusive OR gate 33 is as shown in FIG. 4(C). At this time, the output of the low-pass filter 39 is as shown in FIG. 2(d).
Since the voltage is higher than the standard voltage Eref, the output of the comparator 41 becomes high level, as shown in FIG. 2(e). Since the AND gate 47 is opened and the AND gate 45 is closed, the AND gate 47 outputs a positive control signal PC○ as shown in FIG. 2 (g>).

When the signals E and C are as shown in FIGS. 3(a) and 3(b), the output of the exclusive OR gate 33 is as shown in FIG.
The result will be as shown in C). At this time, the output of the low-pass filter 39 is smaller than the reference voltage Eref, as shown in FIG. 2(d), so the output of the comparator 41 is at a low level, as shown in FIG. 2(e). The AND gate 47 closes and the AND gate 45 opens.
A negative control signal NGO as shown in FIG. 4(f) is output from the AND gate 45.

That is, in FIG. 2, the area S1 of the high potential section of the signal E in the low voltage section 11 of the signal C is larger than the area S2 of the high potential section of the signal E in the high potential section of the signal C.

Conversely, in FIG. 3, the area S2 is larger than the area S1.

Therefore, in the case of FIG. 2, since the area comparison circuit 31 generates more positive control signals PCO, the probability that the forward ill control signal FCO is generated is higher than that of the loop filter 3. Therefore, after a while the phase of the signal C advances and, as shown in FIG. 4, the phase of the signal C is maintained so that the area S1 and the surface (71S2) are equal.

On the other hand, in the case of FIG. 3, since the area comparison circuit 31 generates many negative control signals NGO, there is a high probability that the loop filter 3 generates the negative control signal BCO. Therefore, after the phase of the signal C is delayed for a while, the phase of the signal C is maintained so that the area S1 and the area S2 are equal, as shown in FIG.

5 and 6 show the received signal A input from the input rW element 7 and the output signal @E of the slicer 11 in this embodiment.
, is a waveform diagram of the output signal C of the output terminal 9. As mentioned above, the signal C is adjusted to a phase such that the area S1 of the high potential section of the signal E in the low potential section of the signal C is equal to the area S2 of the high potential section of the signal g-E in the high potential section of the signal C. is maintained, so 1. Regardless of the magnitude of the amplitude of signal A, signal C rises at the time when the area of the high potential section of signal E, which is obtained by slicing signal A, is divided into two equal parts, and the occurrence of jitter as in the conventional method can be prevented.

FIG. 7 shows another embodiment of the present invention, in which the signal A input from the input terminal 7 is sent to the slicer 1.
1. Input to analog switch 49.51. The signal C1 output from the signal generation circuit 5 is sent to the analog switch 5.
1 and an inverter 53 to four analog switches.

The analog switch 49 is closed when the output of the inverter 53 is at a high level, that is, when the signal C is in a low potential range, and the analog switch 51 is closed when the signal SC is in a high potential range. The outputs of the analog switches 49 and 51 are respectively input to low pass filters 55 and 57 and integrated to measure the waveform area. The outputs of the low-pass filters 55 and 57 are compared by a comparator 59, and the output of the comparator 59 is input to an AND gate 47 via an AND gate 45 and an inverter 61.

Next, the operation of this embodiment will be explained. When the signal C is in a high potential area, the analog switch 51 is closed, and when the 1g signal C is in a low potential area, all four analog switches are closed. Therefore, the area of the signal A in the high potential section of the signal C is measured by the low-pass filter 57, the area of the signal @A in the low potential section of the signal C is measured by the low-pass filter 55, and this measured area is Comparator 5 is used for comparison.

When the area of signal A in the high potential section of signal C is larger than the area of signal A in the low potential section of signal C,
Since the output of the comparator 59 becomes "1', the AND gate 45 opens, and the output of the slicer 11 is passed through the AND gate 45 as a negative control signal NCo to the loop filter 3.
is input.

Conversely, the area of signal A in the high potential section of signal C is
When the area of signal A is smaller than the area of signal A in the low potential section of The signal is input to the low-pass filter 3 as a signal.

Note that the present invention can be modified in various other ways. For example, the low-pass filter 39, J5 and the seventh filter in FIG.
The low-pass filters 55, 57 in the figure can also be constructed using operational amplifiers.

Further, the signal generating circuit 5 is also not limited to the one configuration shown in FIG. 1, and i is not limited to the one configuration shown in FIG. For example, it may be configured to avoid changing the frequency division ratio according to the control signal from the loop filter 3, or it may have two fixed clocks with different oscillation frequencies, and the control a
A configuration may be adopted in which the a signal is selected and then passed through the frequency dividing circuit 29.

FIG. 8 is a block diagram showing the configuration of the pond of the loop filter 3. This loop filter 3 is generated from two bit counters 63.65 and 1 (1 bit counter 67 and an OR gate 69.71.
has the relationship \≦M<2N.

In the initial state, the three counters 63, 65, and 67 are set to O. \When the content of the bit counter 63 reaches N, a forward control 1 word FCO is generated and 1. At the same time, three counters 63, 65, 67 are reset. When the contents of the heavy bit counter 65 become negative, the reverse control signal B
Generate CO and 3 counters at the same time 63.65.67
Reset. ~ When the contents of the 1-bit counter 67 reach M, the three counters 63, 65, and 67 are reset.

This circuit determines whether the probability of occurrence of the positive control signal FC○ and the negative control signal BCO is small or large.

[Effects of the Invention] As described above in detail, according to the phase synchronization circuit of the present invention, jitter in the output signal can be removed, so a timing signal can be extracted with high precision from a received signal.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram of a phase locked circuit according to an embodiment of the present invention, and FIGS. 2, 3, and 4 are waveform diagrams of each part of the area comparison circuit 31, and FIG. 6 is a waveform diagram of received signals A, E, and C, FIG. 7 is a block diagram of the configuration of a phase-locked circuit according to an embodiment of the present invention, and FIG. 8 is a diagram of another five-channel configuration of the loop filter. A block diagram showing
Figure 9 is a configuration block diagram of a conventional phase-locked circuit.
0 and 11 are waveform diagrams of signals A, B, and C in the conventional example. 3...Loop filter 5...Signal generation circuit 31...Area comparison circuit Applicant: Toshiba Corporation Patent attorney Sasa Suyama - Figure 1■・17(. Figure 2 Figure 3 Figure 1 Figure 5

Claims (1)

[Claims] (1) A loop filter, a signal generation circuit that changes the phase of an output signal according to a control signal output from the loop filter, and a waveform of one period of the received signal in which the received signal and the output signal of the signal generation circuit are inputted. A phase synchronized circuit comprising: an area comparison circuit that sends a control signal to the loop filter so that the output signal rises or falls at the time when the area is divided into two equal parts.