JPS6335127B2 - - Google Patents

Abstract

The presence of a d.c. offset in the input signal to an adaptive equalizer for a high speed modem must be removed before a valid signal enters the equalizer if the "coefficient up-date" algorithm for the equalizer is not to be confused. Normally the d.c compensation is achieved using adjust-on-test resistors or potentiometers which provide for in life adjustments to compensate for ageing drift. The submission envisages the use of an additional adaptive equalizer tap-stage connected to a fixed voltage source. This voltage is multiplied by the additional tap-stage multiplier and summed with the outputs of the other tap-stages in the equalizers accumulator. The error produced from the equalizer decision circuit is correlated with the fixed voltage in the additional tap-stage correlator the output of which controls the gain of the additional tap-stage multiplier thereby compensating for the original d.c. offset of the output of the equalizer accumulator.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transversal equalizer, and particularly to DC compensation in an adaptive equalizer.

The presence of a DC offset in the input signal to the adaptive equalizer introduces confusion in the coefficient update algorithm. This is because the error signal cannot be properly related to the data signal samples at each tap of the equalizer. Therefore, the DC offset in the input signal must be corrected to zero before the signal enters the equalizer. This is typically accomplished with test adjustment resistors or voltage dividers that provide in-life adjustments to correct for aging drift in analog components such as operational amplifiers, sample-and-hold circuits, and the analog-to-digital converter itself.

In accordance with the present invention, an adaptive equalizer is provided that includes a plurality of tap stages, a first stage receiving an input signal and subsequent stages receiving spaced samples of the input signal. Each stage includes a multiplier and a correlator to which input signals are sent, and the output signals from the multipliers are summed by an accumulator. The accumulator sends a signal to a decision circuit which provides an output signal and an error signal, the latter being sent to each correlator to correct residual errors. The adaptive equalizer includes an additional tap stage, which has its own multiplier and correlator, which are connected to a fixed voltage source.
The output signal from a multiplier is added to the output signal of another multiplier by the accumulator. The error signal produced by the decision circuit is also correlated with the fixed voltage by an additional correlator to control the gain of the additional tap stage multiplier. This compensates for the initial DC offset in the input signal.

The adaptive equalizer of the present invention is applied to a modulation/demodulation device known as a modem.

The present invention will be explained in detail based on the following exemplary embodiments with reference to the accompanying drawings.

Referring to FIG. 1, values Xi, X(i-T), and X(i-2T) obtained by sampling the input signal at intervals are processed by four-quadrant multipliers M ₁ , M ₂ , and M ₃ , respectively. are multiplied and then each multiplied value is added by accumulator A. The output of accumulator A is sent to decision circuit D and compared with a set of reference levels or locally generated reference signals to produce an output signal Y _k and an error signal E _k . The error signal E _k is transmitted through the correlator C1,
are respectively correlated with the sampled signals in C2 and C3, and the outputs of these correlators are input to the associated multipliers.
The gains of M ₁ , M ₂ and M ₃ are controlled to minimize the correlation of each tap stage.

If the input signal has a DC offset, correlator C
1, C2, and C3 attempt to correct residual errors. However, since there is no linear relationship between the DC offset and the signal sample, even if an attempt is made to remove the DC offset using a correlator, the multiplier M ₁ ,
It is not possible to provide optimal settings for M ₂ and M ₃ , resulting in distortion of the output signal Y _k .

Referring to FIG. 2, an equalizer according to the present invention is shown. The equalizer includes a fourth tap stage connected to a fixed voltage source V. The voltage V is multiplied by the multiplier M ₄ and by the accumulator A the multipliers M ₁ ,
It is summed with the outputs of M ₂ and M ₃ . The determination circuit D outputs an output signal Y _k and also provides an error signal E _k to each of the correlators C ₁ to _{C 4} . The error signal E _k is passed through the correlator C ₁ ,
It is correlated with the sample signal in C ₂ and C ₃ , but in an additional tap stage, a fixed voltage V is applied in correlator C ₄ .
and the result is used to control the gain of multiplier _M4 .

That is, in the correlator _C4 , the error signal _Ek is correlated with a fixed voltage that has a linear relationship with the DC offset, so that the output of the correlator _C4 tends to make the DC offset at the output of the accumulator A zero. Multiplier M ₄
The gain will be controlled. Therefore, the DC offset at the output of the accumulator A thus obtained is reduced, and the gain of the multipliers M ₁ to _{M 3} of each tap stage is appropriately controlled by the error signal E _k obtained, and the correlation is Since the multiplier _C4 further controls the gain of the multiplier _M4 so that the DC offset becomes completely zero,
The DC offset in the input signal becomes completely zero.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional adaptive equalizer, and FIG. 2 is a circuit diagram showing a typical embodiment of the adaptive equalizer according to the present invention. Explanation of reference symbols, Xi, X(i-T), X(i-
2T)... Sample signal; A... Accumulator; D...
Judgment circuit; C1, C2, C3, C4... correlator;
M ₁ , M ₂ , M ₃ , M ₄ ... multiplier; Y _k ... output signal; E _k ... error signal; V ... fixed voltage source;

Claims (1)

[Scope of Claims] 1. A plurality of tap stages, an accumulator, and a decision circuit, wherein a first tap stage receives an input signal, and each subsequent tap stage receives an input signal delayed by a predetermined time. each tap stage has a multiplier and a correlator into which the received signal is input; the output signals from the multipliers of each tap stage are summed by the accumulator and the output signal is and a decision circuit that compares the output signal of the accumulator with a reference signal to provide an output signal and an error signal, and the error signal is sent to each of the correlators to correct residual errors. The adaptive equalizer further includes an additional tap stage, the additional tap stage having a multiplier and a correlator connected to a fixed voltage source, the output from the multiplier of the additional tap stage The signal is added by the accumulator to the output signal of the other multiplier, and the error signal provided by the decision circuit is correlated with the fixed voltage by the correlator of the additional tap stage to An adaptive equalizer in which the output of the correlator controls the gain of the multiplier of the additional tap stage, thereby compensating for DC offsets in the input signal. 2. In claim 1, the correlator of the additional tap stage controls the gain of the multiplier of the additional tap stage until the DC offset becomes zero;
Adaptive equalizer that allows the multipliers of other tap stages to take their optimal gain values.