JPH03211920A - Line equalizer - Google Patents
Line equalizerInfo
- Publication number
- JPH03211920A JPH03211920A JP678190A JP678190A JPH03211920A JP H03211920 A JPH03211920 A JP H03211920A JP 678190 A JP678190 A JP 678190A JP 678190 A JP678190 A JP 678190A JP H03211920 A JPH03211920 A JP H03211920A
- Authority
- JP
- Japan
- Prior art keywords
- gain
- peak value
- variable
- equalizer
- flat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
この発明は、ディジタル伝送において線路損失を補償す
る線路等化器に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a line equalizer that compensates for line loss in digital transmission.
(従来の技術)
第2図は例えば特公昭64−8936号公報に示された
従来の可変等化方式による線路等化器を示すブロック図
であり、図において、(1)は入力端子、(2)は利得
変化量の周波数特性が平坦である平坦利得可変回路、(
3)は周波数特性が線路の損失特性と同じ傾斜を持つ可
変等化器、(4)は可変等化器(3)の出力信号の尖頭
値を検出する尖頭値検出器、(5)は尖頭値検出器(4
)で検出した尖頭値と基準値を比較して尖頭値と基準値
を一致させる様に可変等化器(3)の利得を制御する直
流増幅器、(6)は可変等化器(3)の出力信号の隣接
タイムスロットの符号間干渉を検出し、それに対応した
信号を出力して平坦利得可変回路(2)の利得を制御す
る符号間干渉検出器、(7)は出力端子である。(Prior Art) FIG. 2 is a block diagram showing a line equalizer using a conventional variable equalization method disclosed in Japanese Patent Publication No. 64-8936, for example. In the figure, (1) is an input terminal; 2) is a flat gain variable circuit in which the frequency characteristic of the amount of gain change is flat, (
3) is a variable equalizer whose frequency characteristics have the same slope as the loss characteristics of the line, (4) is a peak value detector that detects the peak value of the output signal of the variable equalizer (3), and (5) is the peak value detector (4
) is a DC amplifier that controls the gain of the variable equalizer (3) by comparing the peak value detected by the reference value with the reference value so that the peak value and the reference value match. ), an intersymbol interference detector that detects intersymbol interference in adjacent time slots of the output signal and outputs a corresponding signal to control the gain of the flat gain variable circuit (2), (7) is an output terminal. .
次に動作について第3図に示す波形図を参照して説明す
る。入力端子(1)より入力された受信信号は平坦利得
可変回路(2) 可変等化器(3)を通って出力端子
(7)より出力される。この時、可変等化器(3)の出
力信号の尖頭値を尖頭値検出器(4)が検出し尖頭値が
基準値と等しくなる様に直流増幅器(5)が可変等化器
(3)の利得を制御する。ここで可変等化器(3)の周
波数特性は線路損失と完全に対応しているので、送信パ
ルス波形の増幅および時間幅が正規のものであれば、尖
頭値と基準値が一致した時符号間干渉は0となる(第3
図の波形A参照)。しかし、例えば、送出パルス波形の
増幅が正規の値より大きかった場合には可変等化器(3
)の周波数特性と線路損失が対応しなくなるので、尖頭
値と基準値を一致させる様に可変等化器(3)の利、得
を制御すると符号間干渉を生じる(第3図の波形B参照
)。すると符号間干渉検出器(6)の出力により、平坦
利得可変回路(2)の利得が下げられ、可変等化器(3
)の尖頭値が小さくなるので尖頭値検出回路(4)
直流増幅器(5)によって可変等化器(3)の利得が上
げられる。この一連の動作の繰り返しにより最終的に符
号間干渉が0で、尖頭値と基準値が行ったする様な平坦
利得可変回路(2)と可変等化器(3)の利得の組み合
わせが決定される。また送信パルス波形の振幅が小さか
った場合(第3図の波形C参照)でも同様の結果が得ら
れる。Next, the operation will be explained with reference to the waveform diagram shown in FIG. A received signal input from an input terminal (1) passes through a variable flat gain circuit (2) and a variable equalizer (3) and is output from an output terminal (7). At this time, the peak value detector (4) detects the peak value of the output signal of the variable equalizer (3), and the DC amplifier (5) detects the peak value of the output signal of the variable equalizer (3) so that the peak value becomes equal to the reference value. (3) Control the gain. Here, the frequency characteristics of the variable equalizer (3) completely correspond to the line loss, so if the amplification and time width of the transmitted pulse waveform are normal, when the peak value and the reference value match, Intersymbol interference becomes 0 (3rd
(See waveform A in the figure). However, for example, if the amplification of the transmitted pulse waveform is larger than the normal value, the variable equalizer (3
) and the line loss no longer correspond to each other, so if the gain of the variable equalizer (3) is controlled to match the peak value and the reference value, intersymbol interference will occur (waveform B in Figure 3). reference). Then, the output of the intersymbol interference detector (6) lowers the gain of the variable flat gain circuit (2), and the output of the variable equalizer (3) lowers the gain of the variable flat gain circuit (2).
) becomes small, so the peak value detection circuit (4)
The gain of the variable equalizer (3) is increased by the DC amplifier (5). By repeating this series of operations, the combination of gains of the flat gain variable circuit (2) and variable equalizer (3) is finally determined, with zero intersymbol interference and the peak value and reference value. be done. Similar results can also be obtained when the amplitude of the transmitted pulse waveform is small (see waveform C in FIG. 3).
従来の線路等化器は以上のように構成されているので、
尖頭値と符号間干渉を同時に制御しなければならず、収
束時間が一定でなく、また収束判定も難しいという問題
点があった。Since the conventional line equalizer is configured as above,
There are problems in that the peak value and intersymbol interference must be controlled simultaneously, the convergence time is not constant, and it is difficult to determine convergence.
この発明は上記のような問題点を解消するためになされ
たもので、尖頭値制御と符号間干渉制御を独立して行な
いより安定に収束する線路等化器を得ることを目的とす
る。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a line equalizer that performs peak value control and intersymbol interference control independently and converges more stably.
この発明に係る線路等化器は、利得変化量の周波数特性
が平坦である平坦利得可変回路と、この平坦利得可変回
路の出力信号の尖頭値を検出する尖頭値検出器と、この
尖頭値検出器で検出した尖頭値と基準値を比較して尖頭
値と基準値を一致させるように上記平坦利得可変回路の
利得を制御する直流増幅器と、上記平坦利得可変回路の
出力信号を人力とし、利得変化量の周波数特性が線路の
損失特性と同じ傾斜を持つ可変等化器と、この可変等化
器の出力信号の隣接タイムスロットの符号間干渉を検出
し、符号間干渉を零にするように上記可変等化器の利得
を制御する符号間干渉検出器とを備えたものである。A line equalizer according to the present invention includes a flat gain variable circuit whose frequency characteristic of gain change is flat, a peak value detector that detects the peak value of an output signal of the flat gain variable circuit, and a DC amplifier that compares the peak value detected by the peak value detector with a reference value and controls the gain of the variable flat gain circuit so that the peak value and the reference value match; and an output signal of the variable flat gain circuit. A variable equalizer whose frequency characteristic of gain change has the same slope as the loss characteristic of the line, and intersymbol interference in adjacent time slots of the output signal of this variable equalizer are detected, and the intersymbol interference is detected manually. and an intersymbol interference detector that controls the gain of the variable equalizer so as to make it zero.
この発明における線路等化器は、平坦利得可変回路の出
力を尖頭値検出器に入力し、直流増幅器で平坦利得可変
回路の利得を制御するとともに、平坦利得可変回路の後
段に可変等化器をおいてその出力を符号間干渉検出器に
人力することにより符号間干渉検出器が可変等化器の利
得を制御する。従って、平坦利得可変回路が収束した後
に符号間干渉検出器によって制御され尖頭値を変えるこ
となく符号間干渉を零にする。The line equalizer in the present invention inputs the output of the variable flat gain circuit to a peak value detector, controls the gain of the variable flat gain circuit with a DC amplifier, and has a variable equalizer installed after the variable flat gain circuit. By manually inputting the output to the intersymbol interference detector, the intersymbol interference detector controls the gain of the variable equalizer. Therefore, after the flat gain variable circuit converges, it is controlled by the intersymbol interference detector to reduce the intersymbol interference to zero without changing the peak value.
以下、この発明の一実施例を図について説明する。第1
図において、(1)は入力端子、(2)は利得変化量の
周波数特性が平坦である平坦利得可変回路、(3)は周
波数特性が線路の損失特性と同じ傾斜を持つ可変等化器
、(4)は平坦利得可変回路(2)の出力信号の尖頭値
を検出する尖頭値検出器、(5)は尖頭値検出器(4)
で検出した尖頭値と基準値を比較して尖頭値と基準値を
一致させる様に平坦利得可変回路(2)の利得を制御す
る直流増幅器、(6)は可変等化器(3)の出力信号の
隣接タイムスロットの符号間干渉を検出し、それに対応
した信号を検出して可変等化器(3)の利得を制御する
符号間干渉検出器、(7)は出力端子である。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is an input terminal, (2) is a flat gain variable circuit whose frequency characteristic of gain change is flat, and (3) is a variable equalizer whose frequency characteristic has the same slope as the loss characteristic of the line. (4) is a peak value detector that detects the peak value of the output signal of the flat gain variable circuit (2), and (5) is a peak value detector (4).
A DC amplifier (6) is a variable equalizer (3) that controls the gain of the flat gain variable circuit (2) by comparing the detected peak value with a reference value so that the peak value and the reference value match. An intersymbol interference detector (7) is an output terminal for detecting intersymbol interference in adjacent time slots of the output signal of and detecting a signal corresponding to the intersymbol interference to control the gain of the variable equalizer (3).
次に、動作について説明する。入力端子(1)より人力
された受信信号は平坦利得可変回路(2)に入力される
。平坦利得可変回路(2)の出力は尖頭値検出器(4)
に入力され、尖頭値が基準値と等しくなる様に直流増幅
器(5)が平坦利得可変回路(2)の利得を制御する。Next, the operation will be explained. A received signal input manually from the input terminal (1) is input to the flat gain variable circuit (2). The output of the flat gain variable circuit (2) is the peak value detector (4)
The DC amplifier (5) controls the gain of the flat gain variable circuit (2) so that the peak value is equal to the reference value.
尖頭値が基準値と一致した平坦利得可変回路(2)の出
力信号は可変等化器(3)に入力される。可変等化器(
3)の出力信号は符号間干渉検出器(5)に入力され、
符号間干渉が0になる様に可変等化器(3)の利得が制
御される。この時、可変等化量(3)の利得は線路損失
の傾斜部分のみに相当し、利得を変化させても符号間干
渉の値のみ変化し尖頭値は変化しない様に設定されてい
る。The output signal of the flat gain variable circuit (2) whose peak value coincides with the reference value is input to the variable equalizer (3). Variable equalizer (
The output signal of 3) is input to the intersymbol interference detector (5),
The gain of the variable equalizer (3) is controlled so that intersymbol interference becomes zero. At this time, the gain of the variable equalization amount (3) corresponds only to the slope portion of the line loss, and is set so that even if the gain is changed, only the intersymbol interference value changes and the peak value does not change.
この様に構成することにより、平坦利得可変回路(2)
で尖頭値を基準値に一致させ、その後に可変等化器(3
)で符号間干渉を0にすることができる。With this configuration, the flat gain variable circuit (2)
to match the peak value with the reference value, and then a variable equalizer (3
) can reduce intersymbol interference to 0.
なお、上記実施例では、平坦利得可変回路(2)は直流
増幅器(5)を用いてアナログ信号により利得制御され
たが、ディジタル信号によって利得制御されるものでも
良い。In the above embodiment, the gain of the variable flat gain circuit (2) is controlled by an analog signal using the DC amplifier (5), but the gain may be controlled by a digital signal.
(発明の効果)
以上の様に、この発明によれば、平坦利得可変回路によ
る尖頭値制御と可変等化器による符号間干渉制御を独立
に行なっているので、収束時間もほぼ一定でまたより安
定した収束判定をすることができるという効果がある。(Effects of the Invention) As described above, according to the present invention, since the peak value control by the variable flat gain circuit and the intersymbol interference control by the variable equalizer are performed independently, the convergence time is also approximately constant. This has the effect of making a more stable convergence determination possible.
第1図はこの発明の一部実施例による線路等化量を示す
ブロック図、第2図は従来の線路等化器のブロック図、
第3図は等化波形図である。
(1)は入力端子、(2) は平坦利得可変回路、(3
)は可変等化器、(4)は尖頭値検出器、(5)は直流
増幅器、(6)は符号間干渉検出器、(7)は出力端子
。
尚、図中同一符号は同−又は相当部分を示す。FIG. 1 is a block diagram showing the amount of line equalization according to a partial embodiment of the present invention, FIG. 2 is a block diagram of a conventional line equalizer,
FIG. 3 is an equalized waveform diagram. (1) is the input terminal, (2) is the flat gain variable circuit, (3
) is a variable equalizer, (4) is a peak value detector, (5) is a DC amplifier, (6) is an intersymbol interference detector, and (7) is an output terminal. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
と、この平坦利得可変回路の出力信号の尖頭値を検出す
る尖頭値検出器と、この尖頭値検出器で検出した尖頭値
と基準値を比較して尖頭値と基準値を一致させるように
上記平坦利得可変回路の利得を制御する直流増幅器と、
上記平坦利得可変回路の出力信号を入力とし、利得変化
量の周波数特性が線路の損失特性と同じ傾斜を持つ可変
等化器と、この可変等化器の出力信号の隣接タイムスロ
ットの符号間干渉を検出し、符号間干渉を零にするよう
に上記可変等化器の利得を制御する符号間干渉検出器と
を備えたことを特徴とする線路等化器。A flat gain variable circuit whose frequency characteristic of gain change is flat, a peak value detector that detects the peak value of the output signal of this flat gain variable circuit, and a peak value detected by this peak value detector. a DC amplifier that controls the gain of the flat gain variable circuit so as to match the peak value and the reference value by comparing the peak value and the reference value;
A variable equalizer which receives the output signal of the above flat gain variable circuit as input and whose frequency characteristic of gain change has the same slope as the loss characteristic of the line, and intersymbol interference between adjacent time slots of the output signal of this variable equalizer. and an intersymbol interference detector that controls the gain of the variable equalizer so as to reduce intersymbol interference to zero.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP678190A JPH03211920A (en) | 1990-01-16 | 1990-01-16 | Line equalizer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP678190A JPH03211920A (en) | 1990-01-16 | 1990-01-16 | Line equalizer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03211920A true JPH03211920A (en) | 1991-09-17 |
Family
ID=11647716
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP678190A Pending JPH03211920A (en) | 1990-01-16 | 1990-01-16 | Line equalizer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03211920A (en) |
-
1990
- 1990-01-16 JP JP678190A patent/JPH03211920A/en active Pending
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