JPS6334971A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6334971A JPS6334971A JP61179541A JP17954186A JPS6334971A JP S6334971 A JPS6334971 A JP S6334971A JP 61179541 A JP61179541 A JP 61179541A JP 17954186 A JP17954186 A JP 17954186A JP S6334971 A JPS6334971 A JP S6334971A
- Authority
- JP
- Japan
- Prior art keywords
- lift
- spacer
- channel
- polyimide
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 title claims description 3
- 230000003068 static effect Effects 0.000 claims abstract description 16
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 6
- 238000010292 electrical insulation Methods 0.000 claims description 6
- 229920000620 organic polymer Polymers 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 239000010410 layer Substances 0.000 abstract description 28
- 125000006850 spacer group Chemical group 0.000 abstract description 15
- 239000011229 interlayer Substances 0.000 abstract description 14
- 239000004642 Polyimide Substances 0.000 abstract description 10
- 229920001721 polyimide Polymers 0.000 abstract description 10
- 239000002184 metal Substances 0.000 abstract description 7
- 229910052751 metal Inorganic materials 0.000 abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 5
- 230000001681 protective effect Effects 0.000 abstract description 3
- 238000000137 annealing Methods 0.000 abstract description 2
- 238000001312 dry etching Methods 0.000 abstract 1
- 150000003949 imides Chemical class 0.000 abstract 1
- 239000002120 nanofilm Substances 0.000 abstract 1
- 238000001039 wet etching Methods 0.000 abstract 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 101100401100 Caenorhabditis elegans mes-1 gene Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 230000009291 secondary effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- -1 spacer nitride Chemical class 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野］
この発明は、ＧａＡｓ自己魯合型ＭＥＳＦＥＴを用いた
スタティックＲＡＭの製造工程において層間絶縁膜や保
護膜のもつストレスによってしきい値電圧ｖｔｈのシフ
トを防止する半導体装置の構造に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to the shift of threshold voltage vth due to stress in interlayer insulating films and protective films in the manufacturing process of static RAM using GaAs self-combining MESFETs. The present invention relates to a structure of a semiconductor device that prevents this.
第２図は従来のＧａＡｓスタティックＲＡＭの自己整合
型ＭＥＳ１’ＥＴ部を示す断面図であり、第２図Ａ −
Ｄは自己整合型ＭＥ８ＦＢ’ｌ’の製造方法を説明する
ためにその主要段階における状態を製造順序に従って示
した断面図であり、第２図ＥはスタティックＲＡＭの製
造工程が終了した時点の自己整合型ＭＥ８ＦＥＴの状態
を示した断面図である。図において、（１）ばＧａＡｓ
基板、（２）はチャネルｎ、（３）はオーミックコンタ
クトのためのＦ？！、ｄＪ層ｎ１（４）はゲート電極、
（５）はリフトオフスペーサシリコン窒化膜、（７）は
オーミンク金属、（８）は第１層間絶縁層、（９）は第
１層配線、（ｌＯ）は第２層間絶縁層、（１１） Ｉ／
ｉ＠ ２層配線膜、（１２）は保譲膜、（１３）はフォ
トレジストである。FIG. 2 is a cross-sectional view showing a self-aligned MES 1'ET section of a conventional GaAs static RAM.
D is a cross-sectional view showing the state at the main stages according to the manufacturing order in order to explain the manufacturing method of the self-aligned ME8FB'l', and FIG. FIG. 3 is a cross-sectional view showing the state of a type ME8FET. In the figure, (1) is GaAs
Substrate, (2) is channel n, (3) is F? for ohmic contact. ! , dJ layer n1(4) is a gate electrode,
(5) is a lift-off spacer silicon nitride film, (7) is an ohmink metal, (8) is a first interlayer insulating layer, (9) is a first layer wiring, (lO) is a second interlayer insulating layer, (11) I /
i@ two-layer wiring film, (12) is a preservation film, and (13) is a photoresist.
次に作用について説明する。第２図Ａに示すようにＧａ
Ａｓ基板（１） Ｋチャネルｎ（２）、ゲート電極（４
へ能動層ｎ”（３）を形成しキャップレスアニール法に
よりチャネルｎ（２）及び能動層ｎ”（３）を活性化さ
せて２く。Next, the effect will be explained. As shown in Figure 2A, Ga
As substrate (1) K channel n (2), gate electrode (4
An active layer n'' (3) is formed thereon, and the channel n (2) and active layer n'' (3) are activated by capless annealing.
次に第２図Ｂに示すようにリフトオフスペーサシリコン
窒化膜（５）をプラズマＣＶＤ法やスパッタ法等により
形成する。次に第２図Ｃに示すように７オトレジスト（
１３）をマスクとしてリフトオフスペーサシリコン窒化
膜（５）を湿式または乾式により工７ ｆングし能動層
♂（３）を露出させる。次いで電子ビームまたは抵抗加
熱式蒸着によりオーミンク金属（７）を形成する。次い
で溶剤によりフォトレジスト（１３）を除去しフォトレ
ジスト（１３）上に形成されたオーミンク金属（７）を
リフトオフする。第２図りはり７トオ７後の状態図であ
る。次いで第２図Ｅに示すように成膜技術及び写真製版
・エツチング技術を駆使して第１層間絶縁層（８）、第
１層配線１俣（９）、第２層間絶縁膜（ｌＯ）、第２層
配線膜（１１）、保護膜（１２）ｒ順次形成しスタティ
ックＲＡＭの製造工程が終了する。Next, as shown in FIG. 2B, a lift-off spacer silicon nitride film (5) is formed by plasma CVD, sputtering, or the like. Next, as shown in Figure 2C, 7 otoresist (
Using mask 13), lift-off spacer silicon nitride film (5) is etched by wet or dry process to expose active layer ♂ (3). Then, an ohmink metal (7) is formed by electron beam or resistance heating vapor deposition. Next, the photoresist (13) is removed using a solvent, and the ohmink metal (7) formed on the photoresist (13) is lifted off. It is a state diagram after the second measurement 7 to 7. Next, as shown in FIG. 2E, a first interlayer insulating layer (8), one strip of first layer wiring (9), a second interlayer insulating film (lO), A second layer wiring film (11) and a protective film (12) are sequentially formed to complete the manufacturing process of the static RAM.
〔発り１が解決しようとする問題点Ｊ
従来のＧａＡｓスタティックＲＡＭは以上のようにａ成
されているのでリフトオフスペーサシリコン窒化膜（５
）がゲート電極（４）、チャネルｎ（２）にストレスを
与えしきい値電圧マｔｈがシフトしバラツキも増大する
。また第２図Ｅに示すようにゲート電極（４）、チャネ
ルｎ（２）上に層間絶縁層及び配線膜が多層に形成され
るためその都度ストレスが与えラレるためしきい値電圧
ｖｔｈがシフトしバラツキが増大しＧａＡｓスタティッ
クＲＡＭの性能及び歩留りを低下させる。[Problem J that Prologue 1 attempts to solve Since the conventional GaAs static RAM is constructed as described above, the lift-off spacer silicon nitride film (5
) applies stress to the gate electrode (4) and channel n(2), causing a shift in the threshold voltage Math and an increase in variation. In addition, as shown in FIG. 2E, since multiple interlayer insulating layers and wiring films are formed on the gate electrode (4) and channel n (2), stress is applied each time and the threshold voltage vth shifts. This increases the variation and reduces the performance and yield of the GaAs static RAM.
この発明は上記のような問題点を解消するためになされ
たものでしきい値電圧ｖｔｈのシフトを防止できるとと
もＫしさい値電圧ｖｔｈのバラツキを抑制できるＧａＡ
ｓスタティックＲＡＭを得ることを目的とする。This invention was made in order to solve the above-mentioned problems, and it is possible to prevent the shift of the threshold voltage vth and suppress the variation in the threshold voltage vth.
The purpose is to obtain s static RAM.
［問題点を解決するための手段Ｊ
この発明に係るＧａＡ３スタティックＲＡＭ１す７トオ
７スペーサ窒化膜（５）を＃熱性、耐薬品性、電気絶縁
性を有する有機高分子膜に変更したものである。[Means for solving the problem J The GaA3 static RAM 17 spacer nitride film (5) according to the present invention is changed to an organic polymer film having heat resistance, chemical resistance, and electrical insulation properties. .
〔作用Ｊ
この発明におけるＧａＡｓスタティックＲＡＭの構造は
リフトオフスペーサに耐熱性、耐薬品性、電気絶縁性を
有する有機高分子膜を採用したことによりゲート電極（
４）、チャネルｎ（２）に与えるストレスを低減ししき
い値電圧ｖｔｈのシフトを防止しバラツキを抑制する。[Function J] The structure of the GaAs static RAM in this invention uses an organic polymer film having heat resistance, chemical resistance, and electrical insulation properties as the lift-off spacer, so that the gate electrode (
4) The stress applied to channel n(2) is reduced to prevent shifts in threshold voltage vth and suppress variations.
またその後形成される多層の層間絶縁層及び配線膜のゲ
ート電極（４）、チャネルｎ（２）に与えるストレスが
緩和されしきい値電圧７ｔｈのシフトを防止しバラツキ
を抑制する。Further, the stress applied to the gate electrode (4) and channel n (2) of the multilayer insulating layer and interconnection film formed thereafter is alleviated, thereby preventing a shift in the threshold voltage 7th and suppressing variations.
〔発明の実施例Ｊ
以゛ド、この発明の一失施例を図について説明する。な
お第２図と同−符勿を付したものは同−又は相当部分を
示す。第１図Ａ −Ｄはこの発明を説明するためにその
主要段階における状態を示した断面図で第１図Ｅはこの
発明によるＧａＡｓスタティックＲＡＭの製造工程が終
Ｔした時点の状態を示゛す断面図である。第１図におい
て（６〕は耐熱性、耐薬品性、電気絶縁性を有する有機
高分子膜、例えばポリイミドにより形成されたリフトオ
フスペーサポリイミドである。[Embodiment J of the Invention Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Note that the same reference numerals as in FIG. 2 indicate the same or equivalent parts. 1A to 1D are cross-sectional views showing the state at the main stages for explaining the present invention, and FIG. 1E shows the state at the end of the manufacturing process of the GaAs static RAM according to the present invention. FIG. In FIG. 1, (6) is an organic polymer film having heat resistance, chemical resistance, and electrical insulation properties, such as a lift-off spacer polyimide made of polyimide.
次に作用について説明する。まず第１図Ａの状態を従来
方法第２図Ａと同様に形成する。次に第１図Ｂに示すよ
うにり７トオフスベーサ用としてポリイミドをスピン塗
布やロールコータ塗布法等により形成し、例えば１５０
℃１時間、４００’Ｃ１時間のステップキュアにより完
全にイミド化させてリフトオフスペーサポリイミド（６
）を形成する。Next, the effect will be explained. First, the state shown in FIG. 1A is formed in the same manner as the conventional method shown in FIG. 2A. Next, as shown in FIG.
Completely imidized by step curing at 400°C for 1 hour and lift-off spacer polyimide (6
) to form.
次に第１図Ｃに示すように７オトレジス） （１３）を
マスクトシてリフトオフスペーサポリイミド（６）を湿
式（例えばヒドラジンヒトラード）または乾式（酸素Ｒ
工Ｅ）によりエツチングし能動層ｎ” （３）を露出さ
せる。次いで電子ヒームまたｅよ抵抗加熱式蒸着により
オーミンク金属（７）を形成する。その後％１図りは第
２図りと同様に形成し、第１図Ｅは第２図Ｅと同様に形
成しスタティックＲＡＭの製造工程が終了する。Next, as shown in FIG.
The active layer n'' (3) is exposed by etching using step E). Then, the Ohmink metal (7) is formed by electron beam or resistive heating evaporation. After that, the %1 pattern is formed in the same manner as the second pattern. , FIG. 1E are formed in the same manner as FIG. 2E, and the manufacturing process of the static RAM is completed.
本発明によればしきい値電圧ｖｔｈのシフトを防止しバ
ラツキの増大を抑制できるがその他副次同な効果として
リフトオフスペーサ暎としてシリコン窒化膜からポリイ
ミドに変更したため比誘電率が７から３．７と半減しダ
ート電極（４）と第１層配線膜（９）との間ンζ生じる
配線間容量を減小させＧａＡｓスタティックＲＡＭの性
能を向上できる。また第１層間絶縁層（８）以降に生ず
るストレスを嶽和し一８基板（１）のそりの経時変化を
抑制するため写真製版工程における重ね合わせ精度及び
フォトレジストの解像度を安定させることができる。ま
たポリイミドは露光波長を吸収するため第１層間絶縁層
（８）以降に行なう写真製版工程において７オトレジス
トの解像度が向上する。According to the present invention, it is possible to prevent the shift of the threshold voltage vth and suppress the increase in variation, but as a secondary effect, the dielectric constant is changed from 7 to 3.7 because the lift-off spacer is changed from silicon nitride film to polyimide. The capacitance between the wirings generated between the dirt electrode (4) and the first layer wiring film (9) can be reduced by half, and the performance of the GaAs static RAM can be improved. In addition, the stress generated after the first interlayer insulating layer (8) is suppressed and the warpage of the substrate (1) is suppressed from changing over time, making it possible to stabilize the overlay accuracy and photoresist resolution in the photolithography process. . Furthermore, since polyimide absorbs the exposure wavelength, the resolution of the 7 photoresist is improved in the photolithography process performed after the first interlayer insulating layer (8).
なお上記実施例では、リフトオフスペーサにポリイミド
を用いたが池の耐熱性、耐薬品性、電気絶縁性を肩する
有機高分子膜を用いても上記実施例と同様の効果が得ら
れる。Although polyimide is used for the lift-off spacer in the above embodiment, the same effects as in the above embodiment can be obtained by using an organic polymer film that takes care of the heat resistance, chemical resistance, and electrical insulation properties of the spacer.
以上のように、この発明によればゲート電極形成後のオ
ーミック金属形成においてり７トオ７スベーサとして耐
熱性、耐薬品性、電気絶縁性を有する有機高分子膜を用
いたのでゲート電極及びチャネルｎｒこ与えられるスト
レスを緩和できしきい値電圧ｖｔｈのシフトを防止しパ
ランキの増大を抑制しＧａＡｓスタティックＲＡＭの設
計通りの性能が得られ、また歩留りも向上する。As described above, according to the present invention, an organic polymer film having heat resistance, chemical resistance, and electrical insulation properties is used as a base material in forming the ohmic metal after forming the gate electrode. The applied stress can be alleviated, a shift in the threshold voltage vth can be prevented, and an increase in paranchi can be suppressed, so that the designed performance of the GaAs static RAM can be obtained and the yield can also be improved.
第１図はこの発明の一実施例によるＧａＡｓスタティッ
クＲＡＭの自己整合型ＭＩＳＦＥＴ部を示す断面図、第
２図は従来のＧａＡｓスタティックＲＡＭの自己整合型
ＭＥＳＦＫＴ部を示す断面図である０（１）はＧａＡｓ
基板、（２）はチャネルｎ、（３）は能動層ｎ、（４）
はゲート電極、（５）はリフトオフスペーサシリコンｆ
ｆｌ化膜、（６）はリフトオフスペーサポリイミド、（
７）はオーミック金線、（８）は第１層間絶縁層、（９
）は第１層間絶縁、（１０）は第２層間絶縁層、（１１
）は第２層間絶縁、（１２） Ｖｉ保保護膜（１３）は
７オトレジストである。
なお、図中、同一符号は同一、又は同等部分を示す。FIG. 1 is a sectional view showing a self-aligned MISFET section of a GaAs static RAM according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a self-aligned MESFKT section of a conventional GaAs static RAM. is GaAs
Substrate, (2) channel n, (3) active layer n, (4)
is the gate electrode, (5) is the lift-off spacer silicon f
fl film, (6) is lift-off spacer polyimide, (
7) is an ohmic gold wire, (8) is a first interlayer insulating layer, (9
) is the first interlayer insulation layer, (10) is the second interlayer insulation layer, (11
) is the second interlayer insulation, (12) the Vi protection film (13) is the 7-photoresist. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
己整合型ＭＥＳＦＥＴ部のゲート電極及びチャネルｎ上
に耐熱性、耐薬品性、電気絶縁性を有する有機高分子膜
を形成したことを特徴とする半導体装置の製造方法A method for manufacturing a semiconductor device, characterized in that an organic polymer film having heat resistance, chemical resistance, and electrical insulation properties is formed on the gate electrode and channel n of a self-aligned MESFET section in the manufacturing process of a GaAs static RAM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61179541A JPS6334971A (en) | 1986-07-29 | 1986-07-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61179541A JPS6334971A (en) | 1986-07-29 | 1986-07-29 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6334971A true JPS6334971A (en) | 1988-02-15 |
Family
ID=16067553
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61179541A Pending JPS6334971A (en) | 1986-07-29 | 1986-07-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6334971A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5185278A (en) * | 1990-10-22 | 1993-02-09 | Motorola, Inc. | Method of making self-aligned gate providing improved breakdown voltage |
-
1986
- 1986-07-29 JP JP61179541A patent/JPS6334971A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5185278A (en) * | 1990-10-22 | 1993-02-09 | Motorola, Inc. | Method of making self-aligned gate providing improved breakdown voltage |
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