JPS6333930A - Digital-analog conversion circuit - Google Patents

Abstract

PURPOSE:To decrease the rate of increase in the element number even with increased bit number by constituting a current branch means forming an output current to each input bit and forming the output current as a half of a high- order bit current introduced from a high-order bit in supplying the output current to an output resistor. CONSTITUTION:A 1/2 shunt circuit DV1 is provided in addition to a conversion section CV1 obtaining 1-bit analog conversion processing and an output current of the 1/2 current shunt circuit DV1 acts like a constant current of a low-order bit analog conversion processing section CV2. The 1/2 current shunt circuit DV1 uses a transistor (TR) Q1a and a TR Q1g forming a current mirror circuit as a constant current source. That is, since the output current of each bit is a half of the current of the highorder bit at all times, it is not required to form an output current by changing the resistance (increasing element number) for the purpose, and even if the bit number is increased, number of elements (constant number) required for 1-bit processing has only to be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a digital-to-analog conversion circuit suitable for integration into an integrated circuit.

(Conventional Example) In recent years, integrated circuit manufacturing technology has progressed, and research is also underway to allow analog circuits and digital circuits to coexist within the same chip. The circuit required here is a circuit that converts a digital signal into an analog signal.

FIG. 2 shows an example of a conventional digital-to-analog conversion circuit. Transistor QAOd has its base collector connected in common, and is connected to ground potential line 1 via resistor RAo. Also, the emitter of transistor QAO is connected to resistor F
It is connected to power supply (vcc) line 2 via LBO.

Transistor QAo and resistor RAO2RBO act as a common constant current source for the circuit that converts each human input bit (v1 to Vn) into analog.

The input bit (vl) is applied to the emitter of transistor QBZ. The input bit (Vz) is, for example, the most significant bit (MSB). Transistor QB1t
QCI has both paces and collectors in common and is connected to the collector of C transistor QAJ. The emitter of transistor QCI is connected to output terminal 3.

Resistor RCO is the output resistance. The transistor QAJ
The pace of is connected to the base of transistor QAO,
The collector is connected to power supply line 2 via resistor RBJ.

Bit input (Vz) is @1'''! ! When the voltage is high, a current 41 flows through the transistors QAl and QCI, generating a voltage across the resistor RCil.

A circuit similar to the above is provided for each human input bit (v2 to Vn) and connected in parallel. For input bit (v2), transis/QA, ? ,QB2,QC
2. The circuit with the resistor RB2 works and its output current (2 can be passed through the resistor RCf7. Also, the input pin)
(VJ), transistor QA3. QB3. Q
C3, resistance RB,? The circuit works, and the input bit (V
n), tran-dimeta QAn, QBn, QC
n, a circuit with resistor RBn works.

However, in the above circuit, the resistors RBO, RBJ...
When looking at the value of Run, RB (7=RBZ, RB'=
=g2XELBO1RB,? = 4 x RBOlR
The relationship is Bn = 2''-'X RBO. Therefore, RBO = RBJ<RB'<RB3<RBn.

Therefore, if we look at the current i0, 41.42...in flowing to the collector of the transistor QAO-QAn, we get (0
= There is a relationship.

To summarize the above, ・・・・・・・・・(1) io = 41 = 2Xt2 = 4X<,? =
2n-' X in (2) can be obtained. This relationship is shown in a table, and the output voltage V. When ut is calculated, it is as shown in Table 1 below. ·however,
The number of input bits is 3 bits.

1st As seen from Table 1 above, if the value of the input bit increases, the output voltage V. ut also increases. The relationships shown in Table 1 are based on the premise that equation (2) holds true. Therefore, in reality, transistor glue 7. In order to prevent the relationship in equation (2) from discontinuing due to the influence of (amplification factor), transistor QA (7
~The emitter area of QAn is changed to set an appropriate operating point according to the current.

(Problems to be Solved by the Invention) The conventional digital-to-analog conversion circuit described above has a simple configuration and can be said to be an excellent conversion circuit when the number of bits used is small. However, in the case of this circuit, the number of bits is reduced to 1
As shown in Table 2, when attempting to enlarge the number of elements, the rate of increase in the number of elements is extremely large.

Table 2 However, for the above-mentioned clothing 2, the resistance RBI) is taken as one element, and RB
2 is 2 x RB17, so 2 elements, RBJ i'
i a Since it is an XRBO, there are 3 molecules, and the emitter area is 2.
In the case of , it is calculated as a double child.

As described above, in conventional circuits, the number of elements increases rapidly as the number of bits increases, and the chip area is extremely large to construct the 6-bit or 8-bit conversion circuit required in a normal digital circuit. There is a problem with becoming.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a digital-to-analog converter circuit that has a low rate of increase in the number of elements even when the number of bits increases and is suitable for integration into an integrated circuit.

[Structure of the Invention] (Means for Solving the Problems) This invention provides an output current for each manually-powered bit, and when supplying this to an output resistor, the output current is introduced from the upper bit to the upper bit. It constitutes a shunting means that generates current as a bar.

(Function) With the above-mentioned shunting means, the output current of each bit is always one branch of the upper bit, so by changing the resistance value (increasing the number of elements), the output current Even if the number of bits increases, it is only necessary to increase the number of elements (a constant number) required for processing one pit, and there is no need to double the number of elements as in the conventional case.

(Example) Examples of the present invention will be described below with reference to the drawings. 1st
The figure shows one embodiment of the present invention, and the data to be converted into analog data is input to the input terminal I as input bits (v1 to Vn).
It is supplied to N7 to INn. Further, a predetermined reference voltage V)I is supplied to the terminal 11.

The emitter of the transistor Qc is connected to a ground potential line 1 via a resistor R1m, and the pace collector is commonly connected to a power supply (cc) line 2 via a resistor RJb. Nine, the emitter of the transistor Qlb is the resistor R1.
It is connected to the ground potential line 1 via a, and its pace is connected to the pace KW of the transistor q11. The collector of transistor Qlb is connected to the emitters of transistors Qlc and Qld which perform switching operations in response to the input bit (vg).

The reference voltage ■ is supplied to the pace of the transistor Qlc, and the input bit (vl) is supplied to the pace of the transistor Qld.
is supplied. The collector of the transistor Qle is connected to the four-source line 2, and the collector of the transistor QJd is connected to the collector and pace of the transistor QJe forming a current mirror circuit. Transistor Qle
, Qlf are connected in common and the transistor Qle
The emitter of the transistor QJf is connected to the power supply line 2 through a resistor RJd, and the emitter of the transistor QJf is connected to the power supply line 2 through a resistor R1e.

The collector of transistor QJf has an output 'direct voltage V. U.

is connected to output terminal 3 for deriving . An output resistor 'out is connected between this output terminal 3 and the ground line 1.

The above digital-to-analog converter converts the input bit (vl)
When is 'O', transistor QZc is turned on. Transistors QZa and QJb are current sources using a current mirror circuit that flows constant current i0 = 41. On the other hand, when input bit (vI) is '1', , transistor Ql
The states of e and Qld are reversed, and a current (1) flows through the transistor QJd. The same current flows through the transistor Q1.
. It also flows to the output resistor R0ut via the current mirror circuit formed by Qlt.

By the way, in this invention, as described above, the W shunt circuit DVI is provided in association with the converter CVI that obtains 1-bit analog conversion processing, and the output current of this W shunt circuit Dv1 is used for analog conversion of the lower bit. This acts as a constant current for the processing section CV2.

The dedicated shunt circuit Dv1 operates with a transistor Q1g forming a current mirror circuit together with the transistor Qc as a constant current source.

That is, the emitter of the transistor QZg is connected to the ground potential terminal 1 via the resistor RJf, and the collector is connected to the common emitter of the transistor QJhlQc. The pace of these transistors QJh and QC is determined by a predetermined reference voltage V.
U is commonly supplied. The collector of the transistor Qlb is connected to the power supply line 2, and the collector of the transistor QJt is connected to the collector and hipase of the transistor Qlj and the pace of the transistor Qlk. The transistors QJjlQJk form a current mirror circuit, and each emitter of the transistor Q'jsQJk is connected to the power supply line 2 via the resistors RJ g and RZ h, respectively. The collector of the transistor QJk is connected to the collector and pace of the transistor Q, 2m, which acts as a current source of the lower analog conversion processing unit CVZ.

The output current of the dedicated shunt circuit DVI is the function of the bit current that basically flows through the analog conversion processing section CVZ. That is, the transistor Q1g is the transistor Ql
A has a current mirror relationship with a, and the same current as the current io flows through its collector.

The collector current of this transistor Q1g is shunted by the transistor Q1bsQc. Transistor QZh.

Since the same reference voltage is supplied to the pace of QJi, the current flowing through both transistors Qlh and Ql i is
Equal to child/2. The current thus depleted becomes a basic constant current in the lower bit analog conversion processing unit CVJ.

The analog conversion processing unit CV2 is also the analog conversion processing unit C
It has the same configuration as VI, and transistors Q2a to Q2f
, resistors RZa, and R'c to R2.

This analog conversion processing section CV2 shares the output terminal 3 and output resistance Rout with the analog conversion processing section CVI described above. This analog conversion processing section CV2 is also provided with a dedicated/divided circuit DV2. This rod shunt circuit DV2 is also constituted by transistors QJg to QJk and resistors R2f to RJh, similarly to the rod shunt circuit DVJ.

The operation of the analog conversion processing unit CV2 is also similar to that of the analog conversion processing unit CVI described above. When the input bit (V, ?) becomes high level, the transistor Q2d is turned on and the same current as its collector current is supplied to the output resistor R0ut via the current mirror circuit. In addition, ■ Shunt circuit Dv2
This circuit obtains the same operation as the above-mentioned Iso shunt circuit Dv1, and specifically shunts the basic current of the analog conversion processing section CV2, and supplies the resulting output as the basic current to the analog conversion processing section of a lower order. In this way, in this circuit, the reduced basic current is supplied to the analog conversion processing section and the shame shunt circuit in the lower order one after another.

Tran-dimeta QJa ~Q3f, resistance RJm, RJ
c % RJ@ is an analog conversion processing unit for input bits (vg), and transformer
n! , resistance Rna.

This is an analog conversion processing unit for Roe to Rn5ti input bits (Vn).

Now, resistors RZm, RZc, RJf, R2a, Rffia
, Rjf, RJa, RJa.

The currents flowing in ... are respectively io, H, 42, 43,
44,45°66.47..., the following relationship exists.

(0=what=i2.i3=(4=shi5-deli0゜child=(
7=% (O Therefore, in the above circuit, if only the input bit (VJ) is 11", a voltage of vout = 10 x Rout will be generated at the output terminal 3, and the input pitch will be 1") (If only vg is 1") The voltage of vout=0XROut is output terminal 3
occurs in

The output voltage for 3-bit input is shown in Table 3 below.
become that way.

Table 3 As mentioned above, this circuit operates as a digital-to-analog conversion circuit. Next, Table 4 below shows the number of elements when the number of bits is increased.

Table 4 As shown in Table 4 above, in the case of the present invention, each additional bit increases the number of elements by 18. As can be seen by comparing Table 4 with Table 2 of the conventional circuit, the circuit of the present invention has more prime numbers up to 5 bits, but when the number of prime numbers exceeds 6 bits, the number M of the circuit of the present invention becomes significantly larger. and few.

[Effects of the Invention] As explained above, the present invention is advantageous. In particular, for inputs of 6 bits or more, which are frequently used, analog conversion can be realized with fewer prime numbers than conventional ones, and the chip area when integrated into a circuit can also be reduced.

[Brief explanation of the drawing]

FIG. 1 shows a circuit I-1 showing an embodiment of the present invention. FIG. 2 shows a conventional digital-to-analog conversion circuit. C¥1, CN3...Analog conversion processing unit, DVJ,
DV2... cup shunt circuit.

Claims (1)

[Claims] A first analog conversion that supplies a reference voltage to one input of a differential amplifier, a bit input to the other input, and supplies the output current of this differential amplifier to an output resistor via a current mirror circuit. A differential amplifier having a processing unit and a constant current source having a relationship of a constant current source circuit and a current mirror circuit of the differential amplifier, the current flowing through the constant current source being shunted, and the output current being divided by the divided output current. A digital-to-analog conversion circuit comprising: a shunt circuit that supplies a constant current source circuit of a differential device constituting a two-digit analog conversion processing section.