JPS6333827B2 - - Google Patents

Info

Publication number
JPS6333827B2
JPS6333827B2 JP56033803A JP3380381A JPS6333827B2 JP S6333827 B2 JPS6333827 B2 JP S6333827B2 JP 56033803 A JP56033803 A JP 56033803A JP 3380381 A JP3380381 A JP 3380381A JP S6333827 B2 JPS6333827 B2 JP S6333827B2
Authority
JP
Japan
Prior art keywords
microcomputer
modem
phase
carrier
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56033803A
Other languages
Japanese (ja)
Other versions
JPS57148451A (en
Inventor
Shoichiro Takayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP56033803A priority Critical patent/JPS57148451A/en
Publication of JPS57148451A publication Critical patent/JPS57148451A/en
Publication of JPS6333827B2 publication Critical patent/JPS6333827B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/00095Systems or arrangements for the transmission of the picture signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Facsimiles In General (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Description

【発明の詳細な説明】 本発明はフアクシミリ用或は簡易なデータ端末
等の本体制御用のマイコンにて従属制御される回
線の受信用モデムに関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a receiving modem for a line that is slave-controlled by a microcomputer for controlling the main body of a facsimile machine or a simple data terminal.

従来のフアクシミリ受信機或はデータ端末受信
機の受信用モデムについてはモデム専用の電子回
路にて構成され、アナログモデムではアナログ回
路、又は専用のD、S、P、(デイジイタルシグ
ナル、プロセスサ)によりつくられ又デイジイタ
ルモデムではそれ専用のD、S、P、によりつく
られ、受信信号をデータ速度の直列信号として装
置側に引渡している。このため高価なモデムが必
要となりフアクシミリが比較的高価な一因をなし
ている。
The receiving modem of a conventional facsimile receiver or data terminal receiver consists of an electronic circuit dedicated to the modem, while an analog modem consists of an analog circuit or dedicated D, S, P (digital signal, process sensor). The digital modem is created by D, S, and P dedicated to it, and the received signal is delivered to the equipment side as a serial signal at the data rate. This requires an expensive modem, which is one reason why facsimiles are relatively expensive.

従来のG・2フアクシミリのアナログモデム受
信機は第1図アに示す第1図アにおいて1は増巾
器、2はAGC増巾器、3はキヤリヤ検出並びに
キード回路、4はバンドパスフイルタ、5はキヤ
リヤPLL回路、6はキヤリヤ半波毎のON OFF
回路、7は同期検波回路、8は波形等価器、9は
ローパスフイルタ、10は比較器による振幅出力
並びに位相出力取出し回路である。以上のような
各機能回路ブロツクから成立つているのでその価
格低下はなかなか難しい。
A conventional G.2 facsimile analog modem receiver is shown in FIG. 1A, in which 1 is an amplifier, 2 is an AGC amplifier, 3 is a carrier detection and keyed circuit, 4 is a bandpass filter, 5 is a carrier PLL circuit, 6 is ON/OFF for each carrier half wave
The circuit includes a synchronous detection circuit 7, a waveform equalizer 8, a low-pass filter 9, and a circuit for extracting amplitude and phase outputs from a comparator. Since it is made up of each functional circuit block as described above, it is difficult to reduce its price.

またデイジタルモデムである2400ボーモデムは
キヤリヤ1800Hzを用い、之を1/1200秒づつ、4つ
の相の波に切替えることにより信号2ビツトを1
つにまとめた4種の情報をダイビツトとして位相
変調している。第1図イは受信モデムで11は
AGC、12はイコライザ、13は到来波のエン
ベロープ変化を検出してダイビツトの位相変化点
を検出し又15でキヤリア再生し、14でダイビ
ツトの中央部のOクロス位相点の変化分を検出
し、16でダイビツトを組合せ信号に変換しこれ
を直列になおし、17でデスクランブルして元の
信号を再生する。
In addition, a 2400 baud modem, which is a digital modem, uses a carrier of 1800 Hz and converts 2 bits of signal into 1 wave by switching it to 4 phase waves at 1/1200 seconds each.
The phase modulation is performed using the four types of information summarized as a dibit. Figure 1 A is the receiving modem and 11 is the receiving modem.
AGC, 12 is an equalizer, 13 detects the envelope change of the arriving wave to detect the phase change point of the dive bit, 15 performs carrier reproduction, 14 detects the change in the O cross phase point at the center of the dive bit, At 16, the dibits are converted into a combined signal, which is serialized, and at 17, it is descrambled to reproduce the original signal.

以上説明したようにモデムは数多くの機能ブロ
ツクからなり比較的高価となつてしまう。
As explained above, modems consist of many functional blocks and are relatively expensive.

本発明はこれらのモデムの複雑高価さを解決す
るため、アナログ回路を最少限とし、且つモデム
制御をフアクシミリ等の装置側のマイコンにて直
接制御したものでその目的は簡素、低価格にあり
以下詳細に説明する。
In order to solve the complexity and high cost of these modems, the present invention minimizes the number of analog circuits and directly controls the modem with a microcomputer on the side of a device such as a facsimile machine.The purpose of this invention is to simplify and reduce the cost. Explain in detail.

第2図は第1の実施例であつて、AM.PMVSB
受信モデムの場合について説明する。第2図1は
AMP2はAGC、3はAGCコントロール部21
はリミツタ“0”検出部でこれをマイコンが走査
し“0”クロス点を検出する。“0”クロスあれ
ばマイコン内タイマを駆動しキヤリヤ2100Hzの半
波の16倍のタイミング即ち67.2Kヘルツをスター
トさせる。このタイミングを回路中の4ビツトカ
ウンタ22に加え、この出力を4ビツト比較器2
3につなぎ第15区間或は第16区間がHとなれば
略、到着キヤリヤと受信側2100Hzが略々同期がと
れていることになる。若しカウンタ14以下で0
クロスが発生すれば、同期のやりなおしをする。
次に2100Hzの8回又は16回毎にこの比較器の出力
をしらべ第15区間に0クロスがあれば到着波形が
やや早いこと、又第16区間に“0”クロスがあれ
ば、到着波がおそいとマイコンが判別し、その指
令で67.2kHzタイマにパルスを1加算又はパル
スを1つ間引く、若し第15及び第16区間の出力が
いずれも“H”の場合は黒信号でキヤリヤ分が全
くないことを示すので、位相追従は行なわない。
又15、16区間の出力がいづれも“L”の場合は同
期ずれであるのでカウンタ及び67.2kHzタイマを
リセツトしなおしてキヤリヤ同期をやりなおす。
又到着波の位相が逆転したかどうかについてはカ
ウンタ22のキヤリー端子からフリツプフロツプ
4200Hzのタイマを取出しこれとリミツタ21の出
力+−をH,Lとし排他論理和をつくり逆相同相
を検出することができる。又信号の振巾分は両波
のエンベロープ検波24を行うことにより容易に
画信号(アナログ信号)をとりだすことができ
る。
FIG. 2 shows the first embodiment, in which AM.PMVSB
The case of a receiving modem will be explained. Figure 2 1 is
AMP2 is AGC, 3 is AGC control section 21
is the limiter "0" detection section, which is scanned by the microcomputer to detect the "0" cross point. If it crosses “0”, it drives the timer in the microcomputer and starts at a timing 16 times the half wave of the carrier 2100Hz, or 67.2KHz. This timing is added to the 4-bit counter 22 in the circuit, and the output is sent to the 4-bit comparator 2.
3 and the 15th or 16th interval becomes H, it means that the arriving carrier and the receiving side 2100Hz are almost synchronized. If the counter is 14 or less, it is 0.
If a cross occurs, resynchronize.
Next, check the output of this comparator every 8 or 16 times at 2100 Hz. If there is a 0 cross in the 15th section, the arriving waveform is a little early. If there is a "0" cross in the 16th section, the arriving wave is The microcomputer determines that it is too late, and instructs the 67.2kHz timer to add 1 pulse or thin out 1 pulse.If the outputs of the 15th and 16th sections are both "H", the carrier portion is output as a black signal. Since this indicates that there is no phase at all, phase tracking is not performed.
If the outputs in the 15th and 16th sections are both "L", it means that there is a synchronization error, so reset the counter and the 67.2kHz timer and redo the carrier synchronization.
Also, whether or not the phase of the arriving wave has been reversed can be determined by checking the flip-flop from the carry terminal of the counter 22.
A 4200 Hz timer is taken out and this and the output +- of the limiter 21 are set to H and L to create an exclusive OR to detect inverse phase and in-phase. Further, the amplitude of the signal can be easily extracted as an image signal (analog signal) by performing envelope detection 24 of both waves.

第1の実施例は2相のAM.PMVSB変調の場合
であるがデイジイタルモデムの受信装置について
も同様に装置のマイコンで直接コントロールする
ことができる。簡単のために2400ホンの4相位相
変調(CCITT.V−26A方式)の場合について説
明する。
The first embodiment is a case of two-phase AM/PMVSB modulation, but the receiving device of a digital modem can also be directly controlled by the microcomputer of the device. For simplicity, a case of 2400 phone four-phase phase modulation (CCITT.V-26A method) will be explained.

13にてエンベロープ変化点をみつけてダイビ
ツトの区切り点を検出する。ダイビツトの中央の
1/3600秒の区間の0クロス点を見つけ(端子3
1)これにより装置マイコンに割り込みをかけ
る。キヤリヤ1800Hzの半波の16倍のタイマ即ち
57.6kHzのタイマをスタートさせ、次のダイビツ
トの中央ゾーンの“0”クロス迄を計算する。こ
の場合カウンタは4ビツトカウンタ22−Bを用
い、16回毎に0にもどる。カウンタの結果を比較
器23に入れ0≦〜<4或は12≦〜≦16ならば位
相差0゜又は180゜、4≦〜<12ならば90゜又は270゜を
判断し、又この後10〜15μs後にリミツタ出力(32
端子)を検出しそのが前のダイビツトと同じ
なら270゜或は180゜、異る場合は90゜或は0゜とする。
この判断動作はマイコンが行う。第3図アはタイ
ミング原理図イは基本回路図を示す。22Aは、
ダイビツト区境から中央ゾーンはじめまでの時間
計算カウンタ、31は中央ゾーン“0”クロス時
に“H”になる。これによりマイコンから、カウ
ンタ22−Bが駆動され、次の割込みがかかつた
とき比較器23A,23Bの結果をよみとり且
つ、10〜15μs後リード32で正負を判断し、ダイ
ビツト情報をきめる。次にダイビツトをマイコン
制御でデスクランブラに入れ結果を読出す。
At step 13, the envelope change point is found and the break point of the dibit is detected. Find the 0 cross point in the 1/3600 second section in the center of the davit (terminal 3
1) This causes an interrupt to be sent to the device microcontroller. Carrier 1800Hz half wave 16 times timer i.e.
Start the 57.6kHz timer and calculate up to the “0” cross in the center zone of the next dibit. In this case, the counter uses a 4-bit counter 22-B and returns to 0 every 16 times. The result of the counter is put into the comparator 23, and if 0≦~<4 or 12≦~≦16, it is determined that the phase difference is 0° or 180°, and if 4≦~<12, it is determined that the phase difference is 90° or 270°. Limiter output (32
If it is the same as the previous dibit, set it to 270° or 180°, otherwise set it to 90° or 0°.
This judgment operation is performed by the microcomputer. Figure 3A shows the timing principle and Figure 3B shows the basic circuit diagram. 22A is
A time calculation counter 31 from the boundary of the Daibit section to the beginning of the central zone becomes "H" when the central zone crosses "0". As a result, the counter 22-B is driven by the microcomputer, and when the next interrupt occurs, the results of the comparators 23A and 23B are read, and after 10 to 15 .mu.s, the lead 32 determines whether the data is positive or negative, and the die bit information is determined. Next, the dibit is put into a descrambler under microcomputer control and the result is read out.

以上の例で説明したように本発明はキヤリヤ再
生等のアナログ的な回路を用いず、“0”クロス
点の位置をしらべデイジイタル的にタイミング追
従をするか、又はタイミング変化を計算し、且
つ、これらの動作を装置制御用のマイコンに割り
込みをかけて実施しているのでIC回路として極
めて簡単になる利点を有している。またこの方法
は4800bps、9600bps等の高速モデムにも応用す
ることができる。
As explained in the above example, the present invention does not use analog circuits such as carrier reproduction, but searches for the position of the "0" cross point and follows the timing digitally, or calculates the timing change, and Since these operations are executed by interrupting the device control microcomputer, it has the advantage of being extremely simple as an IC circuit. This method can also be applied to high-speed modems such as 4800bps and 9600bps.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のフアクシミリ受信を説明する回
路図、第2図は本発明の実施例を説明するための
受信モデムの回路図、第3図は本発明の他の実施
例を説明するためのデイジタルモデムの受信装置
のタイミング原理図及び基本回路図の例である。
FIG. 1 is a circuit diagram for explaining conventional facsimile reception, FIG. 2 is a circuit diagram of a receiving modem for explaining an embodiment of the present invention, and FIG. 3 is a circuit diagram for explaining another embodiment of the present invention. 1 is an example of a timing principle diagram and a basic circuit diagram of a digital modem receiving device.

Claims (1)

【特許請求の範囲】[Claims] 1 アナログ又はデイジイタルの位相変調モデム
の受信機においてキヤリア再生回路を用いず、使
用装置のマイコン制御のタイマーと、モデム受信
機のリミツタ及び“0”クロス検出器及びタイマ
カウンタ、結果比較器(マイコン内部でも可)か
ら構成され、且つこれらの動作が装置マイコンに
て一括して制御されることを特徴とするモデム受
信機。
1 Analog or digital phase modulation modem receivers do not use a carrier regeneration circuit, but use the device's microcomputer-controlled timer, the modem receiver's limiter, "0" cross detector, timer counter, and result comparator (inside the microcomputer). 1.) A modem receiver characterized in that these operations are collectively controlled by a device microcomputer.
JP56033803A 1981-03-11 1981-03-11 Modem receiver for facsimile Granted JPS57148451A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56033803A JPS57148451A (en) 1981-03-11 1981-03-11 Modem receiver for facsimile

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56033803A JPS57148451A (en) 1981-03-11 1981-03-11 Modem receiver for facsimile

Publications (2)

Publication Number Publication Date
JPS57148451A JPS57148451A (en) 1982-09-13
JPS6333827B2 true JPS6333827B2 (en) 1988-07-07

Family

ID=12396630

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56033803A Granted JPS57148451A (en) 1981-03-11 1981-03-11 Modem receiver for facsimile

Country Status (1)

Country Link
JP (1) JPS57148451A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63187842A (en) * 1987-01-30 1988-08-03 Hitachi Ltd Vlsi for modem
JPS6454842A (en) * 1987-08-26 1989-03-02 Hitachi Ltd Device and system for modulation/demodulation

Also Published As

Publication number Publication date
JPS57148451A (en) 1982-09-13

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