JPS6333826B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a carrier regeneration circuit using inverse modulation, which regenerates a reference carrier wave from an unbalanced quadrature phase modulated wave (UQPSK wave) by inverse modulation.

Conventionally, there has been a carrier wave regeneration circuit for UQPSK waves using inverse modulation, as shown in Fig. 1. In the figure, 1 is the input terminal of the UQPSK wave, 2 is the synchronous detector on the I channel side, 3 is the synchronous detector on the Q channel side, 4 and 5 are the voltage comparators of each channel,
6 is a phase shifter to delay the phase of the UQPSK wave by 90°,
7 and 8 are two-phase phase modulators for each channel for performing inverse modulation, 9 is an attenuator, 10 is a signal combiner, 11 is a phase detector, 12 is an error voltage amplifier,
13 is a loop filter, 14 is a voltage controlled oscillator,
15 is a phase shifter for delaying the reproduction reference carrier wave by 90°;
16 is a delay line, 17 is an output terminal for a reproduced reference carrier wave, 18 is an inverse modulation section, and 19 is a phase synchronization circuit.

Next, the operation will be explained. The UQPSK wave input to the input terminal 1 is synchronously detected by the reference carrier wave from the voltage controlled oscillator 14 and phase shifter 15 in the synchronous detectors 2 and 3. Each synchronously detected channel signal is sent to the next voltage comparator 4,
At 5, it is determined whether it is a “1” level or a “0” level,
guided to an inverse modulation section 18 consisting of a phase shifter 6, two-phase phase modulators 7 and 8, an attenuator 9, and a signal synthesis section 10;
Inversely modulates the input UQPSK wave. Inverse modulation here means that the input UQPSK wave is given the same unbalance as the UQPSK modulator by the attenuator 9.
This is to remove the modulation component of the input UQPSK wave by performing modulation that is inverse to the phase shift of the UQPSK wave.
The carrier wave component obtained as a result is then guided to a phase synchronization circuit 19 made up of circuit elements 11 to 14, noise is removed, and a reproduced reference carrier wave can be obtained at the output terminal 17.

Next, a more detailed explanation will be given using mathematical formulas and waveform diagrams. Set the input UQPSK wave as shown in the following equation.

s(t)=i(t)V _i sin(ω ₀ t+θ) +q(t)V _q cos(ω ₀ t+θ) (1) In the above equation, ω ₀ is the angular frequency of the carrier wave, i(t), q
(t) is the data series of 1 channel and Q channel, respectively, and each takes a value of ±1,
Assume that i(t) is faster than q(t). Therefore, in order to obtain the same error rate on the receiving side, the voltage amplitudes V _i and V _q of both channels are set such that V _i >V _q . now,
It is assumed that the output of the voltage controlled oscillator 14 is Vr sin (ω ₀ t+θ'), and that the voltage comparators 4 and 5 output +1 when the input is a positive voltage, and output -1 when the input is a negative voltage.
It is also assumed that the attenuation ratio of the attenuator 9 inserted into the Q channel is equal to V _q /V _i . At this time, input UQPSK
The relationship between the difference φ = θ - θ' between the carrier wave phase θ of the wave and the phase θ' of the reproduction reference carrier wave and the output voltage of the phase detector 11 is as follows: i(t) = 1, q(t) = 1 (or i(t)=
-1, q(t)=-1), it becomes as shown in Figure 2, and i
(t)=1, q(t)=-1 (or i(t)=-1,
When q(t)=1), it becomes as shown in Fig. 3. Now, suppose that the response speed of the loop filter 13 in the phase locked circuit 19 of FIG. 1 is sufficiently slow compared to the modulation speed, and that the input modulated wave takes the four possible phase states at the same rate. The average error voltage characteristic for the UQPSK modulated wave is the average of FIGS. 2 and 3, as shown in FIG. 4. As is clear from FIG. 4, the phase locked circuit 19 has four stable points φ=
o, π/2, π, and 3/2π. However, the stable points of φ = π/2 and 3/2π are the result of averaging the error voltage characteristics in Figure 2 and the error voltage characteristics in Figure 3, and therefore the phase of the recovered carrier wave relative to the modulation The jitter becomes larger than the stable point of φ=o and π.

In the conventional UQPSK reference carrier regeneration circuit using inverse modulation, as described above, when the phase synchronization circuit synchronizes with the phase of φ = π/2, 3/2π, the phase jitter of the regenerated carrier wave increases, and in this case, , there was a drawback that the demodulated data of the I channel and the Q channel were interchanged with each other.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and utilizes the fact that the power of the output after synchronous detection is different between the I channel and the Q channel. By detecting the swapping of the oscillators and, if they have been swapped, applying an error voltage to the input of the voltage controlled oscillator to unlock the phase locking circuit, φ=o,
It is an object of the present invention to provide a UQPSK wave carrier regeneration circuit that performs inverse modulation that synchronizes only with the phase of π, has little phase jitter, and does not interchange demodulated data of I and Q channels.

FIG. 5 shows an embodiment of the present invention. The same symbols as in FIG. 1 indicate the same things as in FIG. 1, 101,
102 is a squaring circuit that squares the outputs of the synchronous detectors 2 and 3, respectively; 103 and 104 are squaring circuits 10;
105 is a subtracter that subtracts the output of the low-pass filter 104 from the output of the low-pass filter 103; 106 is a voltage comparator that compares the output of the subtracter 105 with a predetermined voltage; 107 is a Loop filter 13
This is an adder that adds the output of the voltage comparator 106 and the output of the voltage comparator 106, and adds the result to the voltage controlled oscillator 14. 108 and 109 are the circuits 101 and 10, respectively.
3 or 102 and 104, and constitutes an I and Q channel side power detection circuit that detects the output power of the I and Q channel side synchronous detectors 2 and 3,
Further, 110 consists of the above circuits 105 and 106,
It constitutes a comparison circuit that compares the outputs of both power detection circuits 108 and 109, and further includes the adder 10.
Reference numeral 7 functions as a lock tripping circuit that unlocks the phase locked circuit 19 when the output power of the Q channel side synchronous detector 3 is larger.

Now, the outputs of the synchronous detector 2 on the I channel side and the synchronous detector 3 on the Q channel side are respectively expressed by the following equations.

I(t)=i(t)V _i cosφ−q(t)V _q sinφ (2) Q(t)=i(t)V _i sinφ+q(t)V _q cosφ (3) Therefore, square circuit I ² by 101,102
(t), Q(t) ² and low pass filter 103,
When only the DC component is extracted using 104, its output has the I channel and Q channel, respectively, I ² (t) _DC = V _i ² cos ² φ+V _q ² sin ² φ (4) Q ² (t) _DC = V _i ² sin ² φ+V _q ² cos ² φ (5) is obtained. Next, the subtracter 105 calculates I ² (t) _DC
−Q ² (t) When _DC is created, the output of the subtracter 105 is e(t)=(V ² _i −V ² _q ) cos ² φ (6). Due to the unbalanced nature of the I and Q channels, V _i > V _q , so e(t) is φ=o, π
The maximum positive value occurs when φ=π/2, and the maximum negative value occurs when φ=π/2 and 3/2π. Therefore, if the voltage comparator 106 detects whether the output e(t) of the subtracter 105 is positive or negative, it is determined whether the phase locked circuit 19 is locked at φ=π/2, 3/2π, or when φ=o, π. It is possible to determine whether the device is locked or not. When locked at φ=π/2, 3/2π, the adder 107 adds the error voltage to the input of the voltage controlled oscillator 14, allowing the phase locked circuit 19 to be unlocked.

In the above embodiment, the square circuit 101,
102, but an envelope detector may be used instead.

Further, the circuit of the above embodiment can be used as a FALSE LOCK detection circuit since e(t) takes the maximum positive value when the phase locked circuit locks at φ=o, π.

As described above, according to the present invention, it is possible to detect the exchange of demodulated data of the I channel and the Q channel by using the difference in output power after synchronous detection of the I channel and the Q channel. The synchronous circuit output now locks only to the phase of φ=o, π, so there is always less phase jitter.
In addition, there is an effect that a reproduction reference carrier wave in which the demodulated data of both I and Q channels is not interchanged can be obtained.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a conventional circuit for reproducing a reference carrier wave from a UQPSK wave by inverse modulation, and Figure 2 is a circuit diagram of a conventional circuit for reproducing a reference carrier wave from a UQPSK wave by inverse modulation.
=-1, q(t)=-1, FIG. 3 shows that the modulation data is i(t)=1, q(t)=-1 or i(t)=-
Fig. 4 is a detection characteristic diagram of each phase-locked circuit when q(t) = 1, Fig. 4 is a detection characteristic diagram of the phase-locked circuit during modulation, and Fig. 5 is a detection characteristic diagram of the phase-locked circuit when modulated. FIG. 2 is a circuit diagram of a carrier wave regeneration circuit. 1...UQPSK wave input terminal, 18...Inverse modulation section, 19...Phase synchronization circuit, 108, 109...
I, Q channel side power detection circuit, 110... Comparison circuit, 107... Lock tripping circuit (adder).
Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1 An inverse modulation unit equipped with an attenuator on the Q channel side that inversely modulates an unbalanced four-phase modulated wave that has the same unbalanced property as that on the transmitting side, and the output of this inverse modulation unit is phase-synchronized with the above modulated wave. A carrier regeneration circuit using inverse modulation, which includes a phase synchronization circuit that regenerates a reference carrier wave, an I channel power detection circuit that detects the output power of the I channel side synchronous detector, and an output of the Q channel side synchronous detector. A Q channel side power detection circuit that detects the power, a comparison circuit that compares the magnitude of the output of the above two power detection circuits, and as a result of the comparison by this comparison circuit, the output power of the above Q channel side synchronous detector is larger. 1. A carrier wave regeneration circuit using inverse modulation, comprising: a lock tripping circuit for unlocking the phase synchronization circuit.