JPS6333814B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device that time-division multiplex transmits multiple pieces of data, and in the event that the transmission section becomes unable to communicate due to disconnection, etc., the reception clock pulse is regenerated by a data protection circuit provided in the reception section. After detecting that the wire is not being disconnected, the hold pulse is stopped and the state immediately before the disconnection is maintained semi-permanently.Even if the transmitting section is restored, the state immediately before the disconnection is maintained until the receiving section establishes synchronization. To provide a device that prevents a receiving section from operating abnormally in a communication-disabled state by keeping it in a stopped state or by keeping it in a stopped state and quickly returning it to normal operation after synchronization is established. With the goal.

When multiplexing multiple data, a method is used in which each data is asynchronously sampled and then time-division multiplexed using a parallel/serial converter.
The block is shown in FIG. 1 and will be explained.

In Fig. 1, A is a transmitter, B is a transmitter, and C is a transmitter.
is the receiving section. The transmitter A transmits a plurality of data D ₁
A parallel/serial converter 2 that inputs ~Dn and performs time division multiplexing, and an internal oscillation circuit that generates a clock pulse a.
A transmission timing generator 1 generates a sampling pulse b and a frame pulse c. The transmission section B is composed of a coaxial cable or an optical fiber cable, but if an optical fiber cable is used, an electrical signal/optical signal converter (E/O) is installed at the output end of the transmission section A, and an electrical signal/optical signal converter (E/O) is installed at the output end of the transmission section A. An optical signal/electrical signal converter (O/E) is required at the input end. Receiving section C
For example, a PLL (Phase Locked Loop) inputs the transmission data d and extracts the received clock pulse f.
A clock extraction circuit 4 consisting of a
After sampling, the first output (Q ₁ ) and the (n+1)th output (Q _o+1 ) of the serial/parallel converter 5, which are sequentially shifted, and the received clock pulse f are inputted, and a frame pulse g is detected. After establishing synchronization, the reception timing generator 6 generates a hold pulse g′ and the output of the serial/parallel converter 5 (Q ₂ ~
Q _o+1 ) and hold pulse g′ are input, and at the timing of the rise of hold pulse g′, the series
It consists of a hold circuit 8 which holds the outputs (Q ₂ -Q _o+1 ) of the parallel converter 5 and outputs data D ₁ ' - Dn' and a frame pulse C'.

Next, the operation will be described assuming that seven pieces of data Di are input. Parallel/serial converter 2 has a second
When data D-1 to D-7 in the figure are input, they are asynchronously sampled by sampling pulse b. When the x point is expanded on the time axis, it becomes as shown in Fig. 3. At the rising timing of sampling pulse b, frame pulse c, data D-1 to D
-7 state is maintained, read out sequentially at the timing of clock pulses, converted into a serial signal, and sent to the receiving section C via the transmitting section B as transmission data d. In the receiving section C, the transmission data d is input to the clock extraction circuit 4, which reproduces the receiving clock pulse f shown in FIG. Also, transmission data d
are input to the serial-to-parallel converter 5, sampled by the received clock pulse, and sequentially shifted to obtain outputs _Q1 to _Q9 . The reception timing generator 6 inputs the outputs Q ₁ and Q ₉ of the serial/parallel converter 5 and the reception clock pulse f and generates a hold pulse.
Make g′. Serial/parallel converter 5 in hold circuit 8
When inputting the outputs Q ₂ to Q ₉ and the hold pulse g′,
Q ₂ to _{Q 9} are held at the rising timing of hold pulse g', and frame pulse f' and data D-1' to D-7' are reproduced.

Now, if the transmission section B is disconnected, the transmission data e becomes logic O from point _y1 onwards, as shown in Fig. 5.
Q ₂ to _{Q 8} are sampled at the rising timing of the final (y ₂ points) hold pulse g', and the output data Di (D ₁ to _{D 7} ) becomes logic O. Therefore, although the transmitting section A continues to send the transmission data e, the data Di of the receiving section C shows different contents. For example, when used for the purpose of controlling a power mechanism, there is a problem that such abnormal operation may cause damage to equipment or endanger human life.

Therefore, an object of the present invention is to provide a data transmission device that can eliminate such conventional disadvantages.

An embodiment thereof will be described below with reference to the drawings.

As shown in FIG. 6, a transmission timing generator 1 has an oscillation circuit inside and generates a clock pulse a, a sampling pulse b, and a frame pulse c;
Frame pulse c and multiple data D-1 to D to n
A parallel/serial converter 2 inputs the data D-1 to D-7 by time division multiplexing using a sampling pulse b and a clock pulse a to generate a serial signal d, and inputs a serial signal d and a clock pulse a to generate a serial signal d. Transmission section A consisting of a pulse width modulation circuit 3 that modulates a period in which is logic 1 or logic 0 into a predetermined pulse code as transmission data e; transmission section B consisting of a coaxial cable or optical fiber cable; A clock extraction circuit 4 is connected to the transmitter A through a clock extracting circuit 4, which inputs transmission data e, detects the rising edge of the clock, and extracts the reception clock f; After sampling _the transmission data _e at the timing of , hold pulse after establishing synchronization
A reception timing generator 6 that generates a clock pulse f and a hold pulse g' is inputted to a reception timing generator 6 that generates a reception clock pulse f and a hold pulse g', and determines whether or not the reception clock pulse f is continuous at a predetermined interval, and outputs or stops a hold pulse h. The data protection circuit 7, the outputs Q ₂ to Q _o+1 of the serial/parallel converter 5, and the hold pulse h are input, and the inputs Q ₂ to _{Q o+1} are held at the timing of the rise of the hold pulse h to create a frame. It is constituted by a receiving section C consisting of a hold circuit 8 which reproduces timing pulse c' and data D-1' to D-7'.

The operation will be described below assuming that seven pieces of data Di are input.

In this device, the pulse width modulation circuit 3 can be constructed from the circuit shown in FIG. In FIG. 7, when a clock pulse a is input to the frequency divider 31, the outputs a-1 and a-2 shown in FIG. 8 are obtained. When a-1 and a-2 are input to the logical sum element 33 and the logical product element 34, respectively, a-3 is obtained as the output of the logical sum element 33, and a-4 is obtained as the output of the logical product element 34. a-3 has a logic 1 in the period 3・T ₁ ,
1・T The period of ₁ is logic 0. Further, a-4 is assumed to be logic 1 during the period 1·T ₁ and logic 0 during the period 3·T ₁ . The serial signals d and a-3 are connected to the AND element 34
When the serial signal is input to a
The output of -3 is obtained and becomes e-1. Furthermore, when the serial signal d is input to the negation element 32, the inverted signal d
-1 is obtained, and when the inverted signals d-1 and a-4 are input to the AND element 34, a-4 is obtained at its output while the serial signal d is at logic 0. Next, a-3
and a-4 are input to the OR element 33, transmission data e is obtained in which a-3 is input during the period when the serial signal d is logic 1, and a-4 is input during the period when the serial signal d is logic 0.
is obtained. Transmission data e is connected to the receiving section C via a coaxial cable or an optical fiber cable. In the receiving section C, the transmission data e is input to the clock extraction circuit 4. Clock extraction circuit 4
can be constructed from a monostable multivibrator as shown in FIG. When the transmission data e is input to the monostable multivibrator in FIG. 9, the change point of the rising edge of the transmission data e is detected as shown in FIG.
Since it operates only for the period _T1 , the reception clock pulse f can be obtained. When the transmission data e and the reception clock pulse f are input to the serial/parallel converter 5, the reception clock pulse f is input as shown in FIG.
The transmission data e is sampled at the rising edge of , and then sequentially shifted to obtain outputs Q ₁ to _{Q 9} .
When the outputs Q ₁ to Q ₉ and the reception clock pulse f are input to the reception timing generator 6, a hold pulse g' is obtained. Next, the hold pulse g' and the reception clock pulse f are input to the data protection circuit 7. The data protection circuit 7 can be constituted by a circuit as shown in FIG. When a receiving clock pulse f is input to the monostable multivibrator 71, it operates for a period of _6.T1 after detecting the rising edge of the receiving clock f, but is retriggered when the next rising edge is input during operation. Operate. Therefore, when the receive clock pulses f are continuous, the output f-1 is always in the logic 1 state. As shown in FIG. 13, when the transmission data e is no longer input to the reception section C at _y1 due to a disconnection in the transmission section, the reception clock pulse f is also no longer obtained. Monostable multivibrator 71
Since the operating period of 6.T1 is set, ₆ .
After T ₁ , it becomes logic 0. When f-1 is input to monostable multivibrator 72, f-1
After detecting the rising edge of the reset pulse f-2
output f-5 to reset flip-flop 75, so that its output f-5 becomes logic 0. The output f-5 of the flip-flop 75 is connected to the AND element 7.
6, its output h becomes logic 0 regardless of the hold pulse g'. Next, we will discuss what happens when the disconnection is restored. As shown in FIG. 14, when the receiving clock pulse f is restored (at time _y3 ), the transmission data e is input to the receiving section C, so that the receiving clock pulse f can be obtained continuously, and the monostable multivibrator 71 The output f-1 of changes from logic 0 to logic 1. When the output f-1 is input to the monostable multivibrator 73, it operates after detecting the rising edge of f-1.
3 is obtained.

Assuming that the period of the hold pulse g' is T ₂ (=32·T ₁ ), it takes approximately 8·8·1 to establish the synchronization of the receiver C after transmitter B is restored to normal state and transmission data e is input. Since T ₂ is required, the operating time of the monostable multivibrator 73 is set to 10·T ₂ . When f-3 is input to the monostable multivibrator 74, after detecting the fall of f-3, it outputs a set pulse f-4 to set the flip-flop 76, so its output f-5 becomes logic 1. Become. Therefore, AND element 7
A hold pulse h is obtained at the output of 6. When the outputs Q ₂ to _{Q 9} of the serial/parallel converter 5 and the hold pulse h are input to the hold circuit 8, Q ₂ to _{Q 9} are held at the timing of the rise of the hold pulse h, so the frame pulse c shown in FIG. 11 is generated. ' and data D-1' to D-7' are obtained. Further, when the hold circuit 8 is reset by the reset pulse f-2, the data D-1' to D-7' can be forcibly set to logic 0.

As described above, according to the present invention, by pulse width modulating the parallel-to-serial converted serial signal in the transmitting section, clock information is imparted to the serial signal,
In addition to making it easier to synchronize the bits of the receiving section, the data protection circuit makes it possible to immediately detect no signal in the serial signal due to disconnection in the transmission section, etc., and regenerates the receiving section when there is no serial signal. The data is held in the state immediately before the disconnection or in a stopped state, and after the transmission section is restored, synchronization is completely established and the normal operation is returned to the receiving section. This makes it possible to alleviate abnormal operation of equipment.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional data transmission device.
2, 3, 4, and 5 are time charts for explaining the operation of the device shown in FIG. 1, and FIG. 6 is a block diagram of a data transmission device according to an embodiment of the present invention. Figure 7 is a circuit diagram of the pulse width modulation circuit in the same device, Figure 8 is a time chart for explaining the operation of the circuit, Figure 9 is a circuit diagram of the clock extraction circuit in the same circuit, and Figure 10 is the circuit diagram of the same circuit. FIG. 11 is a time chart for explaining the operation of the device. FIG. 12 is a circuit diagram of the data protection circuit in the device.
14 are time charts for explaining the operation of the circuit. 1... Transmission timing generator, 2... Parallel/serial converter, 3... Pulse width modulation circuit, 4... Clock extraction circuit, 5... Serial/parallel converter circuit, 6...
...Transmission timing generator, 7...Data protection circuit, 8...Hold circuit.

Claims (1)

[Claims] 1 A transmission timing generator that has an internal oscillation circuit and generates clock pulses, sampling pulses, and frame pulses, and inputs the frame pulse and n pieces of data, and time-division multiplexes the frame pulse and n pieces of data using the sampling pulse and clock pulse. a parallel/serial converter that converts the signal into a serial signal;
A transmitter consists of a pulse width modulation circuit that inputs a serial signal and a clock pulse and modulates the logic 1 and 0 periods of the serial signal into a predetermined pulse code as transmission data; A clock regenerator connected to the modulation circuit detects the changing point of the rising edge of the transmitted data and regenerates the received clock pulse; n
+1) A reception unit that inputs a bit-shifting serial/parallel converter, the first and (n+1)th output signals of the serial/parallel converter, and a clock pulse, detects a frame pulse, establishes synchronization, and generates a hold pulse. A timing generator and a data protection circuit that inputs receive clock pulses and hold pulses, detects that the receive clock pulses are continuous at a predetermined interval, and outputs a hold pulse when the receive clock pulses are continuous at a predetermined interval. and,
Consists of a receiving section consisting of a hold circuit that inputs the output signal of the serial/parallel converter and a hold pulse, holds the output signal of the serial/parallel converter at the rising timing of the hold pulse, and reproduces the data. A data transmission device characterized by: