JPS633338B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a pipeline processor that includes:
The present invention relates to an instruction processing device for interrupting an instruction when an event that forces the interruption occurs and repeating the instruction after the event is resolved.

[Prior Art] In a data processing system, during instruction processing,
Performance of such instruction processing may be interrupted due to the occurrence of certain conditions. Certain situations (hereinafter referred to as events) force a brief interrupt to complete the operation caused by the event before continuing interrupted instruction processing.

For example, such an event occurs in data processing systems in which a cache is provided as a buffer between main memory and a processing unit. The directory constantly remembers the addresses of data in the cache. Each time the processor accesses the cache, the directory is queried to see if the desired data is stored in the cache. This checks to see if the cache can provide data to the processor in preparation for execution of the instruction. If an address with the desired data is not found in the directory, the data must be stored from main memory to the cache. A new registration is then made in the directory. Only then can instruction processing be resumed by repeating the previous instruction.

However, such instruction repetition is only possible if the contents of the operation register are saved. The contents of the operation register here refer to the instruction, in particular the operation code and operand address (as well as any additional information that the instruction may contain, if necessary).
It is. Well-known data processing systems use backup registers for this purpose, the number of which depends on the degree of parallel instruction processing. This allows returning to the instruction to be repeated.

[Problems to be Solved by the Invention] Although such additional components are not desirable in themselves, another problem is that the entire instruction cycle consisting of one or several clocks must be repeated. , a considerable amount of time is lost.

It is therefore an object of the present invention to handle a particular event that forces an interrupt without the need for extra backup registers and to minimize the time required to repeat the interrupted instruction. The object of the present invention is to provide an instruction processing device with a high level of accuracy.

[Means for Solving the Problems] In a pipelined processor, the instruction processing device of the present invention suspends an instruction when an event that forces suspension of an instruction occurs and repeats the instruction after the event is resolved. a) memorize each normal command;
(b) a first register group consisting of a plurality of serially connected registers that stores the instruction stored at that time as is when an event that forces an instruction to be interrupted occurs; and (b) this first register. a plurality of decoding means provided corresponding to each register constituting the group and decoding instructions stored in each of these registers when an event that forces an interruption does not occur;
(c) a second generating control information for processing the event;
and (d) when an event occurs, the control information generated by the second register group is transferred to the plurality of decoding means instead of the instruction stored in the first register group, and the event resolution is completed. and means for sequentially switching the destination of the output of one register of the first register group storing the instruction at the time of occurrence of the event to one of the plurality of decoding means. There is.

By switching to the decoding means as described above, an extra backup register becomes unnecessary, and the time required to repeat the interrupted instruction can be shortened.

[Embodiment] As shown in FIG. 4, parallel instruction processing is assumed. The first and second rows from the top of FIG. 4 respectively represent the timing of the A clock (A-CL) and the B clock (B-CL) related to the instruction clock, that is, the instruction cycle. To T0 in the 3rd row
T5 represents an instruction cycle. These A and B clocks are primarily used to operate the master/slave flip-flop (FIG. 2), which is the main component of the processor logic.

The instruction set of most data processing systems includes instructions of varying lengths, ie, instructions that require one to several instruction cycles to process.
Processing of instructions is typically performed in two alternating stages. That is, the instruction stage and the execution stage. For instructions that can be executed interpretively rather than directly, the instruction phase, within three instruction cycles, involves fetching the instruction from main memory or buffer, fetching the controlling microinstruction from control storage, and is decrypted. This decoding begins the actual execution phase of the instruction. The execution phase is accomplished within four instruction cycles. That is, the first operand read, the second operand read, and the associated ALU
transfer of both operands to the input registers of the (arithmetic logic unit), actual arithmetic or logical processing of the operands, and storage of the result in a defined storage location;
It is.

In a pipeline processor, ie, a processor with parallel instruction processing, several instructions are partially processed per instruction cycle Ti depending on the degree of parallelism. With two operation registers 4 and 5 as shown in FIG. 3, after a certain initial run, partial processing of three different sequential instructions is possible per instruction cycle Ti. When the first instruction cycle T0 begins, the instruction having the instruction address (eg, A) in the instruction address register 2 (FIG. 1) is read from the instruction store. In the next instruction cycle T1, both operands are fetched and at the same time the next instruction with instruction address B is fetched from the instruction store.

In the third instruction cycle T2, the operand is ALU
arithmetically or logically combine and store the result in a predetermined register (or memory location). Additionally, the next operand pair is retrieved and at the same time the next instruction (third instruction) is selected from the instruction store.

If the branch instruction is successful, the pipeline configured in this way is interrupted and a new pipeline is established. Again, there is an initial run of two instruction cycles that fills the three-way parallel processing pipeline.

These two operation registers support parallel instruction processing, with operation register 4 selecting the source and operation register 5 selecting the target. The term “source”
refers to an operand or other data (eg, at an address) to be processed, and a "target" refers to a data processing element that produces a result and determines where to forward it.

The processor data flow shown in FIG. 3 represents the instruction store 1 continuously transferring instructions to the operation register 4. The processor data flow shown in FIG. Operation register 4 transfers its own instructions to operation register 5 in the subsequent instruction cycle. This is to enable the instruction to be loaded again from instruction storage 1 in the next instruction cycle. The outputs of operation registers 4 and 5 are connected to operation decoding section 6 and operation decoding section 7, respectively.

The instruction residing in the operation register 4 selects the source, ie, the register residing in the data local storage (DLS) 36, via the operation decoder 6. The instruction in the operation register 5 selects a target via the operation decoder 7. In the example in Figure 3, this target is the ALU
39 input registers 37 and input registers 38. Once the instruction reaches the operation register, the operands are retrieved from data local storage 36. For this purpose, for example, the contents of two general purpose registers or the contents of one base register and a displacement are read into the input registers 37, 38 of the ALU 39. The displacement contents are transferred directly from the command store 1 via its own connection line 40.

On the next instruction cycle, operation register 4 transfers its contents to operation register 5. Operation register 5 is not only a result register but also a target (for example, ALU39 function).
Also select. Meanwhile, at the same time, the operation register 4 receives the next instruction and selects the next source.

Parallel processing is performed using the data local storage unit 36 of the processor.
and also occurs in ALU39. Data local storage unit 3
6 outputs the next operand while the ALU 39 generates a result using the current operand. This parallel processing is the basic principle of pipelined computers, and is made possible primarily by triple control of the data local storage 36.
For instructions that use storage operands, connection line 4
0 directly supports base register and displacement calculations, which are also performed in parallel with other processing.

As shown in FIG. 1, operation registers 4 and 5 contain their associated instruction cycle counter (CC1) 8 and instruction cycle counter (CC2) 9 for specific control operations.
have each. Operation register 4
initiates the source selection control in conjunction with the instruction cycle counter 8 which provides clock pulses 1Ti. On the other hand, the operation register 5 has an instruction cycle counter 9 which supplies the clock pulse 2Ti.
Manage target change control in collaboration with

As can be seen from Figure 4, the first instruction cycle
At T0, the instruction with address A present in the instruction address register (IAR) 2 is fetched and stored in the operation register 4 in the second instruction cycle T1. The second instruction cycle, however, is the first instruction cycle 1TO from the point of view of the instruction cycle counter 8. By the way, address A
Since the instruction is a two-cycle instruction, the instruction cycle counter 8 associated with the operation register 4 also needs to generate a clock pulse 1TL.

Considering the time shift, the above control can also be applied to the operation register 5. The instruction cycle counter 9 also receives two clock pulses, viz.
Generates 2TO and 2TL.

Having described the mechanical design above, the present invention will now be described.

During instruction cycle A2TL, an event may occur, such as a desired operand not being found in the cache. The problem here is not to repeat the entire instruction with address A after the event is resolved, i.e. when the cache is again able to supply the required operands, but only the previous instruction cycles A1TL and A2TL. That's true. Therefore, this repetition takes only a fraction of the time compared to repeating the entire instruction, i.e., every instruction cycle, and address A is not required during the repetition, so there is no backup for either the instruction address or the operands. No registers are required.

Repeating instruction cycles A1TL and A2TL without adding backup registers is achieved by the corresponding event signal immediately holding (freezing) the contents of instruction address register 2 and operation registers 4 and 5. be done. This event signal is generated by the above-mentioned event (the first
In the figure, this event is denoted as CM). The contents held (frozen) in these registers do not change until instruction cycle A1TL is repeated.

When the desired operand is loaded into cache from main memory and available for instruction execution, that is, after the event is resolved, operation register 5 and instruction cycle counter 9 are It is further necessary to switch to the output of the instruction cycle counter 8 associated therewith.

Since the two operation registers are turned off while resolving an event, the outputs of these operation registers do not generate control signals. Furthermore, since all event functions are switched to their outputs instead of the contents of the operation registers, an optimal distribution of individual decoding functions can be achieved and the overall amount of connection points can be reduced. .

The circuit configuration (FIG. 1) and its operation (FIG. 5) of this embodiment will be explained next.

Instruction address A exists in instruction address register 2 in instruction cycle T0. In the next instruction cycle T1, the instruction is read from the instruction memory 1 into the operation register 4, and at the same time,
The next instruction address B is read into the instruction address register 2. Furthermore, the instruction currently in the operation register 4 (this instruction is a two-cycle instruction), in combination with the instruction cycle counter 8 associated with the operation register 4, can be used as a valid operation in the general write mode A1TO.
Can be used as EFOP1. In the operation decoding section 6, this effective operation
EFOP1 is decoded and a data flow control signal (DF) is generated. This data flow control signal controls the instruction phase of the instruction. Since no event has occurred requiring the execution of the forced operation involving repetition of the instruction in each cycle and gates 17 and 18 are activated, the instruction is transferred from operation register 4 to the operation decoder. Move to 6. Therefore the event signal CM, x _o-1 for requesting a forced operation (FO)
or x _o does not exist, so multi-conductor lines 41, 42, and 43 carry a signal corresponding to the binary value 0. The number of multiple wires in line 41 corresponds to the number of different possible event signals. Each event signal is further sent to flip-flops (FF1) 24-26 and simultaneously to flip-flops (FF2) 28-30. Since line 42 carries not only the output of instruction cycle counter 27 but also the output of flip-flops (FF1) 24-26,
The number of multiple wires in line 42 depends on the number of event signals. In the preferred embodiment, line 43 has the same number of wires as line 42, since not only the output of command cycle counter (CC3) 27 but also flip-flops (FF2) 28-30 are supplied via line 43.

Each signal stored in parallel in flip-flops 24-26, after combining with additional mode bits if necessary, forms the data flow control word FOP1 for forced operation. Similarly, flip-flops 28 to 3
The data stored in parallel with 0 is further combined with the mode bit to form the control word FOP2 for the forced operation. These control words, which are transferred to the corresponding operation decoders 6, 7, cooperate with the instruction cycle counter 27 to control the execution of the forced operation.

The wires of lines 41 to 43 are ORed for control.
They are combined at gates 31, 33, 34 and 35. The output of the OR gate 31 is the inverter (I)
32 (output signal B〓). The output signal of the inverter (I) 47 is indicated by A〓. The output signals A and B are sent to the inputs of AND gates 3, 12 and 13. The output signal A〓 is further
Controls AND gate 49.

AND gates 3, 12, and 13 are further
It has two inputs. Its one input receives the set signal S, and the other input receives the A clock A-
Receive CL.

The AND gate 3 controls the instruction address register 2 via its output so that a new instruction address can be loaded into the instruction address register 2 in the next instruction cycle. However, if the match condition of AND gate 3 is not met, such loading is not performed.

For standard operation, after a read is performed at address A in the first instruction cycle (e.g.,
T0), the instruction reaches the operation register 4 by means of the activated AND gate 12 in the second instruction cycle T1. Then, the output of operation register 4 is sent to gates 17 and 18.
It reaches the operation decoding unit 6 as the effective operation EOP1. Since there are no event signals (CM,..., x _o-1 , and x _o ),
The outputs of OR gates 31, 33, 34, and 35 produce signals corresponding to a binary zero value. The output signal of OR gate 34 is applied to the input of inverter 14 where it is inverted to a signal corresponding to a binary value of one. This inverted signal is applied to the control input 44 of gate 17 to switch gate 17. Similarly, the output of OR gate 33 is applied to inverter 15 and its inverted signal is applied via control input 45 to gate 18 to switch it.

As shown in instruction cycle T1 in FIG. 5, the instruction having address A located in operation register 4 is associated with instruction cycle 1T0 of instruction counter 8. The instruction cycle T0 of the instruction counter 8 is indicated as 1T0 in FIG.

In the following instruction cycle T2, the instruction reaches the operation register 5. This instruction relates to instruction cycle T0 of instruction cycle counter 9. Instruction cycle T0 of instruction cycle counter 9
is written as 2T0 in Figure 5.

The operation decoding unit 6 further includes circuit means, which output signals 1T, 2T, . . . , (n
+1) Generate T. These output signals indicate the cycle length of each decoded instruction. The output signal 1T has a length of 1 instruction cycle T.
This means that there are two instructions. Similarly, depending on the length of the instruction cycle, 2T, ..., (n
+1) Marked as T.

As shown in FIG. 5, the instruction at address A is 2
It has a length as long as an instruction cycle, and its last cycle TL corresponds to the second instruction cycle T1 of the decoder 10. A circuit consisting of a decoder 10, AND gates 20, 21, 22, and an OR gate 23 generates a signal TL. Signal TL corresponds to the last instruction cycle of an instruction and is independent of the length of that instruction. As shown in Figure 1,
This control signal TL cooperates with AND gate 3 to manage a new instruction address in instruction address register 2, and further cooperates with AND gate 12 to manage a new instruction in operation registers 4 and 5.

Further, as shown in FIG. 5, instruction cycle T3
An event (denoted as CM in the figure) has occurred. This event (CM) means that the operands required to execute the instruction are not in the cache. Access to the cache exists (control signal CA) and the cache directory is explored (signal CDA)
If it is not successful, this event is detected.

Until this event occurs in instruction cycle T3,
Since the pipeline is established gradually, no new instruction address can be loaded into the instruction address register 2 during each instruction cycle. Therefore,
Only the address C of the third instruction exists in the instruction address register 2. When an event (CM) occurs, the operation register 4 has the instruction at address B, and the associated instruction cycle counter 8 indicates the cycle time 1T0 or 1TL, respectively. This is because this instruction is a one-cycle instruction. Operation register 5 has an instruction at address A, and instruction cycle counter 9 has a value of 2TL.
is set to .

Since instruction cycle counters 8 and 9 are connected with a difference of one instruction cycle time, instruction cycle counter 9 indicates a cycle time that is one smaller. This is done as follows.
Before the instruction cycle counter 8 receives a value incremented by 1 from the current valid value via the incrementer 11, or when the output of the instruction cycle counter 8 indicates an instruction cycle TL, the initial value is "0". ”, instruction cycle counter 8
The output of is loaded into the instruction cycle counter 9.
FIG. 5 also shows that instruction cycle counter 8 is always ahead of instruction cycle counter 9 by one step.

Due to the effect of the pipeline, the occurrence of an event (CM) causes a specific situation - the source selection data in the operation register 4 is rewritten by new data already present at the time of event detection. Such a situation requires two actions. One is the execution of a forced operation, in the above example, reloading from main memory into the cache the data that constituted the operands that were not present in the cache in the previous cycle.

The other is the repetition of the instruction and execution stages. The instruction phase (A1TL) overlaps with the instruction execution cycle prior to the operation being forced and activated to resolve the event. As previously discussed, the source and target are selected during the execution phase of this instruction.

A forced operation involving a repetition of the preceding instruction cycle TL begins at the address of the forced operation (routine) that is read into the operation register. When the event signal CM occurs, it becomes the output signal A〓 and
The instruction cycle counter 9 associated with the operation register 5 is stopped by way of an AND gate 49. That is, the instruction cycle counter 9
holds (freezes) its count value 2TL. Depending on the control information contained in the operation registers for forced operations FOP1 and EOP2, these forced operations are executed in the same manner as the operations of other microcoded instructions. Ru.

When the reload operation ends (in the example of FIG. 5, it ends at instruction cycle T _{i +2} ), even if the operation register 5 normally uses the operation decoder 7 for target selection. Also, the source selection of the interrupted instruction is repeated using the operation register 5 as a source selection means. Control input 44a of gate 17a and control input 45a of gate 18a
With the control signal (corresponding to the binary value 1) at , the contents of the operation register 5 are transferred to the operation decoder 6 as the valid operation EOP1. In this way, the source is selected.

In the following instruction cycle T _i+3 , the output of operation register 5 again indicates the valid operation.
It is sent to the operation decoding unit 7 as EOP2. The operation decoder 7 performs target selection. This is possible because in OR gates 31, 33, 34, and 35 the binary value 0
This is because the signal corresponding to is being applied again. In this manner, only the instruction execution cycle 2TL is repeated without the need for any backup registers or redundant circuits.

[Effects of the Invention] As explained above, when a specific event that forces an interruption occurs, the instruction processing device of the invention can process the event without requiring a backup register and execute the interrupted instruction. The time required for repetition can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing a basic master/slave flip-flop, and FIG. 3 is a block diagram for explaining parallel instruction processing. FIG. 4 is a diagram showing the timing of parallel instruction processing, and FIG. 5 is a diagram showing the timing of parallel instruction processing including event processing.

Claims (1)

[Scope of Claims] 1. An instruction processing device for interrupting an instruction when an event that forces the suspension of an instruction occurs in a pipelined processor, and repeating the instruction after the event is resolved, wherein each instruction is a first register group consisting of a plurality of serially connected registers that stores the instruction stored at that time and stores the instruction stored at that time as is when an event that forces suspension of the instruction occurs; a plurality of decoding means provided corresponding to each register forming the group and decoding the instructions stored in each of these registers when an event that forces an interruption does not occur; and for processing the event. a second register group that generates control information of the plurality of registers; and when the event occurs, the control information generated by the second register group is transferred to the plurality of registers instead of the instruction stored in the first register group. the output of one register of the first register group storing the instruction at the time of occurrence of the event is sequentially transferred to one of the plurality of decoding means when the event resolution is completed; An instruction processing device comprising: switching means;