JPS6333332B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a digital-to-analog conversion device that obtains an analog signal by adding signals corresponding to the weights of each digit of digital input, and in particular, the present invention relates to a digital-to-analog conversion device that obtains an analog signal by adding signals corresponding to the weights of each digit of digital input. It provides what is possible.

Analog-to-digital converters that have been widely used in the past use various resistors for purposes such as voltage division, division and addition, or amplification, and the conversion accuracy depends on the accuracy of the resistance values. It was something that depended on me.

For example, as shown in FIG. 1, a constant voltage from a voltage source 11 is commonly applied to the bases of transistors Tr ₁ to _{Tr 5} , and the emitters of transistors Tr ₁ to _{Tr 4} are respectively connected to branch resistors of a ladder resistance circuit.
It is connected to the other end of the voltage source 11 via the ladder resistance circuit. The collectors of transistors Tr ₁ to _{Tr 4} are provided to correspond to each digit of the input digital signal, and are switch switches operated by each digit signal.
It is connected to the ground side or the adder circuit 12 side through S ₁ to S ₄ . Switch S ₁ is the highest bit, Switch S ₄
are respectively controlled by the least significant bit. In this case, the resistors connected to the emitters of transistors Tr ₁ to _{Tr 5} are made equal to each other, for example, 2R, and the resistance values of the resistors connected to the other ends of these resistors are respectively set to R. .

By accurately setting the resistance values of these resistors, currents corresponding to the weights are added in the adding circuit 12. In order to accurately create the resistance values of these resistors, for example, wire-wound resistors with a small temperature coefficient have been used in the past, and it has been necessary to accurately adjust the resistance value of each resistor one by one. Since wire-wound resistors have a large shape, they are not preferable in terms of miniaturizing the entire resistor and integrating it into an integrated circuit.Thin film resistors are therefore used from the viewpoint of integrated circuits. Thin-film resistors are undesirable because they have a large temperature coefficient, and in order to adjust the resistance value correctly, a process called laser trimming is used to fuse part of the thin-film resistor with a laser so that the resistance element reaches the desired resistance value. This adjustment required special equipment and took a long time. Moreover, when such laser trimming is performed, high heat is applied to the thin film resistor element, which adds stress to the resistor element, making it difficult for the resistance value to remain stable over a long period of time and making it more likely to change over time. There were flaws.

In this way, in the converter shown in FIG. 1, each resistance element must have an accurate resistance value, and the resistance element in the adder circuit 12 must also have an accurate resistance value. Therefore, especially when converting an input digital signal with a high number of digits, the precision of the resistance value required for the higher bits becomes extremely high.
From this point of view, conventionally it has not been possible to increase the number of bits of digital input that can be converted.

Furthermore, conventionally, the magnitude of the output analog signal is also influenced by the reference voltage of the voltage source 11. This reference voltage is generally obtained by using a constant voltage of a Zener diode, but since there is considerable variation in the reference voltage itself, it is necessary to adjust the reference voltage, and a resistive element is required for the adjustment. Therefore, the resistance value of the resistor element had to be adjusted accurately. The offset of the operational amplifier in adder circuit 12 also affected the output. Accurately adjusting the resistance value of each resistive element in this way is difficult in itself, and there are limits to it, and more importantly, the resistance value must not be affected by factors such as ambient temperature. Accurate conversion needs to be done. However, in the past, it has been difficult to obtain such highly accurate and stable resistance elements, and deterioration over time is unavoidable, which has the disadvantage of deteriorating conversion accuracy.

In this way, in the conventional digital-to-analog converter shown in Figure 1, weighting is done according to the resistance circuit, so it was necessary to make the resistance value of each resistance element in the resistance circuit accurate. .
In order to be able to accurately convert a digital signal to an analog signal without doing this, that is, without being affected by the resistance value of the resistor element used, the digital signal is converted to a pulse duty ratio and its conversion output is It has been proposed to convert the current into DC to obtain an analog conversion output.

That is, as shown in FIG. 2, the clock pulses from the clock pulse generator 13 are frequency-divided by the frequency divider circuit 14, and each time a certain number of clock pulses are counted, the output is applied to a terminal t to which a signal of each digit of the input digital signal is given. The contents of ₀ to _t0 are preset to the frequency dividing circuit 15 through gates _G0 to _G0 , respectively. Frequency divider circuit 15 also counts the clock pulses of pulse generator 13. The frequency divided output of the frequency dividing circuit 14 resets the flip-flop 16, and the frequency dividing circuit 15 sets the flip-flop 16. The frequency dividing ratios of the equal frequency dividing circuits 14 and 15, that is, the maximum count values are the same.

Therefore, the output of the set side of the flip-flop 16, that is, the Q output, becomes a low level when the output of the frequency divider circuit 14 is generated. The value set in the frequency dividing circuit 15,
In other words, if the input digital signal is large, the frequency divider circuit 15
If the input digital signal is small, the output will be generated slowly, and when an output is generated from the frequency dividing circuit 15, the Q output of the flip-flop 16 will be at a high level. The Q output of flip-flop 16 controls switch 16, and when it is at a high level, switch 16 is connected to the constant voltage side of power supply 11, and when it is at a low level, it is connected to the ground side. Therefore, the output shown in FIG. 3 is generated from the switch 16, and its period T ₀ is the output period of the frequency divider circuit ₁₄ and is constant, but during the high level period, _the output shown in FIG. It is proportional to the size of the digital signal. Therefore, by smoothing the output of the switch 16 by the smoothing circuit 17, an analog converted output proportional to the input digital signal can be obtained at the output terminal 18.

According to such a digital-to-analog converter, processing is performed digitally, and there is no need to adjust the resistance value. In addition, it is not affected by changes in ambient temperature or changes over time. In other words, if the clock cycle of the clock pulse generator 13 is constant and the reference voltage _Es of the reference power supply 11 is constant, other parts will not be affected by changes in ambient temperature or changes over time. Highly stable and highly accurate digital-to-analog conversion can be performed without being affected by changes.

However, with this conventional digital-to-analog converter that converts into a pulse duty ratio, it is necessary to smooth the pulses in the smoothing circuit 17 in order to obtain the converted output, which inevitably results in a high speed with a time delay. It has been difficult to obtain a converted output that sufficiently follows changing digital signals.

The purpose of this invention is to be able to perform high-speed conversion without being affected by the resistance value of the resistor element, without having to make highly accurate adjustments to the resistor element, and in addition, to be able to perform high-speed conversion, and to prevent changes over time and ambient temperature. The object of the present invention is to provide a digital-to-analog conversion device that is not easily affected.

Another object of the present invention is to provide a digital-to-analog converter that can easily compensate for variations in reference voltage or changes over time, and can perform correct conversion. Still another object of the present invention is to be able to automatically compensate for effects based on reference voltage fluctuations, amplifier offset fluctuations, resistance value fluctuations, etc., periodically or as needed, that is, non-periodically. The object of the present invention is to provide a digital-to-analog converter that can perform stable and highly accurate conversion.

A further object of the invention is to add to existing or commercially available digital-to-analog converters, e.g. to provide conversions with a higher overall number of conversion bits than the number of conversion bits of the existing converters, and thus with higher accuracy. An object of the present invention is to provide a digital-to-analog conversion device that can perform the following operations.

According to the present invention, a plurality of code signal generation circuits are provided which smooth the switching output using a smoothing circuit by switching the reference voltage. These code signal generating circuits have different switching ratios and are selected so that their smooth DC outputs correspond to predetermined weights. That is, in each code signal generation circuit, the reference voltage is converted into a pulse signal with a predetermined duty ratio, and then converted into a DC signal. Therefore, this code signal generation circuit is free from the effects of ambient temperature and aging. In this way, a DC signal corresponding to each digit of each input digital signal is obtained, and the output of these code signal generation circuits is controlled by the output switch according to each digit signal of the input digital signal. The output of the code signal generation circuit which obtains the converted analog output by adding the extracted signals in an adder circuit may be a current output and a current addition, or a voltage output and a voltage addition. Also good.

At this time, the control circuit that controls the switch in each code signal generation circuit determines the control of the on/off switching ratio of the switch based on the set value, and the set value is changed by the setting means. Ru. In this way, for example, only one code signal generation circuit is selected and outputted, and the output at that time is indicated by an accurate voltmeter or ammeter, preferably one with digital indication, and this is determined to be the correct output of a predetermined value. Gradually change the setting value of the setting means so that In this way, for example, deviations in overall characteristics such as the current conversion circuit when outputting current in a code signal generation circuit, the offset of that current conversion circuit, and the addition circuit that adds the outputs of each code signal conversion circuit can be corrected with respect to the switch. It can be easily adjusted by changing the ratio, that is, the duty ratio. Moreover, the adjustment value does not change easily.
Similarly, by selecting one of the code signal generation circuits and adjusting the settings of the setting means for each so that its output is correctly obtained as the output of the adder circuit, a correct conversion output can be obtained as a whole. In this case, it is also possible to correct deviations in each part of the circuit.

In the present invention, such correction of each code signal generation circuit is automatically performed. For example, a reference signal generation circuit is provided corresponding to each code signal generation circuit to generate the original reference value of its output. In this reference signal generation circuit, for example, by changing the duty ratio and smoothing it, it is possible to obtain a correct reference value that is not affected by temperature fluctuations of the resistance element. In that case, the desired reference value can be obtained by changing the duty ratio according to the corresponding code signal generation circuit. The output of this one code signal generation circuit is selected and compared with the corresponding reference value by a comparator, and according to the comparison result, the selected code is adjusted so that both inputs of the comparator match. Adjust the settings of the signal generation circuit. Such control can be performed by a so-called microcomputer.

That is, depending on whether the output of the comparator is at a high level or a low level, the microcomputer increments the lower bit of the setting means of the code signal generation circuit selected by the microcomputer, that is, the register in which the set value is stored, by +1 or -1. Thereafter, the comparison operation is performed again and repeated until both inputs of the comparator match. After such adjustment is performed for each code signal generation circuit in sequence, and after all code signal generation circuits are made, a command to manually perform comparison adjustment can be generated periodically or at an appropriate time.

Furthermore, a plurality of code signal generation circuits are added to a digital-to-analog converter that obtains weights using conventional resistance circuits, and the upper number bits of the input digital signal are made to correspond to each code signal generation circuit. By feeding the bits into a digital-to-analog converter using an existing or conventional type resistor circuit and summing the outputs of each bit, a higher order analog conversion output can be obtained.

Next, prior to explaining the digital-to-analog converter according to the present invention, an improved digital-to-analog converter will be explained with reference to FIG. 4 and the subsequent drawings. In this invention, code signal generation circuits A ₀ to A _o are provided. Each code signal generation circuit _A0 to _Ao is provided with a switch 21.
Reference voltages 1 from a common reference power supply terminal 22 are outputted under switching control by the corresponding control circuits 23, respectively. The outputs of the switches 21 are converted into DC by a smoothing circuit 24, respectively. In this embodiment, each DC output is a voltage output, but is converted into a current in the voltage-current conversion circuit 25. The DC currents I ₀ to I _o are selected to have weights corresponding to each digit of the input digital signal. For example, I ₀ is proportional to 2 ⁰ , I ₁ is proportional to 2 ¹ , and I _o is proportional to 2 ⁿ .

In order to achieve such a proportional output, switch 2
1, the switching ratios are different in the code signal generation circuits A ₀ to A _o . Switch 21 is switched between constant voltage terminal 22 and ground by control circuit 23 as described above. The control circuit 23 is a setting circuit 26 provided in each code signal generation circuit.
An output with a duty ratio corresponding to the set value of is output. The low level section of the output is grounded, and the high level section is controlled to be connected to the power supply terminal 22 side. The control circuit 23 has a configuration as shown in FIG. 2, for example. In other words, the control circuit 23
It is composed of frequency dividing circuits 14, 15, and a flip-flop 16 in the figure, and the clock pulses for each frequency dividing circuit can be commonly applied to the code signal generating circuit. The setting circuit 26 is set with the signals applied to the terminals to _{to to} in FIG.

The DC signals I ₀ -I _o obtained by these code signal generation circuits A ₀ -A _o are supplied to output switches S ₀ -S _o . Corresponding digit signals of the input digital signal are applied to terminals t ₀ -t _o of these output switches S ₀ -S _o , respectively. The first digit of the input signal is applied to the terminal t ₀ , the second digit of the input signal is applied to the terminal t ₁ , and the most significant digit of the input signal is applied to the terminal t _o , and the digit signal is “1”. In this case, the corresponding switch is turned on,
The output DC signal of the code signal generation circuit connected to this is made to pass through the output switch.

The outputs of the output switches S ₀ to S _o are added by an adder circuit 27. In the adder circuit 27, the current is converted to voltage as necessary, and a converted analog output is obtained at the output terminal 28.

A specific example of the code signal generation circuit will be explained with reference to FIG. In FIG. 5, the code signal generation circuit _A0 will be particularly explained, but other code signal generation circuits can be similarly configured. As mentioned above, the control circuit 23 can use, for example, the example shown in FIG. This pulse signal is the switch 2
The reference voltage of the terminal 22 is supplied directly to the gate of the FET switch 29 of No. 1, and the FET switch 29 is turned on in a high level state, and the reference voltage of the terminal 22 is supplied to the smoothing circuit 24. However, when the output of the control circuit 23 is at a low level, the output is inverted by the inverter 31 and applied to the gate of the FET switch 32.
The output side of FET switch 29 is FET switch 32
caused to fall to the ground. Therefore, this ground potential is input to the smoothing circuit 23.

As mentioned above, in the control circuit 23, the duty ratio of the output differs depending on the code signal generation circuits A ₀ to A _o , and in this example, the period of each pulse is the same, but the code signal generation circuit A ₀ For the high level pulse width of the output of the control circuit 23,
The high-level pulse width of the output of the control circuit 23 of code signal generation circuit A ₁ is 2 ¹ times that of code signal generation circuit A ₂ , and the pulse width of the output of the control circuit of code signal generation circuit A _o is 2 ¹ times that of code signal generation circuit A 2. 2 _o times each.

For example, in FIG. 5, the smoothing circuit 24 is composed of an RC waveformer in which a plurality of RC resistor passing wave stages each consisting of a series resistor and a shunt capacitor are arranged in series. When a so-called active filter is used as the smoothing circuit 24, it is suitable for integration. In the voltage-current conversion circuit 25, an operational amplifier 33 is provided, and a smoothing circuit 2 is connected to the non-inverting input side of the operational amplifier 33.
A smoothed output voltage of 4 is supplied to the operational amplifier 3.
The output of 3 is given to the gate of FET34.
The source of the FET 34 is grounded through a resistor 35, and the drain is connected to the mover of the output switch _S0 . If the input of terminal t ₀ is “1”, switch S ₀
is connected to the adder circuit 27 side, and if it is “0”,
The drain of FET34 is grounded. The source of the FET 34 is connected to the inverting input side of the operational amplifier 33 so that both inputs of the operational amplifier 33 match.
A current flows through the FET 34, that is, a current corresponding to the input is obtained.

This current is supplied to the adder circuit 27. When the output switch _S0 is controlled, that is, when the corresponding digit signal is “1”, the FET 34 is connected to the adder circuit 27.
A current can flow through the FET 34, which current is supplied to the operational amplifier 36 of the summing circuit 27, for example. This operational amplifier 36
The drains of the FETs 34 of the conversion circuits 5 corresponding to the other code signal generating circuits A ₀ -A _o are connected to the input side of the code signal generating circuits A 0 -A o through the corresponding output switches S ₀ -S _o .

As mentioned earlier, the code signal generation circuit A ₀ ~ _{A o}
In each control circuit 23, the duty ratio of its high level and low level corresponds to the weight of the corresponding input digital signal in a constant period _T0 , and therefore the output of the switch 21 is smoothed by the smoothing circuit 24. Each output voltage corresponds to a weight, and the current output obtained by converting this voltage also corresponds to each weight. If the corresponding output switches S ₀ to _{S o} are controlled by digital signals, the adder circuit 2
At 7, an analog conversion output corresponding to the input digital signal is obtained.

In each of the code signal generation circuits A ₀ to A _o , a current of each weight is obtained by the voltage/current circuit 25, and even if high-speed switches are used as the output switches S ₀ to _{S o} , sufficient response can be achieved. can. Also, the smoothing circuit 24 always obtains its smoothed output, so its output is not affected by this time constant, and it responds to digital inputs at a high speed, converting digital signals that change at high speed. I can do that.

Further, resistors are used in the voltage-current conversion circuit 25 and the adder circuit 27, that is, resistors 35 and 37 in FIG. 5 are used, and the output thereof is influenced by the resistance values of these resistors. However, there is no need to adjust the resistance value itself. That is, in the initial adjustment of this digital-to-analog converter, for one of the code signal generation circuits A ₀ to A _o , for example, A ₀ , the corresponding one of the output switches S ₀ to _{S o} is controlled, that is, _the adder circuit 27 side, observe the conversion output at that time, that is, the output of terminal 28, with a digital voltmeter, for example, and set the setting value of the corresponding code signal generation circuit, that is, the setting circuit 26 of A ₀ , so that it becomes the correct value. What is necessary is to change it and adjust the switching ratio for the switch 21. The setting circuit 26 may be, for example, a digital switch, and the switch may be manually adjusted or may be controlled by applying an input signal from the outside as a register. In this way, all cut-off value errors such as variations in resistance values, offsets of operational amplifiers, and variations in the reference voltage applied to the terminal 22 can be corrected.

This process is performed for each code signal generation circuit. Furthermore, if necessary, if there is a risk that conversion errors may occur due to changes in each part, for example, resistance values, due to changes over time or changes in environmental temperature, the output terminals 28 of each code generation circuit may be connected in the same way. It is sufficient to supply the output to the output terminal and check whether the output is at a predetermined value at that time. If the output deviates from the predetermined value, the setting circuit 26 may be used to adjust the output.

According to the digital-to-analog converter improved in this way, there is no need to adjust the resistance value. Precise adjustment of the membrane resistive element requires, for example, laser trimming, which requires special expensive equipment and a lot of effort, but with this improved device of the invention, such adjustment can be omitted. Furthermore, during laser trimming, there is a risk that the resistive film will be distorted by high heat and its stability will deteriorate, but since such adjustment is not performed, a product with good stability can be obtained. Further, each part, especially the control circuit 23, etc., can be constructed with digital circuits, resulting in good stability, and the whole can be easily integrated into an integrated circuit.

The code signal generation circuits A ₀ to A _o correspond to the weights of the corresponding digits of the input digital signal, and as mentioned earlier, the outputs are only 2 ¹ , 2 ² , 2 ³ , 2 _o , for example. First, for example, one unit that can provide an output of 2 ⁰ and a plurality of units that can provide an output of 2 ² may be provided, and in short, it is sufficient to make them correspond to the weights of each digit of the input digital signal.

Furthermore, as described with reference to FIG. 5, when the voltage-current conversion circuit 25 is provided, the current flowing through the resistor 35 is the value obtained by dividing the output voltage of the smoothing circuit 24 by the resistance value of the resistor 35, and this is the value obtained by dividing the output voltage of the smoothing circuit 24 by the resistance value of the resistor 35. The output current will be . In other words, the output voltage of the smoothing circuit 24 corresponds to the weight, and therefore the output current also corresponds to the weight.

As can be understood from this, the outputs of all the smoothing circuits 24 of the code signal generation circuits A ₀ to A _o are kept constant, that is, the switching ratio of the switch 21 is kept constant, and the code signal generation circuits A ₀ to A By changing the resistance value of the resistor 35 in the voltage-current conversion circuit 25 of _o in accordance with the weight, an output current corresponding to the weight can be obtained. In this case, it is necessary to adjust the resistance value of the resistor 35 so that a current of a predetermined magnitude can be obtained. However, as mentioned earlier, setting circuit 2
The fine adjustment of the resistor 35 can be omitted by adjusting the setting value of the resistor 35, and therefore the weight can be easily determined by the resistance value of the resistor 35. In this case resistor 3
When 5 is constituted by a film resistance element, it is preferable to use a film resistance element obtained by the same process. The voltage-current conversion circuit 25 is not limited to the example shown in FIG. 5, and the addition circuit 27 is also not limited to this example.

It is also possible to output the outputs of the code signal generation circuits A ₀ to A _o as voltages and add the voltages. That is, in this example, as shown in FIG. 6 by the same reference numerals in the parts corresponding to those in _{FIG .}
The output of the smoothing circuit 24 is impedance-converted by a buffer circuit 41 as required and is supplied as a low impedance to output switches S0 to _{S0 ,} respectively. The voltages of the outputs of the output switches S ₀ to S _o are added in an adding circuit 27 . That is, the output switches S ₀ to S _o are connected to the input side of the operational amplifier 36 through resistors 1 ₁ to 1 _o , respectively. In the adder circuit 27, the adder gain is determined by the corresponding input resistor,
For example, the resistance value of the feedback resistor 37 is divided by the resistance value of 1 ₁ , and this gain can be amplified to an appropriate value. Also, in consideration of these factors, the gain of the buffer circuit 41 can be set to an appropriate gain instead of 1. The buffer circuit 41 may be omitted and the output of the smoothing circuit 24 may be supplied to the output switches _S0 to _S0 , respectively. In this case, the input resistors 1 ₁ to 1 _o are also omitted, and the resistors of the smoothing circuit 24 can be used as the adding resistors. Generally, the output resistance value of the smoothing circuit 24 is relatively large, so the gain of the adding circuit 27 is reduced.

Although it is necessary to correctly calibrate the DC signals generated by each code signal generation circuit A ₀ to A _o to have a predetermined level, one aspect of the present invention allows this to be done automatically. For this purpose, for example, as shown in FIG. 7, parts corresponding to those in FIG. 4 are given the same reference numerals.
In this example, a reference signal generation circuit 43 is provided. This reference signal generation circuit 43 can generate reference values for the weights generated in the code signal generation circuits _A0 to _Ao , and can always generate stable values that are not affected by resistance values. It is something that can be done. For example, in this example, a signal with a duty ratio corresponding to each reference value is generated and converted into a DC signal, and the circuit is constructed almost similarly to the code signal generation circuits A ₀ to _{A o} . That is, the switch _21s is controlled by the control circuit _23s to switch between the reference voltage of the terminal 22 and the ground, and the output of the switch _21s is sent to the smoothing circuit 2.
It is converted into a direct current for 4 _seconds and is further supplied to the buffer circuit 44. The buffer circuit 44 does not require a resistor element with a highly accurate resistance value, and may be one in which the output side of an operational amplifier 45 is directly fed back to the inverting input side, as shown in FIG. 8, for example.

A setting circuit _26s is similarly provided for providing a setting value that determines the duty ratio of the output of the control circuit _23s . The setting value of this setting circuit _26s is rewritten under the control of the control section 46.
This set value is selected in advance to a value that allows each code signal generating circuit _A0 to _Ao to obtain its reference value. The control unit 26 can be configured using, for example, a microcomputer, and its bus 47 includes a so-called
The CPU 48 is connected to a read-only memory 49 in which programs and various parameters are stored, a read/write memory 51, and the like. Ideal setting values corresponding to the weights of each code signal generation circuit _A0 to _Ao are stored in the read-only memory 49, and these are used as the corresponding setting values when calibrating the output of each code signal generation circuit. Read and set circuit 26
_s to cause the reference signal generation circuit 43 to generate an ideal reference value.

At the same time, the control unit 46 drives the drive circuit 52 and turns on the switch 53 to supply the signal obtained at the conversion output terminal 28 to the comparator 54 through the switch 53. Reference values are also given. In addition, in order to select one of the code signal generation circuits A ₀ to A _o to be calibrated, the output switch S ₀ is sent through the command lines d ₀ to d _o from the control circuit 46 and further through the OR circuits 2 ₁ to 2 _o . ~S _o is controlled by one of the output switches S ₀ ~S _o
As in the case of FIG. 4, is controlled through the OR circuits 2 ₁ to 2 _o by corresponding digit signals of the digital signals from the terminals t ₀ to t _o .

In this way, one of the code signal generating circuits, for example _A0 , is selected and only the output switch _S0 is controlled, while the other output switches _S1 to _S0 are left uncontrolled. At the same time, the setting circuit _26s in the reference signal generation circuit 43 is set to an ideal value corresponding to the code signal generation circuit _A0 , and therefore the reference signal generation circuit 43 has a reference value for the code signal generation circuit _A0 . can get. The converted output of the output terminal 28, that is, the converted output of the code signal generation circuit _A0 , is supplied to the comparator 54 through the switch 53 and compared with a reference value. The output of the comparator 54 is sent to the control circuit 46
The CPU 48 determines whether the signal is at a high level or a low level, and depending on the result, the setting value for the setting circuit 26 of the code signal generating circuit _A0 is set by +1 or -1 so that both inputs of the comparator 54 match. In other words, control is repeated so that the conversion output of the code signal generation circuit _A0 matches the reference value.

When the code signal generation circuit A ₀ is calibrated in this way, the next code signal generation circuit
The setting value of the setting circuit _26s is changed under the control of the CPU 48 in order to select _A1 so that only its output is obtained at the output terminal 28 and to obtain a corresponding reference value. In this way, the set value of the setting circuit in each code signal generating circuit is automatically adjusted so that the output for each code signal generating circuit becomes the correct reference value.

The settings for the setting circuit _26s may be made by reading out the setting values themselves from the read-only memory 49, or by storing a plurality of setting values corresponding to the code signal generation circuits _A0 to _Ao in the setting circuit _26s in advance. Only one of them may be selected and supplied to the control circuit _23s by a command from the control section 46. A control circuit 46 is configured to periodically calibrate the output of the code signal generation circuit to a reference value.
Alternatively, a command to start calibration may be given to the control circuit 46 manually, for example, if necessary.

In the reference signal generation circuit 43, the smoothing circuit 24
Due to the existence of _s , when the set value of the setting circuit 26 _s is changed, it takes some time to obtain the correct reference value corresponding to the set value, that is, there is a delay corresponding to the time constant of the smoothing circuit 24. However, this can be done by calibrating each code signal generation circuit when not using this conversion device or before using it.
There is no need to do it at such high speed. Therefore, the reference signal generating circuit 43 can obtain a very highly accurate reference value. Similarly, reference signal generation circuit 4
3 may also be used that can stably obtain other highly accurate reference values. Further, the control section 46 may be configured as a sequential hardware without using a microcomputer.

In this way, each code signal generation circuit can be easily calibrated. Therefore, it is easy to calibrate to eliminate the effects of fluctuations in the reference voltage, such as fluctuations caused by replacing the Zener diode in the reference voltage circuit, fluctuations in resistance value in the voltage-current circuit 25, and changes over time. Therefore, highly accurate conversion output can always be obtained. Further, the reference signal generation circuit 443 can also be easily integrated.

Another aspect of the invention is the above-mentioned digital-to-analog conversion using a code signal generation circuit,
It shares the analog-to-digital conversion that obtains weights with conventional resistor circuits. In that case, conventional digital-to-analog conversion is performed on the lower bits of the input digital signal, and digital-to-analog conversion using a code signal generation circuit is performed on the upper bits.

For example, as shown in FIG. 9 with the same reference numerals attached to parts corresponding to those in FIG. 8, a lower bit conversion section 56 is provided. This lower bit converter 56 uses a resistor circuit to obtain a signal corresponding to the weight of each digital signal to be converted, and its accuracy is determined by the resistance value of the resistor element. This lower bit conversion section 56 can be constructed in the same manner as shown in FIG. . The switches S ₀ to S ₁₁ connected to the collector of each transistor are controlled by the lower bits of t ₀ to t ₁₁ among the terminals t ₀ to _{t 15} of the input digital signal, and are connected to the ground side wire 57.
and a line 58 on the adder circuit side. The switches S ₀ to S ₁₁ are controlled by the lower bits of the input digital signal, and the outputs of the lower digit conversion section 56 are added by the adder circuit 27 to perform conversion on the lower digits.

Furthermore, four code signal generating circuits _A12 to _A15 are provided corresponding to the upper digits of the input signals of the terminals _t12 to _t15 . The outputs of these code signal generation circuits are sent to the ground side line 57 or the adder circuit 27 side line 58 by the output switches S ₁₂ to _{S 15} according to the digit signals corresponding to each digit from the terminals t ₁₂ to t ₁₅ . Connection is switched. In this example, as in the case of FIG. 7, automatic calibration is performed, and a reference signal generation circuit 43 is also provided. The code signal generators A ₁₂ to _{A 15} constitute an upper digit converter 59, and this converter 59 supplies the conversion output for each of the upper 4 bits of the input digital signal to the adder circuit 27 to convert it into an analog signal. is converted to

In other words, each digit signal of the input digital signal is
The bit outputs of the lower digit converter 56 and the upper digit converter 59 are added to the adder circuit 2 by controlling S ₀ to S ₁₅ respectively.
7 and the total conversion output is obtained at terminal 28. If the output terminal of the lower digit converter 66 is derived only from the output terminal of the adder circuit 12 as described in FIG. 1, the output of the adder circuit 12 may be supplied to the adder circuit 27.

By doing as shown in FIG. 9, the lower digit conversion unit 56
You can use commercially available ones,
Moreover, the conversion unit 56 does not require very strict adjustment, that is, it does not require strict adjustments such as laser trimming, and even if the output accuracy is not very high, the conversion is for the lower bits, so the fluctuation value with respect to the magnitude of the conversion output is Since a relatively large percentage is allowed, inexpensive items can be used and can be easily configured. However, in the upper digits, the absolute value of the conversion output is large, so the fluctuation is a very small percentage value. As mentioned above, such high conversion accuracy is achieved by providing a code signal generation circuit to generate a signal corresponding to the weight of each bit, and extracting the output as a digital signal. As the high-order digit conversion section 59, it is possible to easily obtain one with high precision, which was previously considered difficult as a whole. for example
Converting 16-bit digital input is also easy.

As described above, according to the present invention, it is possible to easily obtain a highly accurate conversion output, and it is also easy to integrate the converter into an integrated circuit. Moreover, it is possible to obtain a device that operates at high speed, and the operation is also stable.

[Brief explanation of the drawing]

Fig. 1 is a connection diagram showing a conventional digital-to-analog converter that obtains a weighted signal using a resistor circuit, and Fig. 2 is a block diagram showing a conventional converter which obtains digital-to-analog conversion from its DC output by changing the duty ratio. Figure 3 is a waveform diagram for explaining the operation.
Fig. 4 is a block diagram showing an example of an improved digital-to-analog converter, Fig. 5 is a connection diagram showing a part of the concrete example of Fig. 4, and Fig. 6 shows voltage addition with the code signal generation circuit as voltage output. FIG. 7 is a block diagram showing an example of the digital-to-analog converter according to the present invention, which has a function of automatically calibrating the output of the code signal generator, and FIG. A connection diagram showing a specific example of a reference signal generating device, and FIG. 9 shows an example of a digital-to-analog converter according to the present invention, which uses both a conventional digital-to-analog converter and a digital-to-analog converter using a code signal generating circuit. It is a block diagram. 21: Switch, 22: Terminal to which reference voltage is applied, 23: Control circuit, 24: Smoothing circuit, 25:
voltage-current conversion circuit, 26: setting circuit, 27: addition circuit, 28: conversion output terminal, 43: reference signal generation circuit, 46: microcomputer as control section, 47: bus, 53: switch, 54: comparator, 56: Lower digit conversion section, 59: Upper digit conversion section.

Claims (1)

[Claims] 1. A switch that switches and outputs a reference voltage, a smoothing circuit that converts the switch output into DC, a control circuit that controls the switching ratio of the switching, and whose switching ratio is determined by a set value, and a control circuit that controls the switching ratio of the above-mentioned switching, and a control circuit that controls the switching ratio of the above-mentioned switching. A plurality of code signal generation circuits are provided, each having a setting means for giving a predetermined weight, and a plurality of code signal generation circuits having different switching ratios to obtain a DC output corresponding to a predetermined weight. an output switch that selectively extracts the output of the code signal generation circuit according to each digit signal of the input digital signal to be converted; an adder circuit that adds the outputs of these output switches to obtain a converted analog output; a reference value generation circuit that generates a reference value for each of the outputs of the code signal generation circuit; a comparator that compares one selected output of the code signal generation circuit with a corresponding reference value of the reference signal generation circuit; A digital-to-analog conversion device comprising: a control section for controlling the set value of the setting means of the corresponding code signal generating circuit so that the two match according to the comparison result.