JPS633329B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a function value generation device for determining the value of a function for an encoded variable.

Numerical calculations regarding specific functions, such as trigonometric functions or hyperbolic functions, are one of the basic functions essential for arithmetic operations by electronic computers and the like. In addition, calculations involving the above-mentioned functions are often performed in numerical control devices or graphic display devices controlled by minicomputers, microcomputers, etc. when handling geometric coordinates.

Therefore, it is important to simplify and speed up the procedure and processing mechanism for generating a function value, that is, finding the value of a function for a given numerical value.

Among the conventional methods of generating function values, one that is relatively widely adopted because it is well suited to software methods is to expand the function into a polynomial regarding input variables and perform numerical calculations. be. Although this method has the advantage of requiring only a small amount of data to be memorized in advance, since it is an approximate calculation, it is necessary to perform repeated calculations even for high-order terms in order to obtain highly accurate solutions. However, it takes a long processing time and lacks high speed. In addition, the CORDIC algorithm, which is well known as a method for finding elementary functions, is well suited for hardware and firmware implementation, but it also has problems with solution convergence, takes a long processing time, and still requires high speed. It is not suitable for use in equipment.

On the other hand, advances in LSI technology have made it possible to provide large-capacity and inexpensive storage devices such as ROM, so when the number of inputs is relatively small, all required function values can be stored in advance. It may also be stored in a ROM or the like. However, if the number of inputs is large, for example if the input variables are represented with 16-bit binary precision, this method requires approximately 65K words of memory to store all the required function values. It requires ROM, etc., and is economically difficult to put into practical use.

In view of the above circumstances, it is an object of the present invention to provide a function value generation device that can generate function values for relatively highly accurate input variables at high speed with a simple device configuration, and that can reduce the required storage capacity. It's about doing.

According to the present invention, as a device for repeatedly calculating and obtaining a function value for a binary encoded input variable, one or more bits are sequentially calculated from the upper (or lower) of a plurality of binary input signals representing the input variable. means for sequentially taking out the input signals as one set; a counter for sequentially counting the group numbers of the input signals taken out; and a function value memory that is addressed by the output signal of the counter and the input signal belonging to the counted group number. A device, a register for accumulating the results of repeated calculations, an output signal of the function value storage device, and an output signal of the register are inputted, and addition, subtraction, multiplication, and division operations are performed according to a predetermined combination, and the results are returned to the register. a function value calculation device as an input, and the function value storage device stores in advance, for each group, a function value corresponding to a numerical value represented by an input signal belonging to the group according to the addressing. , representing input signals belonging to all groups from the numerical value accumulated in the register and the function value read from the function value storage device to the group number counted by the counter every time the counter counts; A function value generating device is obtained in which the function value for the input variable is obtained by repeating the procedure of calculating a function value for a numerical value using the function value calculation device and accumulating it in the register.

In summary, the present invention divides binary input signals representing input variables into a plurality of sets, stores function values for the input signals belonging to each set for each set, and repeatedly calculates the function values from these stored function values. It is characterized by restoring the function value for the original input variable through calculation.

The present invention provides that a function related to the sum of a plurality of variables is
This method can be applied to a family of functions that can be expressed as four arithmetic operations of functions regarding these individual variables.

The present invention provides a set of input signals divided into a plurality of parts,
Therefore, since function values are stored for numerical values each consisting of a smaller number of combinations, the capacity of storage devices such as ROM can be greatly reduced, and since it is suitable for repeated calculations, the device configuration can be simplified. .

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention, and shows, as an example, the configuration of a trigonometric sine/cosine function value generator.

In this example, it is assumed that a sine function value is generated for the input variable θ (in radians) in the range 0θ<π, but in order to use the storage device efficiently, the input variable θ is hexadecimal integer
Then encode it with the following relationship and rewrite X
is treated as an input variable. That is, X = ⁽ ₂ ^m _{/ π} ⁾ _θ ... ₍ ^{1 )} i=0,...,m-1). Furthermore, the bits representing the input variable X are divided into n groups of r bits each. That is, m=nr, and if m is not a multiple of r, a bit that is always 0 is appropriately added to the upper bits of X so that the above relationship is satisfied. Then, n variables X ₁ , . . . , X _o represented by bits belonging to each set are defined as follows. That is, Obviously, X=X ₁ +X ₂ +...+X _o . _Furthermore , if we write _it as Y _{0 = 0 Y k = X 1 +} ) = sinY _k-1 cosX _k + cosY _k-1 sinX _k …(3) cosY _k = cos (Y _k-1 +X _k ) = cosY _k-1 cosX _k −sinY _k-1 sinX _k …(4) The formula holds true. Equations (2) and (3) are finally calculated by changing k from 1 to n and calculating the sine/cosine function value for the input variable X as sinX=sinY _o cosX=cosY _o . Show what you can get.

This calculation requires each variable X ₁ ,...,X _o
Only sine and cosine function values for . Note that in the above explanation, the expressions such as sinX are defined as sinX=sinθ, etc. under the relationship of equation (1), and the same applies in the following explanation.

To simplify the explanation below, it is assumed, as an example, that the precision of the input variable X is 16 bits, and that the input signals representing the input variables are divided into four groups of 4 bits each. That is, m=16, r=4, n=4.

Referring to FIG. 1, reference numeral 1 denotes means for dividing the input signal representing the input variable X into a plurality of sets and sequentially taking out the signals, and is a 16-bit shift register having parallel input/output terminals. 2 is a 2-bit counter, 3 is a function value storage device, 4 is a function value calculation device, 5 is a register, 6 is a 2-bit counter, 7 is an OR circuit, 8
is a delay circuit.

Reference numeral 101 is a 16-bit input signal line that supplies input variable X, and is connected to the parallel input signal line of shift register 1. 102 is a parallel output signal line for the lower four bits of the shift register 1, which is connected to a part of the address signal line of the function value storage device 3. 201
is an output signal line of the counter 2, and is connected to the remaining address signal lines of the function value storage device 3. 3
01 is an output signal line of the function value storage device 3, and is connected to one input signal line of the function value calculation device 4. 401 is an output signal line of the function value calculation device 4, and is connected to an input signal line of the register 5. 50
Reference numeral 1 denotes an output signal line of the register 5 as well as an output signal line for outputting the function value obtained by the present function value generation device, and is connected to the other input signal line of the function value calculation device 4. 601 is a control signal line to which a first pulse signal is applied, and the shift register 1
It is connected to the shift pulse input signal line of the counter 6 and the clock input signal line of the counter 6. A signal line 602 transmits the carry signal of the counter 6, and is connected to the clock input signal line of the counter 2 and one input signal line of the OR circuit 7. 701 is a control signal line for applying a second pulse signal, and is connected to the reset input signal line of counters 2 and 6 and register 5, the set input signal line of shift register 1, and the other input signal line of OR circuit 7. Ru.
702 is an output signal line of the OR circuit 7 and is connected to an input signal line of the delay circuit 8. Reference numeral 801 denotes an output signal line of the delay circuit 8, which is connected to the set input signal line of the register 5.

Shift register 1 is shifted one bit at a time to the lower bit by applying a shift pulse, and therefore 4 bits are shifted to lower bits.
An input signal representing the variables X ₁ , ..., X ₄ can be taken for every shift pulse. counter 6 is 2
The four shift pulses are counted in bits and one carry signal is output each time. A counter 2 counts the carry signals. That is, the counter 2 counts the set number in synchronization with the input signals representing the variables X ₁ , . . . , X ₄ being taken out sequentially from the shift register 1, and has 2 bits. The function value storage device 3 is a 64-word ROM that is addressed by the 4-bit output signal of the shift register 1 and the 2-bit output signal of the counter 2.
The sine and cosine function values for X ₁ , . . . , X ₄ are stored in the upper half and lower half of each word corresponding to the addressing, respectively. More specifically, as an example, the variable X _k (k=1,...,
Regarding 4), set the value of sinX _k in the upper half of one word at address X _k /2 ^4(k-1) +16(k-1) and in the lower half.
Remember the value of cosX _k . The values of sinX _k , cosX _k, etc. are obtained in advance by other calculation means, and are expressed in floating point format with the same precision as the function values generated by this device, for example. .

The register 5 is for accumulating the function values finally calculated by repeated calculations, that is, the values of sinX _k-1 and cosX _k-1 in equations (3) and (4), and has the same storage format as the function value storage device 3. In this way, the sine function value is placed in the upper half,
The cosine function value is stored in the lower half, and the predetermined initial value is sinY ₀ (=0) and
The value of cosY ₀ (=1) can be set.
Further, to each of the output signal lines 301, 401, and 501, a sine function value is transmitted to the upper half signal, and a cosine function value is transmitted to the lower half signal.

A specific configuration of the function value calculation device 4 is shown in FIG.

In Figure 2, 41, 42, 43 and 44
numeral 45 is a multiplication circuit, numeral 45 is an addition circuit, and numeral 46 is a subtraction circuit, each of which performs an operation in the format of the stored function value, that is, in the above example, a floating point format. 301 ₁ and 301 ₂ are the upper half and lower half signal lines of the output signal line 301 of the function value storage device 3, respectively. Signal line 301 ₁ is connected to one input signal line of multiplication circuits 41 and 44 .

Signal line 301 ₂ is connected to one input signal line of multiplication circuits 42 and 43. 501 ₁ and 5
01 _{and 2} are the output signal lines 501 of register 5, respectively.
These are the upper half and lower half signal lines. Signal line 501 ₁ is connected to the other input signal line of multiplication circuits 42 and 44 . Signal line 501 ₂ is connected to the other input signal line of multiplication circuits 41 and 43. 402, 403, 404 and 405 are output signal lines of multiplication circuits 41, 42, 43 and 44, respectively. Output signal lines 402 and 403 are connected to respective input signal lines of adder circuit 45. Output signal lines 404 and 405 are subtraction circuit 4
6 input signal lines. 401
₁ and 401 ₂ are output signal lines of the addition circuit 45 and the subtraction circuit 46, respectively, and form the upper half and lower half of the output signal line 401 of the function value calculation device 4. That is, the function value calculation device 4 inputs the values of sinX _k and cosX _k read from the function value storage device 3 and the values of sinY _k-1 and cosY _k-1 accumulated in the register 5, and calculates the third and (4).

Referring again to FIG. 1, OR circuit 7 is provided to apply both the second pulse signal and the output signal of counter 6 to delay circuit 8. The delay circuit 8 is provided to delay the pulse signal by applying an amount corresponding to the reading time of the function value storage device 3 and the calculation time of the function value calculation device 4.

Next, the operation will be explained with reference to FIGS. 1 and 2.

If input variable X is supplied to signal line 101 and a second pulse signal is applied to control signal line 701 at the same time, input variable X is set to shift register 1, and its lower ₄ bits, that is, a signal representing variable is output to the output signal line 102. The second pulse signal also resets the counters 2 and 6 and sets the initial values sinY ₀ and cosY ₀ in the register 5. At this time, the values of sinX ₁ and cosX ₁ are read from the function value storage device 3 from the address indicated by the output signals of the shift register 1 and the counter 2 and supplied to the function value calculation device 4. The function value calculation device 4 receives the values of the sinX ₁ and cosX ₁ and the output signals sinY ₀ and cosY ₀ of the register 5, and calculates the values of sinY ₁ and cosY ₁ according to equations (2) and (3). and supplies it to the register 5 again. Here, the second pulse signal passes through the OR circuit 7, and the delay circuit 8 outputs the sinY ₁ ,
It is delayed until the value of cosY ₁ is calculated and applied to register 5, and at this timing register 5
The contents of are updated to the values of sinY ₁ and cosY ₁ . Next, the first pulse signal is serially slowed down to four control signal lines 60.
1, a signal representing the variable X ₂ is output to the output signal line 102 of the shift register 1.
Also, one kill signal is generated to the output signal line 602 of the counter 6, and the counter 2 counts by one. At this time, from the function value storage device 3, sinX ₂ ,
The value of cosX ₂ is read, and the contents of register 5 sinY ₁ ,
In addition to cosY ₁ , function value calculation device 4 calculates sinY ₂ and cosY ₂
is obtained. The carry signal passes through the OR circuit 7 and the delay circuit 8, and the values of sinY ₂ and cosY ₂ are updated and set in the register 5 again. Thereafter _, when the application of the first pulse signal is repeated and _the signal representing _the variable signal line 5
It can be taken out through 01.

For an input variable X with 16-bit precision, all
In order to store the values of sinX and cosX, 65536 words of ROM are required, whereas the function value storage device 3 in this embodiment has 64 words, so approximately
A huge reduction in storage capacity of 1/1000th is achieved.

FIG. 3 is a circuit diagram showing a second embodiment of the means 1 for sequentially taking out four sets of input signals of 4 bits each from the 16-bit input signal representing the input variable X shown in FIG. Like reference numbers indicate like components. Reference numeral 11 denotes a 16-bit register, which sets the input variable X supplied to the input signal line 101 in response to the second pulse signal applied to the control signal line 701. 12 is a selection circuit. 103, 104,
Reference numerals 105 and 106 are output signal lines of the register 11, and output signals of 4 bits each are taken out in order from the higher order, and are supplied to the selection circuit 12. The selection circuit 12 receives the output signal line 201 of the counter 2 and selects the output signal line 1 according to an instruction from the counter 2.
One set of signals 03, 104, 105, or 106 is selected and output to the output signal line 102.

That is, according to this embodiment, the input signals representing the variables X ₁ , . . . , X ₄ can be sequentially and rapidly extracted from the input signal representing the input variable X.

FIG. 4 shows a circuit diagram of a part of a sine/cosine function value generator for explaining a third embodiment of the present invention. To explain this in comparison with the first embodiment, m = 16, r = 1, n = 16. That is, 16 sets of input signals are taken one bit at a time from the 16-bit input signal of the input variable X. shall be.

Components with the same reference numbers as those in FIG. 1 are the same components, and components configured in exactly the same way have been omitted to simplify the drawing.

2' is a 4-bit counter, 31 is a ROM having a ternary state, 32 is a fixed register having a ternary state, and 33 is an inverter.

Reference numeral 102' denotes an output signal line of the lower one bit of the shift register 1, which is connected to the chip enable signal line of the ROM 31 and the input signal line of the inverter. 201' is a 4-bit output signal line of the counter 2', which is connected to the address signal line of the ROM 31. 302 and 303 are output signal lines of the ROM 31 and fixed register 32, respectively, and are wired to the output signal line 301 of the function value storage device 3.
Connected with OR. 304 is an inverter 33
The output signal line is connected to the chip enable signal line of the fixed register 32.

Here, equation (2) is written as X _k =0 or 2 ^k-1 k = 1,...,16. That is, sinX _k = sin0 or sin2 ^k-1 cosX _k = cos0 or cos2 ^k-1 , and it is utilized that the values of sin0 and cos0 are common to each variable X ₁ , . . . , X ₁₆ .

That is, to the ROM 31, sin2 ^k-1 is sent to one word at the address indicated by the counter 2', that is, address k-1.
Write the values of cos2 ^k-1 in the upper half and lower half, respectively. ROM31 has 16 words. Constants sin0 (=0) and cos0 (=0) are fixed and stored in the fixed register 32.

The input signal of the input variable
The counter 2', which is output to the output signal line 102' and set by the second pulse signal, counts the group number of the input signal taken out and indicates the address of the ROM 31 in synchronization with the first pulse signal. do.
At this time, the output signal of shift register 1 is an immediate variable X _k
When 1 bit representing 1 is 1, from ROM31
When the values of sin2 ^k-1 and cos2 ^k-1 are 0, the values of sin0 and cos0 are read from the individual register 32 and output to the output signal line 302 or 303, respectively. The output signal lines 302 and 303 are in a wired OR relationship, so one of the signals is sent to the output signal line 30.
Tell 1. That is, the value obtained to the output line 301 is
sinX _k and cosX _k . The operations of the other components are completely the same as those in the first embodiment, and will therefore be omitted.

According to this embodiment, when extracting one bit from the input signal representing the input variable X, each variable X ₁ ,
By sharing and storing the common function values sin0 and cos0 for ..., X _o , there is an effect of further halving the storage capacity of the ROM.

As is clear by analogy from the above embodiments, the present invention can also be applied to generating values of other trigonometric functions or hyperbolic functions. In the above embodiment, if continuous numerical values are supplied to the input variable X, continuous sine and cosine function values can be obtained at the same time, so it can also be used as an arc generator.

As explained above, the effect of the present invention is that the storage capacity of the function value storage device can be significantly reduced, and the number of repeated counting is at most the bit length of the input variable.
It is possible to generate function values at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a sine/cosine function value generator for explaining the first embodiment of the present invention, FIG. 2 is a circuit diagram showing the specific configuration of the function value calculation device, and FIG. Figure 3 is a circuit diagram showing a second embodiment of the means for dividing and extracting input signals into a plurality of sets and its peripheral parts, and Figure 4 is a sine/cosine function value generation diagram for explaining the third embodiment. FIG. 2 is a circuit diagram showing a partial configuration of the device. In the figure, 1... Means for dividing and extracting input signals into a plurality of groups, 11... Register for input variable X, 12... Selection circuit, 2, 2'... Counter for counting group numbers of input signals, 3 ...Function value storage device, 31...
ROM, 32...Fixed register, 33...Inverter, 4...Function value calculation device, 41, 42, 4
3, 44...Multiplication circuit, 45...Addition circuit, 46
...Subtraction circuit, 5...Register for accumulating the results of repeated calculations, 6...Counter, 7...OR circuit,
8...Delay circuit.

Claims (1)

[Claims] 1. A device that repeatedly calculates a function value for a binary-encoded input variable, and uses one or more bits as a set in order from the upper (or lower) of a plurality of binary input signals representing the input variable. a counter for sequentially counting the set numbers of the input signals taken out; a function value storage device addressed by the output signals of the counter and the input signals belonging to the counted set numbers; A register that accumulates calculation results, and a function that inputs the output signal of the function value storage device and the output signal of the register, performs addition, subtraction, multiplication, and division operations according to a predetermined combination, and inputs the result to the register again. the function value storage device stores in advance, for each group, a function value corresponding to a numerical value represented by an input signal belonging to the group according to the addressing, and the function value storage device every time the counter counts, the function value for the numerical value represented by the input signal belonging to all the groups from the numerical value accumulated in the register and the function value read from the function value storage device up to the group number counted by the counter. A function value generation device, characterized in that the function value for the input variable is obtained by repeating a procedure of calculating the function value in the function value calculation device and accumulating the calculated value in the register.