JPS633318B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a rhythm generating device that can slightly change the timing of a rhythm pattern in accordance with a song.

An example of the configuration of a conventional rhythm generator is shown in Figure 1.The pulse output of the pulse oscillator POS, which often has a variable repetition period, is connected to a digital counting circuit CNT.
The state of "1" and "0" in each stage of the counting circuit at that time is used as an address signal to read out a rhythm selection circuit such as a read-only memory ROM. The sound source circuit is controlled by the resulting output signal.
The TG is driven to generate a desired rhythm. In this case, the contents of the ROM are set at the time of initial manufacture, and the rhythm is always generated at the correct tempo as designed. Note that it is possible to change the tempo by changing the repetition period of the pulse oscillator POS, but this is an overall change, and after the change, the rhythm is accurately repeated again. Therefore, even if the accuracy of the mechanical tempo was maintained, it was impossible to satisfy the desire to adjust the timing slightly depending on the song's idea.

On the other hand, when a drum player is actually playing, he may give off the so-called ``motaru'' feeling as appropriate.
Unlike traditional electronic instruments, it is played at a precise tempo and is not monotonous. Therefore, conventional rhythm generators that can perform only at a fixed rhythm tempo are monotonous and easily boring.

SUMMARY OF THE INVENTION An object of the present invention is to provide a rhythm generating device capable of improving the above-mentioned drawbacks and slightly changing the timing of a rhythm pattern.

Embodiments of the present invention shown in the drawings will be described below. FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 shows an operation time chart of FIG. 2. In Fig. 2, CNT1 is a first counting circuit that digitally counts the number of input pulses, DEC is a switch that sequentially obtains pulses according to the output of each stage of the first counting circuit, and uses a binary decoder, for example, and SW.
is a switch for selecting a specific pulse from the sequential pulses, and GAT is a gate circuit for selecting a specific pulse from the sequential pulses.
The output of the counting circuit CNT1 and the output of the switch SW are controlled by a flip-flop output, which will be described later, and only one of them is allowed to pass. CNT2 is the second counting circuit using a down counter in this case, AD
1, AD2 indicates an AND circuit. FF is a flip-flop circuit which is set and reset by the calculation outputs of AD1 and AD2, and controls the selection of the pulses passing through the gate GAT. In FIG. 2, a pulse converter DEC, AND circuits AD1 and AD2, and a flip-flop FF constitute a pulse selection device to be applied to the second counting circuit. In addition, the most significant bit (MSB) is applied to the pulse from the first counting circuit CNT1 to the gate GAT, and the logic circuit AD1,
The lowest significant bit (LSB) of the second counting circuit CNT2 and the next bit are applied to AD2.

The repetition period of the oscillator POS determines the rhythm tempo, so adjust it to a predetermined value and set its output to the first
Applied to the counting circuit CNT1. The first counting circuit CNT1 counts each time a pulse arrives, and each stage of the counting circuit inverts the state of "1" and "0" at a predetermined time. When this state output is regarded as a binary number and decoded in the converter DEC, sequential pulses of the number of outputs related to the number of stages of the counting circuit CNT1 are obtained at the output of the converter DEC. Display this output as Q1…Qr…Qn. The phase of the highest bit MSB of each stage of the first counting circuit CNT1 is inverted by the inverter INV to generate the pulse train PL.
(see Figure 3 A), gate circuit GAT
and one of the outputs of the switch DEC.
Select Qr by switch SW and gate circuit
Use this as another input for GAT (see Figure 3 B). Since the output of the converter DEC goes around once in one cycle shown in Figure 3A, in the middle of the cycle as shown in Figure 3B,
Qr occurs. At the beginning of the pulse train PL, the flip-flop FF, etc. that operates as a selection device is not in the operating state, so the gate GAT is
is passed through, and the output Qr of the converter DEC is cut off. In the second counting circuit CNT2, all bits become "1" at the initial pulse (time T0) of the pulse train PS (see Figure 3 C) that has passed through the gate circuit GAT (because it is configured as a down counter). The A1 and A2 bits are also applied to AND circuits AD1 and AD2. Due to the pulse train PS, the bit terminal of A1 changes as shown in FIG. 3D, and the bit terminal of A2 changes as shown in FIG. 3E. pulse train
PS and A1 operate normally up to two PL pulses, but at time T1, A1 becomes “0”′,
A2 becomes “1” and the converter is turned on as shown in Figure 3.
Since the Qn pulse rises from DEC, the AND circuit AD2 operates at time T2, and the flip-flop
Set FF. (See Figure 3, G) Therefore
Terminal Q of FF becomes "1", gate GAT prohibits passage of pulse train PL, and output from switch SW (FIG. 3) is allowed to pass. Then, as shown in Fig. 3C, the pulse train PS finally rises in response to Qr at time T3, and at that time each bit of A1 and A2 changes to "1" and "0". A new read is made. Then, at time T4, the AND circuit AD1 operates for the next Qn pulse and resets the flip-flop FF. (Refer to Figure 3 H) Therefore, the gate circuit
GAT allows the pulse train PL to pass again, so the time
The next rise of the pulse PL at T5 also occurs in the output pulse train PS of the gate circuit.
After that, time T6 corresponds to T0, time T7 corresponds to T3, and the operation is repeated. Then, at the rising edge of the waveform shown in Figure 3 D, the address signal for reading the ROM changes to obtain a rhythm sound, so originally, every other rising edge of the pulse train PL in Figure 3 A should be accompanied by a musical note, e.g., an evenly spaced eighth. Where you should get the note (Fig. 3), the second
With the configuration shown in the figure, notes with varying intervals can be obtained, as shown in Figure 3. In other words, from T0 to T3, two eighth notes occur with an eighth rest in between, making the whole sound like a triplet, and when you hear it, the eighth note following the eighth rest is normal. This is similar to what happened a little later. Note that the position of the delayed note is related to the selected position of the output Qr of the converter DEC in Fig. 2, so it can be moved forward or backward by operating the switch SW, and its variable range is as shown in Fig. 3 A. Waveform PL
This is one period in .

In this way, according to the present invention, since a device is provided for selecting the pulse train applied to the second count for obtaining the address signal for reading out the rhythm selection circuit, monotony can be eliminated by appropriately changing the timing. By obtaining a rhythm generator, a more effective electronic musical instrument has been obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration of a conventional rhythm generating device, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is an operation time chart of FIG. POS...Pulse oscillator, TG...Sound source circuit,
CNT, CNT1, CNT2... Counting circuit, ROM...
...Rhythm selection circuit, DEC...Converter, SW...Switch, GAT...Gate circuit, AD1, AD2...
...AND circuit, FF...flip-flop circuit.

Claims (1)

[Claims] 1. A pulse oscillator, a first counting circuit that counts output pulses of the pulse oscillator, a converter that sequentially converts the output pulses of the first counting circuit into pulses, and a sequential pulse of the converter. a switch that selects one desired sequential pulse from among the rhythm patterns; a rhythm selection circuit that stores and selects a rhythm pattern; a second counting circuit that reads out the rhythm selection circuit; and a rhythm read out from the rhythm selection circuit. a rhythm sound source driven by pattern pulses to generate a rhythm sound; a control signal generating means for generating a control signal based on the final sequential pulse of the converter and a required output pulse of the second counting circuit; Selection for switching and selecting one of the output pulses of the first counting circuit and the sequential output pulses obtained from the switch based on the control signal of the control signal generating means and applying the selected one to the second counting circuit. A rhythm generating device comprising: means for partially changing the timing of rhythm pattern pulses read out from the rhythm selection circuit.