JPS6332956A - Package - Google Patents
PackageInfo
- Publication number
- JPS6332956A JPS6332956A JP61174751A JP17475186A JPS6332956A JP S6332956 A JPS6332956 A JP S6332956A JP 61174751 A JP61174751 A JP 61174751A JP 17475186 A JP17475186 A JP 17475186A JP S6332956 A JPS6332956 A JP S6332956A
- Authority
- JP
- Japan
- Prior art keywords
- cap
- electronic component
- heat dissipation
- frame
- block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000008018 melting Effects 0.000 claims abstract description 6
- 238000002844 melting Methods 0.000 claims abstract description 6
- 150000001875 compounds Chemical class 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims abstract description 4
- 230000017525 heat dissipation Effects 0.000 claims description 20
- LNUFLCYMSVYYNW-ZPJMAFJPSA-N [(2r,3r,4s,5r,6r)-2-[(2r,3r,4s,5r,6r)-6-[(2r,3r,4s,5r,6r)-6-[(2r,3r,4s,5r,6r)-6-[[(3s,5s,8r,9s,10s,13r,14s,17r)-10,13-dimethyl-17-[(2r)-6-methylheptan-2-yl]-2,3,4,5,6,7,8,9,11,12,14,15,16,17-tetradecahydro-1h-cyclopenta[a]phenanthren-3-yl]oxy]-4,5-disulfo Chemical compound O([C@@H]1[C@@H](COS(O)(=O)=O)O[C@@H]([C@@H]([C@H]1OS(O)(=O)=O)OS(O)(=O)=O)O[C@@H]1[C@@H](COS(O)(=O)=O)O[C@@H]([C@@H]([C@H]1OS(O)(=O)=O)OS(O)(=O)=O)O[C@@H]1[C@@H](COS(O)(=O)=O)O[C@H]([C@@H]([C@H]1OS(O)(=O)=O)OS(O)(=O)=O)O[C@@H]1C[C@@H]2CC[C@H]3[C@@H]4CC[C@@H]([C@]4(CC[C@@H]3[C@@]2(C)CC1)C)[C@H](C)CCCC(C)C)[C@H]1O[C@H](COS(O)(=O)=O)[C@@H](OS(O)(=O)=O)[C@H](OS(O)(=O)=O)[C@H]1OS(O)(=O)=O LNUFLCYMSVYYNW-ZPJMAFJPSA-N 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract 2
- 239000000463 material Substances 0.000 abstract 1
- 230000005855 radiation Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000008602 contraction Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 229920002545 silicone oil Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、電子装置等に使用されるパブケージに係わり
、特に放熱性に優れた高密度のパッケージに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a package used for electronic devices and the like, and particularly to a high-density package with excellent heat dissipation.
従来のこの種のパッケージとしては、例えば、特公昭６
０−５４７８５号公報に記載されているものがあって、
その概略を第３図に示す。Conventional packages of this type include, for example,
There is something described in Publication No. 0-54785,
The outline is shown in Fig. 3.
第３図に示すパッケージ１において、電子部品２が装着
されている回路基板３は、その周辺部および上方を覆う
キャップ４の下部内周に半田５で固着されている。電子
部品２は、上下部を低融点半田６．７によりキャップ４
および電子部品２にそれぞれ接着された放熱ブロック８
によってキャップ４に接続されている。電子部品２の生
じる熱は放熱ブロック８を介してキャップ４に伝達され
て放熱されている。In the package 1 shown in FIG. 3, the circuit board 3 on which the electronic component 2 is attached is fixed with solder 5 to the inner periphery of the lower part of the cap 4 that covers the periphery and upper part of the circuit board 3. The top and bottom of the electronic component 2 are capped with low melting point solder 6.7.
and a heat dissipation block 8 bonded to the electronic component 2, respectively.
It is connected to the cap 4 by. Heat generated by the electronic component 2 is transmitted to the cap 4 via the heat radiation block 8 and is radiated.
上述した従来のパッケージ１においては、電子部品２に
おいて発生した熱を、放熱ブロック８を介して垂直方向
にのみ逃がしていたので、放熱量に限界があり、より高
消費電力の消費電力の電子部品の実装には適用しがたい
という問題がある。In the conventional package 1 described above, the heat generated in the electronic component 2 is dissipated only in the vertical direction via the heat dissipation block 8, so there is a limit to the amount of heat dissipation, and the power consumption of the electronic component with higher power consumption is limited. There is a problem that it is difficult to apply to the implementation of .
本発明のパッケージは、回路基板の周囲に設けられた枠
体に固着されているキャップの裏面、すなわち電子部品
側に型取りされた放熱ブロックを設け、かつ電子部品と
上記放熱ブロック間に熱伝導性コンパウンドを設けたこ
とを特徴としている。The package of the present invention is provided with a molded heat dissipation block on the back side of the cap fixed to a frame provided around the circuit board, that is, on the electronic component side, and conducts heat between the electronic component and the heat dissipation block. It is characterized by the presence of a sex compound.
以下本発明の一実施例を、第１図および第２図に基づい
て説明する。An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.
第１図において、回路基板１１の上下部には複数の電子
部品１２および端子１３がそれぞれ固着されている。回
路基板１１の周辺部は、回路基板１１の周りを覆う枠体
１４の下部に形成された内向きの段部１４ａに固着され
ている。In FIG. 1, a plurality of electronic components 12 and terminals 13 are fixed to the upper and lower parts of a circuit board 11, respectively. The peripheral portion of the circuit board 11 is fixed to an inward step 14a formed at the bottom of a frame 14 that covers the circuit board 11.
裏面に凹状の収納部１５が形成されているキャップ１６
は、上記電子部品１２を覆うようにして枠体１４の上部
にねじ等により固着されている。A cap 16 with a concave storage portion 15 formed on the back side
is fixed to the upper part of the frame 14 with screws or the like so as to cover the electronic component 12.
キャップ１６は、熱伝導性のよいＣｕ系またはＡｆ系の
金属や、ＢｅＯやＡＮＮ等の絶縁材が用いられている。The cap 16 is made of a Cu-based or Af-based metal with good thermal conductivity, or an insulating material such as BeO or ANN.
上記キャップ１６の収納部１５内には、予め各電子部品
１２の高さにそれぞれ合うよに、高さを整合されて一体
化され、かつ凹部１７ａを有する放熱ブロック１７が設
けられている。この放熱ブロック１７は、その材質とし
て低融点金属、例えばＳｎ／Ｂｉ
（４２１５８ｗｔ％、融点１３８°Ｃ）や、Ｉｎ／Ｐｂ
／Ａｇ
（８０／１５１５ｗｔ％、融点１４９°Ｃ）等を用いれ
ば、予めキャップ１６に容易に接着できる。Inside the housing portion 15 of the cap 16, a heat dissipation block 17 is provided which is height-aligned and integrated in advance to match the height of each electronic component 12, and has a recess 17a. The heat dissipation block 17 is made of a low melting point metal such as Sn/Bi (42158wt%, melting point 138°C) or In/Pb.
/Ag (80/1515 wt%, melting point 149°C) or the like can be easily bonded to the cap 16 in advance.
上記放熱ブロック１７と電子部品１２との間は予め５０
μｍｍ程度の間隙が設けられていて、その間隙には硬化
しない熱伝動性コンパウンド１８が設けられている。熱
伝導性コンパウンド１８はＢｅＯやＡｆ等の粉末を入れ
た非流動性シリコンオイルが用いられる。The distance between the heat dissipation block 17 and the electronic component 12 is 50 mm in advance.
A gap on the order of μmm is provided, and a thermally conductive compound 18 that does not harden is provided in the gap. As the thermally conductive compound 18, non-fluid silicone oil containing powder such as BeO or Af is used.
電子部品１２で発生する熱は、硬化しない熱伝導性コン
パウンド１８を通り、放熱ブロック１７において垂直お
よび斜め上方に伝導して、キャップ１６に達する。キャ
ップ１６の上方にヒートシンク（図示略）を形成してお
けば、キャップ１６からの放熱が促進される。一方、動
作時または非動作時に生じる膨張および収縮に伴う電子
部品１２への応力は、５０μｍ程度の厚みの硬化しない
熱伝動性コンパウンド１８で吸収される。The heat generated by the electronic component 12 passes through the uncured thermally conductive compound 18 and is conducted vertically and diagonally upward in the heat dissipation block 17 to reach the cap 16 . If a heat sink (not shown) is formed above the cap 16, heat radiation from the cap 16 will be promoted. On the other hand, stress on the electronic component 12 due to expansion and contraction that occurs during operation or non-operation is absorbed by the unhardened thermally conductive compound 18 having a thickness of approximately 50 μm.
第２図は、変形された放熱ブロック１９が適用されてい
るパッケージを示す。FIG. 2 shows a package to which a modified heat dissipation block 19 is applied.
放熱ブロック１９は、前記放熱ブロック１７と同様に電
子部品１２の高さと合うように高さが整合されていて、
各電子部品１２との接着部以外の箇所には複数の凸部１
９ａが型取りされて形成されている。放熱ブロック１９
に適宜の数および形状の凸部１９ａを形成することによ
り、上記放熱ブロック１７と同様の放熱作用が行われる
。The height of the heat radiation block 19 is adjusted to match the height of the electronic component 12 similarly to the heat radiation block 17, and
A plurality of convex portions 1 are provided at locations other than the bonded portions with each electronic component 12.
9a is formed by molding. Heat dissipation block 19
By forming convex portions 19a of an appropriate number and shape in the heat dissipation block 17, a heat dissipation effect similar to that of the heat dissipation block 17 described above is achieved.
以上説明したように本発明によれば、電子部品とこれを
覆うように枠体上にもうけたキャップとの間に、型取り
された放熱ブロックと、熱伝動性コンパウンドを設ける
ことにより、電子部品の発生する熱を効率良く逃がすこ
とができる。As explained above, according to the present invention, by providing a molded heat dissipation block and a thermally conductive compound between the electronic component and the cap provided on the frame to cover it, the electronic component The heat generated by the can be efficiently dissipated.
第１図は本発明の一実施例を示すパッケージの縦断面図
、第２図は変形された放熱ブロックが適用されているパ
ッケージの縦断面図、第３図は従来のパッケージの縦断
面図である。
１１・・・・・・回路基板、１２・・・・・・電子部品
、１４・・・・・・枠体、１５・・・・・・収納部、１
６・・・・・・キャップ、１７・旧・・放熱ブロック、
１８１．１９・・・・・・熱伝動性コンパウンド。
出 願 人
日本電気株式会社
代 理 人FIG. 1 is a vertical cross-sectional view of a package showing an embodiment of the present invention, FIG. 2 is a vertical cross-sectional view of a package to which a modified heat dissipation block is applied, and FIG. 3 is a vertical cross-sectional view of a conventional package. be. 11... Circuit board, 12... Electronic component, 14... Frame, 15... Storage section, 1
6...cap, 17.old...heat radiation block,
181.19...Thermal conductive compound. Applicant: NEC Corporation Representative
Claims (1)
板が固着されていて、回路基板の周辺を囲うように設け
られた枠体と、上記枠体の電子部品側に設けられている
型取りされた放熱ブロックと、上記電子部品と放熱ブロ
ック間の間隙に設けられた熱伝導性コンパウンドとを備
えることを特徴とするパッケージ。 ２、前記放熱ブロックが、低融点金属であることを特徴
とする特許請求の範囲第１項記載のパッケージ。[Scope of Claims] 1. A circuit board on which an electronic component is mounted, a frame to which the circuit board is fixed and provided so as to surround the circuit board, and an electronic component side of the frame. A package comprising: a molded heat dissipation block provided in the electronic component; and a thermally conductive compound provided in a gap between the electronic component and the heat dissipation block. 2. The package according to claim 1, wherein the heat dissipation block is made of a low melting point metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61174751A JPS6332956A (en) | 1986-07-26 | 1986-07-26 | Package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61174751A JPS6332956A (en) | 1986-07-26 | 1986-07-26 | Package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6332956A true JPS6332956A (en) | 1988-02-12 |
Family
ID=15984045
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61174751A Pending JPS6332956A (en) | 1986-07-26 | 1986-07-26 | Package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6332956A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0997938A2 (en) * | 1998-07-08 | 2000-05-03 | Hitachi, Ltd. | Multi-chip module |
| JP2002093960A (en) * | 2000-09-12 | 2002-03-29 | Nec Corp | Cooling structure of multichip module and its manufacturing method |
| JP2007005670A (en) * | 2005-06-27 | 2007-01-11 | Fujitsu Ltd | Electronic part package and bonding assembly |
-
1986
- 1986-07-26 JP JP61174751A patent/JPS6332956A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0997938A2 (en) * | 1998-07-08 | 2000-05-03 | Hitachi, Ltd. | Multi-chip module |
| EP0997938A3 (en) * | 1998-07-08 | 2002-08-14 | Hitachi, Ltd. | Multi-chip module |
| JP2002093960A (en) * | 2000-09-12 | 2002-03-29 | Nec Corp | Cooling structure of multichip module and its manufacturing method |
| JP2007005670A (en) * | 2005-06-27 | 2007-01-11 | Fujitsu Ltd | Electronic part package and bonding assembly |
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