JPS63318776A - Heterojunction bipolar transistor - Google Patents

Heterojunction bipolar transistor

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Publication number
JPS63318776A
JPS63318776A JP15576787A JP15576787A JPS63318776A JP S63318776 A JPS63318776 A JP S63318776A JP 15576787 A JP15576787 A JP 15576787A JP 15576787 A JP15576787 A JP 15576787A JP S63318776 A JPS63318776 A JP S63318776A
Authority
JP
Japan
Prior art keywords
layer
base layer
conductivity type
type
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15576787A
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Japanese (ja)
Other versions
JPH0658914B2 (en
Inventor
Shinichi Tanaka
愼一 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62155767A priority Critical patent/JPH0658914B2/en
Publication of JPS63318776A publication Critical patent/JPS63318776A/en
Publication of JPH0658914B2 publication Critical patent/JPH0658914B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To obtain a heterojunction bipolar transistor which is more improved in high speed and high frequency performance thereof so as to have a base layer of low resistance in which recombination probability of minority carrier is low and conduction speed thereof is high, by for the base layer being composed of a lamination structure consisting of a lightly doped layer and a heavily doped layer whose thickness is approximately equal to the mean free path of a carrier of one conductivity type. CONSTITUTION:A base layer of the opposite conductivity type formed on a collector layer 3 of one conductivity type is composed of a lamination structure consisting of a lightly doped layer 4 and a heavily doped layer 5 whose thickness is approximately equal to the mean free path of a carrier of one conductivity type. For example, on a heavily doped layer 2 of an n<+> type GaAs layer formed on the surface of a semi-insulating substrate 1, a collector layer 3 of an n-type GaAa layer, a lightly doped base layer 4 of a p-type GaAs layer with a Be density of 1X10<18>atm/cm<3> and with a thickness of 1000Angstrom , and a heavily doped base layer 5 of a p<+> type GaAs layer with a Be density of 1X10<20>atm/cm<3> and with a thickness of 500Angstrom which is approximately equal to the mean free path of an electron are formed one after another. Moreover, on the base layer consisting of the layers 4 and 5, an emitter layer 6 of an n-type Al0.3Ga0.7As layer.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はへテロ接合バイポーラトランジスタに関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a heterojunction bipolar transistor.

〔従来の技術〕[Conventional technology]

今日、バイポーラトランジスタに使われる半導体材料と
して、従来のシリコンに代わり、GaAs等電子移動度
の高い化合物半導体を応用したものが注目を集めている
。特に、近年、分子線エピタキシャル(MBE)法や有
機金属CVD (MOCVD)法等製造技術が目ざまし
く進歩・発展したことによって、特性の良好なヘテロ接
合バイポーラトランジスタができるようになり、それが
現在主流のGaAsF E TやHEMTに代わる次世
代の高周波・高速デバイスとして非常に期待されるよう
になってきた。
BACKGROUND ART Today, compound semiconductors with high electron mobility, such as GaAs, are attracting attention as semiconductor materials used in bipolar transistors, instead of conventional silicon. In particular, in recent years, with the remarkable progress and development of manufacturing technologies such as molecular beam epitaxial (MBE) method and metal organic CVD (MOCVD) method, it has become possible to produce heterojunction bipolar transistors with good characteristics, which are now mainstream. It has become highly anticipated as a next-generation high-frequency, high-speed device to replace GaAsFETs and HEMTs.

このようなヘテロ接合バイポーラトランジスタの最も大
きな特徴は、エミッタ層にベース層よりも広い禁制帯幅
の半導材料を用いることにより、ベース層を高濃度化し
た場合でもベース層からエミッタ層への少数キャリヤの
注入を押えると共にエミッタ注入効率を大きく保つこと
ができることである。
The most important feature of such a heterojunction bipolar transistor is that the emitter layer is made of a semiconductor material with a wider bandgap than the base layer, so even if the base layer is highly doped, there is no trace of a small amount of energy from the base layer to the emitter layer. It is possible to suppress carrier injection and maintain high emitter injection efficiency.

第3図は従来のへテロ接合パイボーラトランジスタの第
1の例のバンド構造図である。
FIG. 3 is a band structure diagram of a first example of a conventional heterojunction pibora transistor.

この例のへテロ接合バイポーラトランジスタは、N型の
コレクタ層3′上にP型のベース層5′とベース層5′
よりも電子親和力が小さくがつ禁制帯幅が広いN型のエ
ミッタ層6′とを順次積層した構造をとり、ベース層5
′及びエミッタ96’の間の階段型へテロ接合の部分で
電子親和力の差に相当するエネルギーの不連続が伝導帯
に生じている。その結果、エミッタ層6′からベース層
5′に注入される電子9′は、第3図に模式的に示すよ
うに、そのエネルギー差に相当する初期運動エネルギー
によっていわゆるパリスティック飛行を行い、通常の拡
散による伝導よりも高速の伝導をする。従って、このい
わゆるパリスティック飛行による高速伝導で、ベース層
5′における少数キャリヤ(この場合電子)のベース走
行時間が短縮され、高速・高周波性能の優れたベテロ接
合バイポーラトランジスタが実現できる。
The heterojunction bipolar transistor of this example includes a P-type base layer 5' and a base layer 5' on an N-type collector layer 3'.
The base layer 5 has a structure in which an N-type emitter layer 6' having a smaller electron affinity and a wider forbidden band width is sequentially laminated.
An energy discontinuity corresponding to the difference in electron affinity occurs in the conduction band at the stepped heterojunction between the emitter 96' and the emitter 96'. As a result, the electrons 9' injected from the emitter layer 6' to the base layer 5' perform a so-called paristic flight due to the initial kinetic energy corresponding to the energy difference, as schematically shown in FIG. The conduction is faster than that by diffusion. Therefore, high-speed conduction due to so-called paristic flight shortens the base transit time of minority carriers (electrons in this case) in the base layer 5', making it possible to realize a beterojunction bipolar transistor with excellent high-speed and high-frequency performance.

しかしながら、このいわゆるパリスティック飛行が有効
な距離は、なかだが電子の平均自由工程程度なので、そ
の距離以上のところの電子の伝導は、通常の拡散機構に
依存した低速度の伝導となり、ベース層5′が通常非常
に高濃度にドープされたベテロ接合バイポーラトランジ
スタでは、走行中の電子の再結合確率が高くそのためか
えってベース透過率が低下して、高速・高周波性能が阻
害され飛躍的な性能の向上はあまり望めなくなる。
However, since the distance over which this so-called pallitic flight is effective is approximately the mean free path of the electron, the conduction of electrons beyond that distance becomes low-speed conduction that depends on the normal diffusion mechanism, and the base layer 5 In beterojunction bipolar transistors, which are usually doped with extremely high concentrations of becomes less hopeful.

第4図は従来のへテロ接合バイポーラトランジスタの第
2の例のバンド構造図である。
FIG. 4 is a band structure diagram of a second example of a conventional heterojunction bipolar transistor.

この例のへテロ接合バイポーラトランジスタは、N型の
コレクタ層3″上に結晶組成を変えたP型のグレイデッ
ドバンドギャップのベース層5″とベース層5″よりも
禁制帯幅が広いN型のエミッタ層6″とを順次積層した
構造であり、傾斜したベース層5〜の伝導帯に基づく内
部電界によってエミッタ層5″から注入された電子9″
が矢印10″のように加速されて拡散よりも速い伝導が
期待される。
The heterojunction bipolar transistor of this example has a P-type graded bandgap base layer 5'' with a different crystal composition on an N-type collector layer 3'' and an N-type with a wider forbidden band width than the base layer 5''. It has a structure in which emitter layers 6'' of
is expected to be accelerated as shown by arrow 10'', resulting in faster conduction than diffusion.

しかしながら、その内部電界が高くなり一定値を越える
ようになると谷間散乱が顕著になって、電子の平均移動
度が下る0例えば、AI!、、Ga1−NAsからなる
ベース層5″の層厚を1500人としてx : 0.1
5→Oとすると、内部電界は約10kV/1になり容易
に谷間散乱が起る条件になる。
However, when the internal electric field becomes high and exceeds a certain value, valley scattering becomes noticeable and the average mobility of electrons decreases.For example, AI! ,, assuming that the thickness of the base layer 5'' made of Ga1-NAs is 1500 layers, x: 0.1
When 5→O, the internal electric field becomes approximately 10 kV/1, a condition that easily causes valley scattering.

なお、第1の例の場合にも谷間散乱は起きるが、ヘテロ
接合部の電子親和力の差によるエネルギーのギャップが
あまり大きくなければ谷間散乱による影響は小さい。
Although valley scattering also occurs in the first example, the influence of valley scattering is small if the energy gap due to the difference in electron affinity at the heterojunction is not too large.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述したように従来のへテロ接合バイポーラトランジス
タの第1の例では、ベース層とエミッタ層との電子親和
力の差によるヘテロ接合部のエネルギーの不連続を利用
したいわゆるパリスティック飛行に基づく電子の高速伝
導によって高速・高周波性能の一層の向上を図っている
が、このパリスティックな伝導の有効な距離はたかだか
電子の平均自由行程程度でありそれ以降のベース層の伝
導は通常の拡散機構に従うので、ベース層の層厚を厚く
したり不純物濃度を高くしてベース抵抗を低減しようと
するとベース層における電子の伝導速度の低下や再結合
の割合の増大による電子のベース層透過率の減少が起り
高速・高周波性能が損われるという欠点がある。
As mentioned above, in the first example of the conventional heterojunction bipolar transistor, the high-speed electron flight is based on so-called pallitic flight, which takes advantage of the energy discontinuity of the heterojunction due to the difference in electron affinity between the base layer and the emitter layer. We aim to further improve high-speed and high-frequency performance through conduction, but the effective distance for this pallitic conduction is at most the mean free path of an electron, and subsequent conduction in the base layer follows the normal diffusion mechanism. If an attempt is made to reduce the base resistance by increasing the thickness of the base layer or increasing the impurity concentration, the transmittance of the electrons in the base layer will decrease due to a decrease in the conduction velocity of electrons in the base layer and an increase in the rate of recombination.・There is a drawback that high frequency performance is impaired.

又、第2の例では、グレイデッドバンドギャップのベー
ス層を採用することにより、ベース層の傾斜した伝導帯
に基づく内部電界により電子を加速して高速性能の向上
を図っているが、内部電界の強度がある一定値を越える
と谷間散乱が顕著になり電子の平均移動度が低下するの
で、高速・高周波性能の改善には限界がある。
In addition, in the second example, by adopting a graded bandgap base layer, electrons are accelerated by the internal electric field based on the inclined conduction band of the base layer to improve high-speed performance, but the internal electric field When the intensity exceeds a certain value, valley scattering becomes noticeable and the average mobility of electrons decreases, so there is a limit to the improvement of high-speed/high-frequency performance.

本発明の目的は、ベース層における少数キャリヤの再結
合確率が低くしかも伝導速度が速い高速・高周波性能の
一層優れた低ベース抵抗のへテロ接合バイポーラトラン
ジスタを提供することにある。
An object of the present invention is to provide a low base resistance heterojunction bipolar transistor with a low probability of recombination of minority carriers in the base layer, high conduction speed, and even better high-speed and high-frequency performance.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のへテロ接合バイポーラトランジスタは、−導電
型のコレクタ層上に形成した反対導電型のベース層と前
記ベース層上に形成した前記ベース層よりも電子親和力
が小さくかつ禁制帯幅が広い一導電型のエミッタ層とを
有するヘテロ接合バイポーラトランジスタにおいて、前
記ベース層が低濃度不純物層と一導電型のキャリヤの平
均自由行程にほぼ等しい厚さの高濃度不純物層との積層
からなる。
The heterojunction bipolar transistor of the present invention has a base layer of an opposite conductivity type formed on a collector layer of a negative conductivity type, and a base layer formed on the base layer that has a smaller electron affinity and a wider forbidden band width. In a heterojunction bipolar transistor having an emitter layer of one conductivity type, the base layer is composed of a laminated layer of a lightly doped impurity layer and a highly doped impurity layer having a thickness approximately equal to the mean free path of carriers of one conductivity type.

〔作用〕[Effect]

このような本発明のへテロ接合バイポーラトランジスタ
によると、エミッタから注入された電子は平均自由行程
程度の厚さの高濃度ベース層をパリスティック飛行によ
る高速伝導した後、今度は低濃度ベース層中をコレクタ
まで通常の拡散機構により比較的ゆるやかな走行を行わ
せることによって、ベース層におけるキャリヤの平均の
伝導速度の低下を防止すると共に再結合確率の増大を抑
えることが出来て、ベース抵抗が低くかつ注入効率の高
い高性能へテロ接合バイポーラトランジスタが実現可能
である。
According to such a heterojunction bipolar transistor of the present invention, electrons injected from the emitter conduct at high speed through a high concentration base layer with a thickness of about the mean free path, and then travel through a low concentration base layer through a paristic flight. By allowing carriers to travel relatively slowly to the collector using a normal diffusion mechanism, it is possible to prevent a decrease in the average conduction velocity of carriers in the base layer and to suppress an increase in the probability of recombination, resulting in a low base resistance. Moreover, a high-performance heterojunction bipolar transistor with high injection efficiency can be realized.

〔実施例〕   ゛ 第1図は本発明の一実施例の断面図である。[Example] ゛ FIG. 1 is a sectional view of an embodiment of the present invention.

この実施例は、半絶縁性基板1表面に設けたプロトンの
イオン注入による所定のパターンの絶縁領域1aにより
仕切られかつドーパントをSiとして不純物濃度が3 
X 10 ”ato腫/Ca13で層厚が4000人の
n” −GaAs層からなる高濃度層2をMBE法によ
り形成し、高濃度層2上にドーパントをSiとし不純物
濃度が5 X 1016atom/ c11’で層厚が
5000人のn−−GaAs層からなるコレクタ層3、
ドーパントをBeとし不純物濃度が1×1018ato
m/ clI’で層厚が1000人のp −GaAs層
からなる低濃度ベース層4及びドーパントをBeとし不
純物濃度がI X 10 ”atom/ ays’で層
厚が電子の平均自由工程距離にほぼ等しい500人のP
” −GaAs層からなる高濃度ベース層5をMBE法
により順次形成し、高濃度ベース層5上にドーパントを
Stとして不純物濃度が3 X 10 ”atom/c
ta’で層厚が2000人のn  Af (1,3Ga
(1,7As層からなるエミッタ層6及びドーパントを
Siとして不純物濃度が5 X 10 ”atom/ 
cta’で層厚が2000人のn” −GaAs層から
なる高濃度層7をMBE法により順次形成し、高濃度層
7からコレクタ層3の各層を所定のパターンに順次エツ
チングした後高濃度層2及び7並びに高濃度ベース層5
の上にそれぞれコレクタ及びエミッタ並びにベース電極
8C及び8e並びに8bを形成した構造となっている。
In this embodiment, the surface of a semi-insulating substrate 1 is partitioned by insulating regions 1a having a predetermined pattern formed by ion implantation of protons, and the dopant is Si and the impurity concentration is 3.
A high-concentration layer 2 consisting of an n-GaAs layer with a thickness of 4,000 layers and a layer thickness of X 10 "atoms/Ca13 is formed by the MBE method, and Si is used as a dopant on the high-concentration layer 2 so that the impurity concentration is 5 X 1016 atoms/c11. a collector layer 3 consisting of an n--GaAs layer with a layer thickness of 5000,
The dopant is Be and the impurity concentration is 1×1018ato.
A low concentration base layer 4 consisting of a p-GaAs layer with a thickness of 1000 m/clI' and a dopant of Be, an impurity concentration of I x 10 "atom/ays" and a layer thickness approximately equal to the mean free path distance of electrons. equal 500 P
A high concentration base layer 5 made of a -GaAs layer is sequentially formed by the MBE method, and the impurity concentration is 3 x 10'' atoms/c with St as a dopant on the high concentration base layer 5.
The layer thickness at ta' is 2000 people nAf (1,3Ga
(The emitter layer 6 consists of a 1,7As layer and the dopant is Si, and the impurity concentration is 5 x 10" atoms/
A high concentration layer 7 consisting of an n''-GaAs layer having a layer thickness of 2000 cta' is sequentially formed by the MBE method, and each layer from the high concentration layer 7 to the collector layer 3 is sequentially etched into a predetermined pattern. 2 and 7 and high concentration base layer 5
The structure has a collector, an emitter, and base electrodes 8C, 8e, and 8b formed thereon, respectively.

第2図は本発明の一実施例のバンド構造図である。FIG. 2 is a band structure diagram of an embodiment of the present invention.

この実施例のバンド構造は、ベース層が低濃度及び高濃
度ベース層4及び5からなっており、エミッタ層6と高
濃度ベース層5とが階段へテロ接合による伝導帯のエネ
ルギー不連続δEcが約0.1eV生じており、エミッ
タ層6から注入された電子9aはδEcに相当する初期
運動エネルギーによって平均自由行程距離にほぼ等しい
層厚の高濃度ベース層5中をいわゆるパリスティック飛
行で伝導してその運動エネルギーを失い、以降低濃度ベ
ース層4を拡散によって走行してコレクタ層3に到達す
る。
In the band structure of this example, the base layer consists of low concentration and high concentration base layers 4 and 5, and the energy discontinuity δEc of the conduction band is caused by the step heterojunction between the emitter layer 6 and the high concentration base layer 5. The electron 9a injected from the emitter layer 6 is conducted in a so-called pallistic flight through the highly concentrated base layer 5 having a layer thickness approximately equal to the mean free path distance due to the initial kinetic energy corresponding to δEc. It loses its kinetic energy and then travels through the low concentration base layer 4 by diffusion to reach the collector layer 3.

ところで、P型の不純物をドープしたGaAs中の再結
合寿命τ。は、経験的に、 と表わすことができる。ここで、NTはP型の不純物濃
度、N ratは実験との参照濃度である。即ち、不純
物濃度N、が低くなるにつれて電子の再結合寿命τ。が
伸びる。
By the way, the recombination lifetime τ in GaAs doped with P-type impurities. can be expressed empirically as Here, NT is a P-type impurity concentration, and N rat is a reference concentration from the experiment. That is, as the impurity concentration N decreases, the electron recombination lifetime τ increases. grows.

従って、この実施例のように、エミッタ層6より注入さ
れた電子が、再結合確率の高い高濃度ベース層5中はパ
リスティック飛行により高速で伝導し、再結合確率の低
い低濃度ベース層4中は通常の拡散走行、により伝導す
るので、拡散走行中の再結合確率の増大を抑えて注入効
率を改善すと共に高濃度ベース層5によりベース抵抗を
低減し高速・高周波性能を一段と向上したベテロ接合バ
イボーラトランジスタを実現できる。
Therefore, as in this embodiment, electrons injected from the emitter layer 6 are conducted at high speed by pallitic flight in the high concentration base layer 5 where the recombination probability is high, and the low concentration base layer 4 where the recombination probability is low. Since conduction occurs through normal diffusion, the injection efficiency is improved by suppressing the increase in recombination probability during diffusion, and the high-concentration base layer 5 reduces base resistance, further improving high-speed and high-frequency performance. A junction bibolar transistor can be realized.

ただし、この実施例では、半導体材料として互いに格子
整合しているAj7 GaAsとGaAsとを用いたが
、特にこれに限定せず電子親和力に差のあるものなら何
れでもよく、又、格子不整合の材料を使用しても良い。
However, in this example, Aj7 GaAs and GaAs, which are lattice-matched to each other, were used as semiconductor materials, but the material is not limited to this, and any material with a difference in electron affinity may be used. Materials may be used.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明では、ベース層を低濃度ベー
ス層と層厚が少数キャリヤの平均自由打紙程度の高濃度
ベース層とで構成することにより、ベース抵抗及びベー
ス層中の少数キャリヤの再結合確率を低減し高速・高周
波性能を一段と向上したベテロ接合バイポーラトランジ
スタを実現できるという効果がある。
As explained above, in the present invention, the base layer is composed of a low-concentration base layer and a high-concentration base layer whose layer thickness is about the same as that of paper with a mean free flow of minority carriers, thereby reducing the base resistance and the minority carriers in the base layer. This has the effect of reducing the recombination probability and realizing a beterojunction bipolar transistor with further improved high-speed and high-frequency performance.

ぞれ従来のへテロ接合バイポーラトランジスタの第1及
び第2の例のバンド構造図である。
1A and 1B are band structure diagrams of first and second examples of conventional heterojunction bipolar transistors, respectively; FIG.

1・・・半絶縁性基板、1a・・・絶縁領域、2・・・
高濃度層、3.3’、3″・・・コレクタ層、4・・・
低濃度ベース層、5・・・高濃度ベース層、5′、5″
・・・ベース層、6.6’ 、6″・・・エミッタ層1
.7・・・高濃度層、8b・・・ベース電極、8C・・
・コレクタ電極、8 e−・・エミッタ電極、9a、9
b、9’ 。
1... Semi-insulating substrate, 1a... Insulating region, 2...
High concentration layer, 3.3', 3''...Collector layer, 4...
Low concentration base layer, 5...High concentration base layer, 5', 5''
...Base layer, 6.6', 6''...Emitter layer 1
.. 7... High concentration layer, 8b... Base electrode, 8C...
・Collector electrode, 8 e-... Emitter electrode, 9a, 9
b, 9'.

9″・・・電子、11,12.13・・・フェルミレベ
ル。
9″...electron, 11,12.13...Fermi level.

箔ど詔 防4図Hakudo edict Defense 4 figure

Claims (1)

【特許請求の範囲】[Claims] 一導電型のコレクタ層上に形成した反対導電型のベース
層と前記ベース層上に形成した前記ベース層よりも電子
親和力が小さくかつ禁制帯幅が広い一導電型のエミッタ
層とを有するヘテロ接合バイポーラトランジスタにおい
て、前記ベース層が低濃度不純物層と一導電型のキャリ
ヤの平均自由行程にほぼ等しい厚さの高濃度不純物層と
の積層からなることを特徴とするヘテロ接合バイポーラ
トランジスタ。
A heterojunction having a base layer of an opposite conductivity type formed on a collector layer of one conductivity type, and an emitter layer of one conductivity type formed on the base layer and having a smaller electron affinity and a wider forbidden band width than the base layer. 1. A heterojunction bipolar transistor, wherein the base layer is composed of a laminated layer of a lightly doped impurity layer and a highly doped impurity layer having a thickness approximately equal to the mean free path of carriers of one conductivity type.
JP62155767A 1987-06-22 1987-06-22 Heterojunction bipolar transistor Expired - Fee Related JPH0658914B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62155767A JPH0658914B2 (en) 1987-06-22 1987-06-22 Heterojunction bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62155767A JPH0658914B2 (en) 1987-06-22 1987-06-22 Heterojunction bipolar transistor

Publications (2)

Publication Number Publication Date
JPS63318776A true JPS63318776A (en) 1988-12-27
JPH0658914B2 JPH0658914B2 (en) 1994-08-03

Family

ID=15612964

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62155767A Expired - Fee Related JPH0658914B2 (en) 1987-06-22 1987-06-22 Heterojunction bipolar transistor

Country Status (1)

Country Link
JP (1) JPH0658914B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59132164A (en) * 1983-01-18 1984-07-30 Nippon Denso Co Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59132164A (en) * 1983-01-18 1984-07-30 Nippon Denso Co Ltd Semiconductor device

Also Published As

Publication number Publication date
JPH0658914B2 (en) 1994-08-03

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