JPS63318643A - Address display system - Google Patents

Abstract

PURPOSE:To unify an expression of an address to a logical address display and to observe, etc., information obtained by an emulator, by the logical address display, by providing a means for converting a physical address on a bus, to a logical address. CONSTITUTION:A given physical address P is checked by using adders 103-109, comparators 101, 111-117, and AND gates 119, 121. Subsequently, based on its result, by a logical address computer 123, the corresponding logical address L is obtained by using the physical address P and the contents bs1, bs2 of a base register. Also, the content (base address) BASE of the base register which has been used for generating its physical address are also outputted. Next, by comparing the address L with a logical address which has been stored in an emulator or a register in a host, an instruction is executed and an address of load/store of a data is monitored and various debugs can be executed. That is, an expression format of the address can be unified to a logical address display, and the debug work efficiency can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an address display method during display of trace results during debugging of a microprocessor system or the like.

[Technical ¥ of invention! ? In recent years, memory management units (memory management units) for converting logical addresses into physical addresses have been developed in microprocessor chips.
MMU) is increasingly being installed. Software/software for systems incorporating such microprocessors
In the section where hardware is supposed to be debugged, as in the past, by replacing the microprocessor in the target system with an emulator, information on the operating status of this target system can be collected, and if the specified τψ is running. It is extremely effective to interrupt the operation of the system at point U), which occurs at point U, and examine the process leading up to that point.

When tracing the operation of a target system program using an emulator using the conventional method, MMU
Since address translation is performed by , the address used (for example, an address specifying a break point, etc.) had to be an address that actually appears in path 1:, or a certain physical address. Also, by using the symbol table generated by the assembler, the assembler source
Code 1: where the in symbolic
Even during debugging, it was necessary to display the valley symbols registered in the symbol table as real addresses. Alternatively, start the trace operation even if it is displayed as a logical address in the symbol table.
It was necessary to use software to convert the display format of the symbol address necessary for l into a physical address display.

However, when a trace operation is performed using a physical address display in this manner, there is a problem that the trace result becomes difficult to understand. In other words, when displaying a disassembled trace result, if the operand part is an address, the expression format is naturally a logical address display, whereas the data address appearing on the bus or the address of an executed QI instruction is displayed as a logical address. Expression formats such as the following are converted by the MMU to represent the physical address actually output on the bus. In this way, since the expression format of the address in the operand part and the expression format of the address in the other parts are different, it is difficult to tell at first glance whether they both point to the same address or not. It gave a bad *V to the efficiency of debugging.

[Object of the Invention] It is an object of the present invention to solve the problems of the prior art described above, and to make it possible to observe information obtained by an emulator by displaying logical addresses.

[Invention 4! Summary According to an embodiment of the present invention, by providing a means for converting a physical address on a bus into a logical address, it is possible to display a logical address when instructing a debugging operation of a trace cap and outputting the result. I am making it available for use.

[Embodiment of the Invention] In the embodiment of the present invention, logical address-physical address conversion of a microprocessor (hereinafter referred to as microprocessor) to be traced is performed as follows.

Since the microprocessor's program counter (PC) is 16 bits, the logical address space is 64 bytes. This logical address space is divided into three areas AO1AI%A using 4-bit boundary registers BRI and BR2.
Divide into 2. That is, given a logical address L, L(brl 4 area AObrl
≦L<br2 + area AI b ``2≦L → area A2 (brl and br2 are boundary registers BRI and BH3, respectively)
(The contents of the address are shifted to the left by 12 bits.) Since the physical address is 20 bits, the physical address space is 1024 bytes. In order to map the logical address to the physical address space for each area AO1AI, A2, 8-bit base registers BS1. B.S.
2 is provided.

The following mapping is performed according to the area to which the selected logical address L falls. Physical address L Physical address P Area AO → L (Area AO゛) 11 area AI
+ L+bsl (area A1') area A2 → L+b
s2 (area A2°) (bsl and bs2 are the contents of base registers BSI and BS2 shifted to the left by 12 bits, respectively) If this mapping is expressed graphically, the second
The result will be as shown in the figure.

Since the above-mentioned address conversion is performed within the microprocessor, addresses that are stored on the bus for instruction fetches and data loads/stores are represented as physical addresses.In this embodiment, logical addresses are In order to perform tracing on the bus L, a circuit is provided to convert such a physical address of the bus L into a logical address. A conceptual block diagram of an example of the configuration of such a circuit is shown in FIG.

In FIG. 1, additions 103 to 109 and comparators 101 to 11 determine which area in the physical address space a given physical address P falls in as shown in FIG.
1 to 117, check using AND gate 119.121. Based on the result, the logical address meter H'JA123
Physical address P, base register contents bsl, bs
2 to obtain the corresponding logical address L. The contents of the base register (base address) BASE used to generate the physical address are also output.

Note that when a boundary register or base register is loaded, the address of that register and data loaded are simultaneously output outside the chip. Detect and latch it. The above brl, b'2, bsl, and bs2 are actually data latched in this way. Also, depending on the contents of the boundary register and base register, the physical address P is inversely converted to the logical address L. may not be determined uniquely, but in preparation for such cases, priorities are established between areas.Also, given physical address P
If it does not belong to any area (the diagonal FA portion of the physical address space in FIG. 2), an error is notified. Further, the configuration may be such that the address Ij, which is provided to the path L for DRAM refresh or DMA, is ignored.

In this way, the microprocessor development system can monitor the addresses for instruction execution and data load/store by comparing the logical address L that has been extracted with the logical address stored in a register in the emulator or host. You can perform various well-known debugging operations.

The assembler used in this example stores symbols and their corresponding logical addresses (and base addresses) in a symbol table used for symbolic debugging.
address) in the form of a pair. For example, corresponding to the assemble list shown in Table 1, a symbol table including the contents shown in Table 2 is obtained.

Table 1 1 sample 3 0R oooω0H 0000C31ω0 4LABELI JP LABE
L27 0RC101■OH 10003AFOOO9L^8EL2 LD A, (L
ABEL3) 10Q3C3100010JP LABE
L212 0RG 31FOOOHFO
OD 55 13 L^8EL3 D
EFB 551 (Table 2 LABELI 0OOOOOH LABEL2101000H LABEL331FOOOH (However, the upper two digits of the 6-digit hexadecimal number in the ORG pseudo-instruction in Table 1 and the address field in Table 2 are the base address, and the lower four digits are the logical address. In addition, the code for setting the boundary registers BRI, BR2, and base registers BS1 and BS2 is not shown in Table 1, but is performed separately.], Executing the program shown in Table 1 near symbol LABEL2 Table 3 shows a list of output trace results when the trace instruction trace about LABEL2 is given to the microprocessor development system to investigate the situation. Relative line number from the line corresponding to , the next two columns are the base address and logical address converted by 'tNj from the physical address on the path, next is the data on the path, next is the data on the path This is an appropriate display depending on the type (op code, operand, write/read data).

Table 3 1ine# address ape/data
mneonic opcode or 5
tatus time, nit ■geki≠■Amma■ -OQ3ω0000C3JP1ωO1, us-0020
0000100operand 1. uS()01
00000210 operand 1. u
Sabout 101ω03A LDA, (FOOD
I 1. uS4()01101ωl QQ
opcrand 1. uS4002101ω2
FQ operand 1. us4003
31FOO055datarcad 1. uS40
04101ω3C3JPlooO1, uS$00510
100400 operand 1. us4
00610100510 operand 1
．． In uS Table 3, for example, in the line labeled about, a byte is loaded from the logical address FOOO to the A register, but this addressing operation is performed on the bus t; It can be confirmed very easily by the fact that it is displayed. This address is actually physical address 4
0000) (appears on the bust, but if this is displayed as is, the correspondence will be difficult to understand.

Naturally, the present invention is not limited to the above-described embodiments, but includes various modifications. For example, the circuit shown in FIG. 1 for inverse address conversion may be in the form of a circuit for speed direction -1: and for reducing the number of parts. Furthermore, there are many address conversion methods other than the one shown in FIG. 2. In addition, there are various methods for debugging operations using microprocessor development system calculations other than those described above.

Even with such various modifications, the present invention does not lose its effectiveness.

〔Effect of the invention〕

As explained above, according to the present invention, the address expression format used during debugging can be unified to the logical address display, so the user does not have to pay attention to the correspondence between the physical and logical address displays. This greatly improves the efficiency of debugging. For example, since both the disassembled part in the trace result list and the part indicating addresses appearing on the path are displayed as logical addresses, it becomes easier to correspond between them.

[Brief explanation of drawings]

Figure 1 is a diagram for explaining an example of the configuration of a part that converts a logical address into a physical address in an embodiment of the present invention, and Figure m2 is a diagram for explaining an example of the correspondence between logical addresses and physical addresses. . 103-109: Adder

Claims (1)

[Claims] An address display method for a microprocessor development device comprising means for converting a physical address obtained based on the operation of a target system into a logical address display.