JPS63317858A - Control system for cache memory - Google Patents

Abstract

PURPOSE:To perform the instruction executing processes of a CPU within a block transfer period by providing a means which transfers the unit data which is under block transfer to a cache memory from a main memory to the CPU. CONSTITUTION:In case a data fetch request is received from a CPU 1 and no request data is stored in a cache memory 2, the data on a request address is stored in a register 7 and the block transfer is started to the memory 2 from a main memory 3 via a memory has 5. The unit data on the bus 5 which is under the block transfer is stored in a buffer register 8 along with the address of said data. A comparator 9 compares the address of the register 7a with the contents of the register 8 by a signal 11 received from the memory 2 and showing a block transfer state every time the unit data is transferred. When the coincidence is obtained from aid comparison, the data is sent to the CPU 1 via a unidirectional buffer 10. The CPU 1 continues its processing with the received data. Thus the block loading and instruction executing jobs are carried out in parallel with each other and therefore the throughput is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control method for a small-capacity, high-speed cache memory.

[Conventional technology]

FIG. 2 shows the overall configuration of a conventional computer centered on the cache memory. In the figure, 2 is a central processing unit, 2 is a small-capacity high-speed cache memory, 3 is a large-capacity main memory, 4 is a memory bus control device, and 5 is a memory bus.

Unless otherwise specified, the term "data" below means both instruction and operand data.

Next, the operation will be explained. When a data fetch request is issued from the central processing unit 1 to execute an instruction, the presence or absence of necessary data in the cache memory 2 is first checked. If the data exists, the data in the cache memory 2 is transferred to the central processing unit 1 via the memory bus 5, and no data is transferred from the main memory 3 via the memory bus 5.

However, if there is no required data in the cache memory 2, the several bytes of data before and after the required data are first transferred from the main memory 3 to the memory bus 5.
The data is transferred to the cache memory 2 via. This operation is called block loading. A predetermined amount of time is required to transfer this data consisting of blocks of several bytes. Since access to the cache memory 2 is faster than access to the main memory 3, the cache memory 2 is directly used for the execution of instructions by the central processing unit 1.

[Problems with conventional technology]

In the conventional method, during the block loading period, the memory bus 5
is exclusively used for data transfer between the cache memory 2 and the main memory 3, so even if a data fetch request is issued from the central processing unit 1, it will not be processed until the block load is completed.
The central processing unit 1 had to wait for data to be received. Such cases actually occur frequently due to the local nature of S/W, resulting in a problem that the processing capacity of the system is reduced.

This invention was made in order to improve the decrease in system throughput due to the waiting time of the central processing unit during the block loading period as described above. The purpose is to provide a cache memory control method that allows execution processing to continue.

[Means for solving problems]

In this invention, in the cache memory control method, when the data requested to be fetched from the central processing unit 1 does not exist in the cache memory 2, a block load is performed from the main memory 3 to the cache memory 2. , compares the information in register 7 and the information in buffer register 8 with register 7 that stores information on data for which a fetch request has been made, and buffer register 8 that holds information on data that has been loaded into cache memory 2. Comparator 9 and this comparator 9
A unidirectional buffer 10 is provided for transferring data in the buffer register 8 to the central processing unit 1 based on the comparison result.

[Effect]

The buffer register 8 is initialized when a block load occurs, and holds the data and its address for which the data transfer from the main memory 1 to the cache memory 2 has been completed during the block load period. When a data fetch request occurs from the central processing unit 1 to the main memory 3 during the block load period, the comparator 9 compares the contents of the register 7 and the contents of the buffer register 8, and repeatedly fetches the data from the buffer register until the block load is completed. 8 and search for the necessary data. If necessary data exists, the data is transferred to the central processing unit 1 via the unidirectional buffer 10, and the processing of the central processing unit 1 is continued.

An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, 1 is a central processing unit, 2 is a cache memory, 3 is a main memory, 4 is a memory bus control device, 5 is a memory bus, and 6 is a bidirectional buffer that separates the memory bus from the central processing unit l. . 7 is a register that holds the address for which a fetch request was made from the central processing unit 1 during block loading, and 8 is information regarding data transferred from main memory to cache memory (data and its address).
A buffer register 9 is a comparator that determines the presence or absence of data required by the central processing unit. 10 is a unidirectional buffer that drives data from the buffer register 8 to the central processing unit 1 when the comparator 9 determines that the requested data exists in the buffer register 8; 11 indicates that a block is being loaded; This is the control line shown. The bidirectional buffer 6 is normally connected to the central processing unit 1
It outputs data from the memory bus 5 to the memory bus 5, and conversely outputs data from the memory bus 5 to the central processing unit 1.

The operation will be explained below using FIG.

The operation of the present invention starts from the time when there is a data fetch request from the central processing unit 1, but the requested data does not exist in the cache memory 2 and is not hit, so block loading starts. When a block load begins, the buffer 6 is placed in both directions, the central processing unit 1 is disconnected from the memory bus 5, and the buffer memory 8 is initialized for writing. During the block load period, block data of several pytres and tens of bytes is transferred from the main memory 3 to the cache memory 2 in burst mode, and each unit of data and its address transferred in parallel is buffered. It is also transferred to memory 8.

On the other hand, the central processing unit 1 operates independently of the memory bus 5 and continues to request fetching of data in order to continue its own processing, but during block loading, the memory bus 5 The request will be bended.

On the other hand, the address of the data required by the central processing unit 1 is stored in the register 7, and compared with the contents of the buffer register 8 by the comparator 9 to check the presence or absence of the data. Data checking is performed until the block load is completed every time a new unit of data is transferred to the cache memory 2. When the presence of necessary data in the buffer register 8 is confirmed, the unidirectional buffer 10 is checked. It opens and sends the data to the central processing unit 1, and the data fetch request that was being bent is cleared. When the central processing unit 1 receives the necessary data, it moves on to the next process. In this way, the central processing unit 1 can continue processing even when the memory bus 5 is unavailable during block loading.

During this time, the block loading to the cache memory 2 is completed, so that the memory bus 5 and the central processing unit 1, which had been separated by the bidirectional buffer 6, are reconnected. Thereafter, the central processing unit 1 continues to receive and process the necessary data from the cache memory 2 at high speed.

In the above embodiment, a central processing unit is used as the data processing device, but a high-speed input/output processing device may be used, and the same effects as in the above embodiment can be expected.

〔Effect of the invention〕

As described above, according to the present invention, there are a register that stores information on data for which a fetch request has been made, a buffer register that stores information on data that has been loaded into the cache memory, and a register that stores information on data that has been loaded into the cache memory. A comparator that compares the information in the register with the information in the register, and a unidirectional buffer that transfers the data in the buffer register to the central processing unit based on the comparison result of the comparator, Even when the bus is occupied, if the data required by the central processing unit is partially stored in the cache memory, it can be transferred from the buffer register containing the data at the same timing as the cache memory via the unidirectional buffer. Data can be transferred to the central processing unit. Therefore, it is possible for the central processing unit to continue processing without waiting for all block loads to be completed, and block loads and instruction execution are performed in parallel, resulting in improved system throughput.

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram centered on a cache memory showing an embodiment of the present invention, and FIG. 2 is a configuration diagram showing a conventional method. ■...Central processing unit, 2...Cache memory, 3
...Main memory, 4...Memory bus control device, 5...
Memory bus, 6.10... Buffer, 7... Register, 8... Buffer register, 9... Comparator, 11... Signal line indicating block loader. Agent: Masuo Oiwa (2 persons) Procedural amendment (voluntary), Showa year, month, day 2, name of invention: Cache memory city” Ft visit ceremony 3, name of person making the amendment (601) Mitsubishi Electric Corporation Representative Moriya Shiki 4, agent address 2-2-3-5 Marunouchi, Chiyoda-ku, Tokyo, scope of patent claims subject to amendment, detailed description of the invention, drawings section. 6. Contents of amendment (11 patents) The scope of the claims is amended as shown in the attached sheet. (2) The phrase ``This operation will be utilized'' in the third to eighth lines of page 3 of the specification is deleted. (3) From page 4, line 20 to page 5, line 1 of the same book, "from main memory 1" is corrected to "from main memory 3." (4) The drawings and Figure 1 are attached to The above is amended as follows. 2. Claims: Toshi Toyoto vs. Support If the data requested to be fetched from the central processing unit does not exist in the cache memory, the data is blocked from the main memory to the cache memory. In a cache memory control method in which loading is performed, a register that stores information on the data for which the fetch request has been made, a buffer register that holds information on the data that has been completely loaded into the cache memory, and a register that stores information on the data that has been loaded into the cache memory; A cache memory control method comprising: a comparator that compares information in a buffer register; and a unidirectional buffer that transfers data in the buffer register to the central processing unit based on the comparison result of the comparator.

Claims (1)

[Claims] In a cache memory control method in which a block load is performed from main memory to cache memory when data requested to be fetched from a central processing unit does not exist in the cache memory, the fetch a register that stores information on requested data; a buffer register that holds information on data that has been loaded into the cache memory; a comparator that compares information in the register with information in the buffer register; A cache memory control system comprising: a unidirectional buffer that transfers data in the buffer register to the central processing unit based on a comparison result of a comparator.