JPH03255562A - Memory access controller - Google Patents

Abstract

PURPOSE:To improve the throughput as the system by providing a means for transferring data from a shared memory to an exclusive memory, and also, transferring a part or all of the data to a processor corresponding to the exclusive memory from the shared memory. CONSTITUTION:By detecting a fact that in block data transferred to exclusive memories 12, 22 from a shared memory 10 by a shared memory data transfer request, vector data loaded to processors 15, 25 from the exclusive memories 12, 22 by its subsequent vector load request is contained, the data which is being transferred to the exclusive memories 12, 22 from the shared memory 10 is transferred directly to the processors 15, 25, as well. In such a way, the vector load request processing can be executed at a high speed, and the throughput as the system can also be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory access control device, and particularly to a memory access control device that processes memory access requests from a plurality of processors. The present invention relates to an apparatus for processing data transfer requests between memories.

[Conventional technology]

In recent years, there has been an increasing demand for computers with high parallel processing capabilities, and many systems have a plurality of processors each having their own dedicated memory, as well as a memory that is shared by all processors. Conventionally, in such a system, when loading a series of data in the shared memory to a vector data register, etc. in the processor, it is necessary to first transfer it to the dedicated memory corresponding to the own processor and then load it into the processor from there. This simplified control.

Also, when you want to transfer vector data in a processor to a shared memory, control is simplified by first transferring it from the processor to the dedicated memory for its own processor, and then transferring it from there to the shared memory. Ta.

[Problem to be solved by the invention]

According to the memory access control device that performs the conventional processing described above, data is transferred to the dedicated memory in units of block data larger than the data to be loaded into the processor, so during data transfer from the shared memory to the dedicated memory, This has the disadvantage that the load request to the processor is forced to wait, resulting in a reduction in the throughput of the system.

In addition, since some data from the processor is stored in the corresponding dedicated memory, a data transfer request to the shared memory is forced to wait during the storage process, resulting in a reduction in system throughput.

[Means for Solving the Problems] A memory access control device of the present invention includes a plurality of processors, and at least one processor corresponding to each of the plurality of processors.
In a memory access control device that controls data transfer between a dedicated memory and a shared memory shared by the plurality of processors, the device transfers data from the shared memory to the dedicated memory, and also transfers data from the shared memory to the dedicated memory. and means for transferring part or all of the data to the processor of the computer.

The memory access control device of the present invention also includes a memory for controlling data transfer between a plurality of processors, at least one dedicated memory corresponding to each of the plurality of processors, and a shared memory shared among the plurality of processors. The access control device includes means for transferring data from the processor to a dedicated memory corresponding to the processor and transferring the data to the shared memory.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, one embodiment of the present invention includes shared memory 10° request reception control circuits 11 and 21 . Dedicated memories 12 and 22. Transfer control circuits 13 and 23. Data check circuits 14 and 24.
It consists of processors 15 and 25.

Processors 15 and 25 have exactly the same configuration and can each execute instructions in parallel. The shared memory 10 is a memory shared by the processors 15 and 25, and is addressed in bytes and has a dedicated memory 12 for each processor.
and 22, but the access time seen from each processor is slower than that of dedicated memory. Request reception control circuits 11 and 21. Dedicated memories 12 and 22. Transfer control circuits 13 and 23. Data check circuits 14 and 2
4 are dedicated circuits or memories corresponding to the processors 15 and 25, respectively, and have exactly the same configuration. Therefore, in the following explanation, for the sake of brevity, processor 25 is shown in parentheses.
Numbers of corresponding circuits, memory signal lines, etc. are shown.

In addition, in the specific operation explanation, the circuit corresponding to the processor 15 will be explained in detail, and the circuit corresponding to the processor 25 will be omitted. Request reception control circuit 11 (21
) is a circuit that controls the reception and sequential processing of access requests from the processor 15 (25>) to the shared memory 10 or the dedicated memory 12 (22) supplied via the signal line 151 (251). (22
) is a memory dedicated to the processor 15 (25), which is composed of multiple banks, addressed in byte units, and is transferred to the signal line 131 (2) under the control of the transfer control circuit 13 (23).
A predetermined access is performed in 1-byte units based on a code indicating the type of access request and a dedicated memory access address supplied via 31). When the dedicated memory 12 (22>write access), the write data is transferred to the signal line 132 (2
32), and read data in the case of read access is sent out from the signal line 133 (233).

Data is transferred between the dedicated memory 12 (22) and the shared memory in 1 kilobyte blocks of 1 byte x 1024 times under the control of the transfer control circuit 13 (23). The processor 15 reads consecutive 1 kilobyte block data from address O of the shared memory 10 and stores it at 204 of the read-only memory 12.
Block data transfer request to transfer from address 8 to consecutive addresses (hereinafter referred to as shared memory data transfer) - followed by the start address 2176 of the dedicated memory 12
A request (hereinafter referred to as a vector load request) is supplied to read 128 byte data of 128 elements consecutive from the address in the positive direction of the address with an inter-element distance of 1 byte and transfer it to the processor 15. FIG. 2 shows an image of the shared memory data transfer and the subsequent vector load, as well as the shared memory address and dedicated memory address.

When the request reception control circuit 11 receives the shared memory data transfer request, it sends the shared memory access request code (block data read) and the start address "O" of the shared memory access from the signal line 111, and also sends the block transfer data. A code indicating a request to write the transfer data to the dedicated memory 12 and the start address "2048" for accessing the dedicated memory are sent from the signal line 112 in synchronization with the timing when the data is transferred from the shared memory 10. The request reception control circuit 11 also has a function of checking successive access requests, and when it receives a vector load request following a shared memory data transfer request, a signal 1111 is sent.
3 sends a check valid signal, and the signal line 1
14, the code of the vector load request, the start address "2176", the inter-element distance "1", and the number of elements "128" are sent.Data check time N14 includes the subsequent vector load in the data transferred by the shared memory data transfer request. Check that the data is completely included,
If included, the circuit sends a high-speed access enable signal from the signal line 141 indicating that the data being transferred can be directly returned to the processor 15 as vector load data.
The operation will be explained in detail with reference to FIG. Here, in order to facilitate the subsequent explanation, various signals sent from the signal lines 111, 112, and 114 will be divided in detail. The code and address of the shared memory access request sent from the signal line 111 are sent to the signal lines 111-1 and 111 in that order.
-2. A dedicated memory write request for shared memory transfer data sent from the signal line 112 is sent to signal lines 112-1 and 112-2 in the order of code and address. Signal line 11
4, the code of the vector load request sent from signal line 114-1, the start address, the distance between elements, the number of elements,
114-2, 114-3, 114-4.

FIG. 3 is a diagram showing in detail the configuration of the data check circuit 14 of FIG. 1, and the data check circuit 14 includes registers 180 to 183. Address calculation circuit 184, 18
5. Distance check circuit 186, address check circuit 1
It is composed of 87. In FIG. 3, the signal lines having the same numbers as those in FIG. 1 are the same signal lines.

Currently, the register 180 is set with the start address "2048" for writing to the dedicated memory 12 by shared memory data transfer via the signal line 112-2. register 1
80 to 183 are sequentially supplied with the start address "2" of the vector load request via signal lines 114-2 to 114-4.
176", the inter-element distance "1", and the number of elements "128" are set. The address calculation circuit 184 is a circuit that calculates the final address of data to be written to the dedicated memory 12 during shared memory data transfer, and the signal line 1180 The block data size 1024'' is added to the write start address “2048” supplied via
2" and sends it from the signal line 1184. The address calculation circuit 185 calculates the vector load request when the distance between elements is 2" and sends it from the signal line 1184.
This is a circuit that calculates the final access address of the dedicated memory 12 when it is assumed that the address is for consecutive addresses.
Number of elements supplied from signal line 1183 to 76" 12
8'' is added to calculate the final address ``2304pa'' and sent from the signal line 1185. The distance check circuit 186 is a circuit that checks whether the inter-element distance of the vector load supplied via the signal 811182 is "1" and is for consecutive addresses.Currently, the inter-element distance of the vector load request is "1". ”, so the match signal is sent to the signal line 118.
Send from 6. The address check circuit 187 is a circuit that checks whether high-speed access is possible by directly transferring data being transferred from the shared memory 10 to the dedicated memory 12 to the processor 15 as vector load data, and is supplied via signal lines 1180 and 1184. Write the shared memory transfer data to the dedicated memory 12 The starting address ``2176'' and the final address ``of the vector load supplied from the signal lines 1181 and 1185 are within the range of the starting address ``2048'' and the final address ``3072''. 2304'' is included, and the check valid signal is supplied from the signal line 113 and the inter-element distance match signal is supplied from the signal line 1186, so the signal line 14
1. Sends out a signal that allows faster access.

Now return to Figure 1. The transfer control circuit 13 receives the shared memory 10 access request or signal &! supplied from the request reception control circuit 11 via the signal line 111. 112 and 114
This circuit receives a dedicated memory 12 access request supplied via the dedicated memory 12, sends the access request directly to the shared memory 10 or the dedicated memory 12, and controls the transfer of access data with the processor 16. The access request code and address for the shared memory data transfer request are on signal line 1]1(
The code is signal line 111-1. The address is a signal! 11l-
2), and the dedicated memory 12 write access request code and address for transfer data are supplied via the signal line 112 (
The code is signal line 112-1, the address is signal line 112-
2). Access request code of dedicated memory 12 of vector load request, distance between address elements,
The number of elements is signal line 114 (code is signal line 114-1, address is signal line 114-2, distance between elements is signal Ml 14
-3. The number of elements is supplied via signal line 114-4). A valid signal, code, and address for an access request to the dedicated memory 12 are sent to the signal line 131 (a valid signal is sent to the signal line 13
1-1. The code is signal line 131-2. The address is sent from the signal line 131-3), and the write data is sent from the signal line 132. Continuous output data from the dedicated memory 12 is supplied via a signal line 133. The valid signal, code, and address of the access request to the shared memory 10 are sent to the signal line 134 (the valid signal is sent to the signal line 1341, and the code is sent to the signal line 1
34-2. The address is sent from the signal line 134-3), and the write data is sent from the signal line 135. Shared memory read data is provided via signal line 136. The vector load data transferred to the processor 15 is a signal! 1137, and a signal indicating that the load data by high-speed access is valid is sent from the signal line 138. Transfer data from Brose Sisa 15 is on signal line 1
Supplied from 39. The transfer control circuit 13 is connected to the signal line 141
When a high-speed access enable signal is supplied via the shared memory data transfer from the shared memory 10 to the dedicated memory 12
It has a characteristic function of controlling the data being transferred to the processor 15 so that it is transferred as is to the processor 15 as subsequent vector load data.

Here, using FIG. 4, the transfer control circuit 13 in FIG.
The operation will be explained in detail.

FIG. 4 is a diagram showing in detail the configuration of the transfer control circuit 13 of FIG. 1, in which request decoding control circuits 1100. register 1101
~1105. Address generation diagram H1106, 1107, countdown circuit 111081109, count value check circuit 1110.1111, comparison circuit 1112. Valid flag register 111B, dedicated memory address selection circuit 1
114° request sending circuit 1115. Data switching circuit 111
It is composed of 6. In FIG. 4, the signal lines having the same numbers as those in FIG. 1 are the same signal lines.

Since the request decoding control circuit 1100 is supplied with a block data continuation request code for the shared memory via the signal line 111-1, it sends it out from the signal line 134-2 as a read request code for the shared memory, and also sends it out from the signal line 134-2 as a read request code for the shared memory. 1 sends out a request valid signal. register 11
01 is supplied and held through the signal !!111-2 and holds the start address "O" for reading block data, and is connected to the signal line 13.
The address is sent from 4-3. The shared memory 10 in FIG. 1 receives this block data read request through signal line 1.
36, the block data to be transferred to the dedicated memory 12 begins to be sent. The request decoding control circuit 11 synchronizes with the timing at which block data starts to be transferred from the shared memory 10.
Signal to 00! A private memory 12 write request for transfer data is provided via 112-1. Upon receiving the request, the request decoding control circuit 1000 generates a write request code for the dedicated memory 12 and sends it from the signal line 131-2, and also sends a dedicated memory 12 access address creation instruction signal from the signal line 1201. The register 1102 is a register that stores an address for writing transfer data from the shared memory l○ to the dedicated memory 12. When an address creation instruction signal is received from the signal line 1201, the write start address supplied via the signal line 112-2 is stored. Select and hold address "'2048". Countdown circuit 1108 is connected to signal line 1
When it receives an address creation instruction signal supplied via signal line 1310, it starts counting down from the total number of elements of the block data "1024" and continues counting down thereafter in response to an address update instruction signal supplied via signal line 1310. The count value is sent from signal line 1308. The count value check circuit 110 receives an address creation instruction signal supplied via the signal line 1201 and then checks the address generation instruction signal via the signal line 130.
8, and sends out an address update instruction signal from signal line 1310 until the count value reaches '0°'. The address generation circuit 1106 adds 1"' to the address supplied via the signal line 1302 to generate the write address of the next element, and the signal line 1306
Send from The register 1102 updates the signal line 1 every time an address update instruction signal is supplied via the signal line 1310.
It selects and holds the address supplied via 306 and sends it out from signal line 1302. The request decoding control circuit 1100 is supplied with a write request for the shared memory transfer data to the dedicated memory 12 via a signal line 112-1, and at the same time is supplied with a vector load request via a signal line 11t-1. The request decoding control circuit 1100 that received the request connects the signal line 14
When a high-speed access enable signal is supplied via the signal line 1202, a dedicated memory 12 access address creation instruction signal is sent out from the signal line 1202. When processing a normal vector load request alone, a read request code for the dedicated memory 12 is also generated and a signal is sent! However, when the write data by shared memory data transfer is directly transferred to the processor 15 as vector load data as in this embodiment, the read request is suppressed from being sent. The register 1103 is a register that selects and holds the dedicated memory 12 access address during vector load request processing, and when it receives an address creation instruction signal via the signal line 1202, it selects and holds the start address of the vector load supplied via the signal line 114-2. "21
76'' is selected and held.Register 1104 is connected to signal line 1.
When receiving an address creation instruction signal via the signal line 111-3, the inter-element distance of the vector load request supplied via the signal line 111-3 is set and held at "1". When register 1105 receives an address generation instruction signal via signal 111202, it sets and holds the number of vector load elements supplied via signal line 114-4, ``128''. When receiving the address instruction signal supplied through the signal line 1
The countdown is started by taking in the number of elements "128" supplied via the signal line 1311, and thereafter the countdown is continued by the address update instruction signal supplied via the signal line 1311. The count value is sent from signal line 1309. The count value check circuit 1111 is connected to the signal line 12
In response to the address creation instruction signal supplied via the signal line 1302, the address update instruction signal is sent out from the signal line 1311 until the count value reaches "0". Address generation port #
l1107 is the inter-element distance “1” supplied via the signal line 1304 to the address supplied via the signal line 1303.
” to create the write address of the next element and signal line 1.
307. Register 1103 is connected to signal line 131
Each time an address update instruction signal is supplied via signal line 1307, the address selected and held is transmitted via signal line 1303. The comparison circuit 1112 receives the write address to the dedicated memory 12 by transferring the shared memory data supplied from the signal line 1302 and the signal line 1303.
The circuit detects the match of the dedicated memory 12 access address by the vector load supplied from
Every time the addresses match eight times, an address match signal is sent from the signal line 1312. Valid flag register 1103
is an address match signal supplied via the signal i11312, and while the logic value "1" is set, and 1' is set, a data valid signal indicating the validity of the vector load data is sent from the signal line 38. When the processor 15 is supplied with this data valid signal, it takes in the data supplied from the signal line 37 as vector load data.The valid flag register 1103 outputs the data valid signal due to 128 address matches, and then transfers the data to the count value check circuit 111.
1 is reset to "O" when the count value "O'" is detected and the address update instruction signal is no longer supplied from the signal line 1311. The dedicated memory address selection circuit 1114 receives the signal! Dedicated memory 12 write address and signal line 1 by shared memory data transfer request supplied via 1302
The dedicated memory 12 write address is selected according to the vector load request supplied via the signal line 131-3.
Each time an address update instruction signal is supplied via a signal line 1310 in a circuit that sends data to the dedicated memory 12, a write address for the dedicated memory 12 is selected by the shared memory data transfer supplied via a signal line 1302.

If the address update instruction signal is not supplied, signal line 13
Select the address provided via 03. A request sending circuit 1115 receives a dedicated memory 12 write address update instruction signal by shared memory data transfer supplied via a signal line 1310 and a dedicated memory 12 continuous address update instruction signal by a vector load request supplied via a signal line 1311. In response, if at least one address update instruction signal is supplied, a special memory 12 access request valid signal is sent from the signal line 131-1. The data switching circuit 1116 is a circuit that controls switching of write and read data between the dedicated memory 12, the shared memory 10, and the processor 15, and when a shared memory data transfer request code is supplied from the signal line 134-2, the signal line Signals the shared memory read data provided via !136! 132, the data is sent as write data to the dedicated memory 12. At this time, when a vector load data valid signal is supplied from the signal line 138, the shared memory read data is directly sent out from the signal line 137 as vector load data. Normal signal line 131. If only a single vector load request code is supplied via the signal line 33, read data from the dedicated memory 12 supplied via the signal line 33 is sent out from the signal line 37.

Next, FIG. 5 shows the structure of another embodiment of the present invention. In FIG. 5, another embodiment of the invention is a shared memory 10a.
, request reception control circuits 11a and 21a, dedicated memory 12
a and 22a, transfer control circuits 13a and 23a, data check circuits 14a and 24a, and processor 15
There are 4 precepts from a and 25a to n.

The processors 15a and 25a have exactly the same configuration and can each execute instructions in parallel. shared memory 10a
is a shared memory for the processors 15a and 25a, which is addressed in bytes and has a larger capacity than the dedicated memories 12a and 22a corresponding to each processor, but the access time seen from each processor is slower than the dedicated memory. Request reception control circuits 11a and 21a, dedicated memories 12a and 22a, transfer control circuits 13a and 23a, and data check circuits 14a and 24a are dedicated circuits or memories corresponding to processors 15a and 25a, respectively, and have exactly the same configuration. Therefore, in the following description, for the sake of simplicity, numbers of circuits, memories, signal lines, etc. corresponding to the processor 25a will be shown in parentheses. Further, in the detailed description of the operation, the circuit corresponding to the processor 15a will be explained in detail, and the circuit corresponding to the processor 25a will be omitted. The request reception control circuit 11a (21a) controls the reception and sequential processing of access requests to the shared memory 10a or the dedicated memory 12a (22a) from the processor 15a (25a) supplied via the signal line 151a (251a). It is a circuit. Dedicated memory 12a
(22a) is a memory dedicated to the processor 15a (25a), which is composed of multiple banks, addressed in byte units, and is supplied via the signal line 131a (231a) under the control of the transfer control circuit 13a<23a). Data is read in units of bytes based on the read request signal and the access address of the dedicated memory 12, and the read data is sent out from the signal line 134a (234a). Also, signal line 13
Data is written in 1-byte units based on the write request and main memory write address supplied via 2a (2B2a). The write data is sent to the signal line 133a (233a
). Data is transferred between the dedicated memory 12a (22a) and the shared memory in units of 1 kilobyte blocks of 1 byte 1024 times under the control of the transfer control circuit 13a (23a).

Now, a request is made from the processor 15a to the request reception control circuit 11a via the signal line 151a to write 128-byte data of 128 elements consecutive from the starting address 2176 of the dedicated memory 12a with an inter-element distance of l bytes in the positive direction of the address ( (hereinafter referred to as a vector store request), followed by a consecutive 1 from address 2048 of the dedicated memory 12a.
Read kilo, byte block data, shared memory 1
A block data transfer request (hereinafter referred to as a shared memory data transfer request) is supplied to the continuous address calculation circuit from address O of 0a. Figure 2 shows an image of these vector stores and the subsequent shared memory data transfer.
The address of the dedicated memory 12a and the address of the shared memory 10a are shown.

The request reception control circuit 11a has a function of checking successive access requests, and when it receives a shared memory data transfer request following a vector store request, the signal line 11a
4 From a, the code of the vector store request, the start address "'2176'", the distance between elements "'1'°, and the number of elements "1"
28", and the shared memory 10 is sent from the signal line 112a.
A code indicating a request to read data to be transferred to a from the dedicated memory 12a and the start address "2048" for accessing the dedicated memory 12a are sent. At the same time, the signal line 113
A check valid signal is sent from a. The data check circuit 14a checks whether the preceding vector store data is completely included in the transfer data according to the shared memory data transfer request, and if it is included, the vector store data is directly transferred as the shared memory transfer data. This circuit sends out a high-speed access enable signal from the signal line 141a indicating that data can be transferred to the shared memory 12a, and its operation will be described in detail with reference to FIG. In order to facilitate the following explanation, the dedicated memory 12am output code and address for transferring shared memory data sent from the signal line 112a are assumed to be signal lines 112a-1112a-2 in this order.

Signal &1114 Signal lines 114a1, 114a-2, 114a-3, 114 in the order of code, start address, distance between elements, and number of elements of the vector store request sent from a.
Let it be a-4. Figure 7 shows the data check circuit 1 of Figure 5.
4a is a diagram showing the configuration of register 180 in detail.
a to 183 a, address calculation circuit 184a.

185a, a distance check circuit 186a, and an address check circuit 187a. In FIG. 7, the signal lines having the same numbers as those in FIG. 5 are the same signal lines.

Now registers 180a to 182a are connected to signal line 114a in order.
-2 to 114a-4, respectively, to the start address "2176" of the vector store request.

The inter-element distance "1" and the number of elements "128" are set. The register 183a is set with the read start address "2048" of the dedicated memory 12a by shared memory data transfer via the signal line 112a2.The address calculation circuit 184a determines that the vector store request is for consecutive addresses with an inter-element distance of "1". This is a circuit that calculates the final access address of the dedicated memory 12a when it is assumed that Final address ゛230
4'' and sends it out from the signal line 184a.The address calculation circuit 184a is a circuit that calculates the final address of the data read from the dedicated memory 12a in the shared memory data transfer. Block data size at address “2048”
1024 ” is added to the final address “” 3072
” and sends it out from the signal line 1183a.The distance check circuit 186a checks whether the inter-element distance of the vector store supplied via the signal line 1181a is “1” and corresponds to consecutive addresses. Since the inter-element distance of the current vector store request is "1", a match signal is sent from the signal line 1186a.

The address check circuit 187a is a circuit that checks whether high-speed access is possible in which the data in the vector store from the processor 15a to the dedicated memory 12a is transferred directly to the shared memory 10a as shared memory transfer data.
Signal lines 118: Reading start address “2048” and end address “2048” from the dedicated memory 12a of shared memory transfer data supplied via 3a and 1185a 307
Signals within 2” range * 1180a and 1184a
The address range includes the start address ゛2176'° and the last address ``2304'' of the vector store supplied via Therefore, a high-speed access enable signal is sent from the signal line 141a. Now return to Figure 1. When the request reception control circuit 11a receives the high-speed access enable signal via the signal line 141a, it sends a high-speed processing start instruction signal to start the read processing of the dedicated memory 12a for shared memory data transfer from the signal line 115a. An access request code (block data write) for writing to the shared memory 10a from the signal line 111a in synchronization with the timing when the block transfer start data at address 2048 is read from the dedicated memory 12a, and the start address for accessing the shared memory 10a. Send address O.

The transfer control circuit 3a directly transfers the shared memory 10a or This circuit sends an access request to the dedicated memory 12a and controls the transfer of access data with the processor 15a. The dedicated memory 12a read access request code and Atonis for the shared memory data transfer request are supplied via the signal line 112a (the code is the signal line 112a-1, the address is the signal IJil12a-2), The memory access request code and address are supplied via a signal line 111a (the code is signal line 111a-1 and the address is signal 11111a-2). Dedicated memory access request code for vector store request, address, distance between elements, number of elements are signal line 114a (code is signal line 114a-1°, address is signal line 114a-2, distance between elements is signal line 114
a-3, the number of elements is signal line 114a-4>. A request signal for a read request to the dedicated memory 12a, the address is sent from the signal line 131a (the request signal is sent from the signal line 131a-1, the address is sent from the signal line 131a-2), and a request signal for a write request, the address is sent from the signal line 132a. (The request signal is 132a-1, and the address is signal *1B2a-2). Data written to the dedicated memory 12a is sent from the signal line 133a, and data read from the dedicated memory 12a is sent via the signal &! 134a
Supplied via. Valid signals, codes, and addresses for access requests to the shared memory 10a are sent to the signal line 135a.
(The valid signal is signal line 135a-1, the code is signal line 1
35a-2, the address is the signal line 135a-3), and the write data is sent out from the signal line 136a. Shared memory 10a read data is supplied via signal line 137a. Vector store data from processor 15a is signal! The data to be transferred to the processor 15a is sent from the signal line 139a.

The transfer control circuit 13a has a characteristic function of transferring the vector store data sent from the processor 15a as-is to the shared memory 10a as shared memory transfer data when high-speed access is possible.

Here, using FIG. 8, the transfer control circuit 13 in FIG.
The operation of a will be explained in detail.

FIG. 8 is a diagram showing in detail the configuration of the transfer control circuit 13a shown in FIG. 1109a, count value check circuit 1
110a, 1111a, comparison circuit 1112a, switching control flag register 1113a, request sending circuit 1114a1
115a, and a data switching circuit 1116a. In FIG. 8, the signal lines having the same numbers as those in FIG. 5 are the same signal lines. The request control circuit 1100a is connected to the signal line 1
When the high-speed processing start instruction signal is supplied via the signal line 112a-1, the read processing of the dedicated memory 12a for shared memory data transfer that was supplied via the signal line 112a-1 is started, and a write request signal is sent to the dedicated memory 12a by vector store. is sent from the signal line 131a-1, and the signal ! l 1201a sends a special memory 12a access address creation instruction signal. The register 1102a is a register that holds an address for reading data transferred to the shared memory 10a from the dedicated memory 12a, and is connected to the signal line 1201a.
When an address creation instruction signal is received from the signal line 112a-
Read start address supplied via 2048
" is selected and held. When the countdown circuit 1108a receives the address creation instruction signal supplied via the signal line 1201a, the total number of elements of the block data" 1024
The countdown starts from ''', and from then on, the signal line 13
The countdown is continued by the address update instruction signal supplied via 10a.

The count value is sent from signal line 1308a.

The count value check circuit 1110a is connected to the signal line 1201a.
In response to the address creation instruction signal supplied via the signal line 1308a, the address update instruction signal is sent out from the signal line 1310a until the count value reaches 'O'. The address generation circuit 1106a adds "1" to the address supplied from the signal line 131a-2 to create a read address for the next element, and sends it out from the signal line 1306a. The register 1102a selects and holds the address supplied via the signal line 1306a every time the address update instruction signal is supplied via the signal line 1310a, and sends it from the signal line 1302a. The request control circuit 1100a is supplied with a data write request code for the shared memory 10a via the signal 1!1lla-1 in synchronization with the timing at which read data from the dedicated memory 12a is sent by shared memory data transfer. It is sent from the signal line 135a-2 as a write request code for the
A request valid signal is sent from 5a-. register 1101
a is supplied with and holds the start address path O" for writing block data via the signal 11111a-2, and is connected to the signal line 13.
The address is sent from 5a-3. Further, the request control circuit 1100a is supplied with a request to read the shared memory transfer data from the dedicated memory 12a via the signal line 112a-1, and at the same time is supplied with a vector store request via the signal line 114a-1. Upon receiving the request, the request decoding control circuit 100a sends an instruction signal to take in the first address to access the dedicated memory 12a from the signal line 1202a. register 1
103a is a dedicated memory 12 when processing a vector store request.
a Register that selects and holds the access address and connects signal line 1
When receiving the start address capture instruction signal via the signal line 114a-2, it selects and holds the start address "'2176" of the vector store supplied via the signal line 114a-2. When the register 1104a receives the start address capture instruction signal via the signal line 1202a, the register 1104a receives the inter-element distance "'1" of the vector store request supplied via the signal line 114a-3.
is set and held. Register 1105a receives signal H
, 1202a, the vector store element number "128" supplied via the signal line 114a-4 is set and held. The comparison circuit 1112a receives the read address from the dedicated memory 12a by shared memory data transfer supplied from the signal line 1302a, and the signal &! A circuit that detects a match between access addresses of the dedicated memory 12a by the vector store supplied from the vector store 132a-2 sends an address match signal to the signal line 1312 when the address matches at address 2176.
Send from a. When the count town circuit 1109a receives the address match signal via the signal line 1312-a, the count town circuit 1109a counts the number of elements "12" supplied via the signal II 1305a.
8" and starts the countdown. After that, the countdown is continued by the address update instruction signal via the signal line 1311a. The count value is sent from the signal line 1309a. The count value check circuit 1111a via the signal line 1312a. In response to the supplied address match signal, the count value supplied via the signal line 1309a is checked, and the signal line 1 is turned on until the count value reaches PaO''.
311a sends out an address update instruction signal.

The address generating circuit 1107a receives the address supplied via the signal line 132a2 and the inter-element pressure Il! supplied via the signal line 1304a! ``1'' is added to create a write address for the next element and sent from the signal line 1307a. The register 1103a updates the signal line 1307 every time an address update instruction signal is supplied via the signal line 1311a.
Select and hold the address supplied via signal line 1
32a-2. The above comparison circuit 1112a performs 1 from address 2304 after the address match at address 2176.
Every time the addresses match 28 times, an address match signal is sent. The switching control flag register 1113a is connected to the signal line 13
The logical value ``1'' is set by the address match signal supplied via the processor 12a, and while the logic value ``1'' is set, the vector store data from the processor 15a is stored in the shared memory 1.
A data switching control signal for controlling data switching to be transferred to 0a is sent from the signal line 1313a. The switching control flag register 1113a is a count value check circuit 1111 after data switching control based on 128 address matches.
a detects the count value "O" and connects the signal line 1311a.
When the address update instruction signal is no longer supplied, “O”
will be reset to The request sending circuit 1114a is connected to the signal line 1
A request sending circuit 1115a receives an address update instruction signal supplied via the signal line 1310a and sends out a read request signal for the dedicated memory 12a from the signal line 131a-1. In response, a write request signal to the dedicated memory 12a is sent from the signal line 132a-1. The data switching circuit 1116a is a circuit that controls switching of write and read data between the dedicated memory 12a, the shared memory 10a, and the processor 15a, and when a shared memory data write request signal is supplied from the signal line 135a-2, the signal line The data read from the dedicated memory 12a supplied via the signal line 134a is sent as shared memory write data via the signal line 136a.At this time, when a data switching control signal is supplied via the signal R1313a, the data is sent via the signal line 138a. The selected vector store data is sent as shared memory write data from the signal line 136a. Since the write request signal to the dedicated memory 12a due to the vector store request is supplied from the signal line 131a-1 through the signal line 131a-1, the vector store data, which is also supplied from the signal line 133a through the signal line 138a, is sent to the dedicated memory 12a. do.

〔Effect of the invention〕

As explained above, the present invention allows block data to be transferred from the shared memory to the dedicated memory in a shared memory data transfer request to include vector data to be loaded from the dedicated memory to the processor in a subsequent vector load request. By directly transferring the data being detected and transferred from the shared memory to the dedicated memory to the processor, vector load request processing can be speeded up, and the throughput of the system can also be increased.

Furthermore, the present invention detects that vector data to be stored from the processor to the dedicated memory in a vector store request is included in block data to be transferred from the dedicated memory to the shared memory in a subsequent shared memory data transfer request. By directly transferring the vector data stored in the dedicated memory to the shared memory, the shared memory data transfer process can be speeded up, and the throughput of the system can also be increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a memory access control device according to an embodiment of the present invention, FIG. 2 is a diagram showing an image of shared memory data transfer and vector loading, and FIG. 3 shows the data check circuit B14 in FIG. 1. 4 is a block diagram showing the transfer control circuit 13 in FIG. 1, FIG. 5 is a block diagram showing a memory access control device according to another embodiment of the present invention, and FIG. 6 is shared with the vector store. FIG. 7 is a block diagram showing the data check circuit 14 in FIG. 5, and FIG. 8 is a block diagram showing the transfer control circuit 13 in FIG. 5. 10.10a--shared memory, 11. lla, 21.
21a...Request reception control circuit, 12.12a. 22.22a... Dedicated memory, 13.13a, 23.
23a...Transfer control circuit, 14.14a, 24.24
a...Data check circuit, 15.15a, 25.2
5a-processor, 180-183.180a-18
3a-Register, 184, 184a, 185.185a
. . . Address calculation circuit, 186.186a . . . Distance check circuit, 187° 187a . . . Address check circuit, 1100. 1100a...Request decoding control circuit, 1101-1105.1101a-1105a...
・Register, 1106.1106a, 1107, 110
7a...address generation circuit, 1108.1108a,
1109°1109a...Countdown circuit, 11
10, 1110a, 1111, 1lla - Count value check circuit, 1112.1112a... Comparison circuit, 1113... Switching control flag register, 1113a
... Valid flag register, 1114.1115.11
15a...Request sending circuit, 1114a...Dedicated memory address selection circuit, 1116.1116a...Data switching circuit.

Claims (1)

[Claims] 1. A memory access control device that controls data transfer between a plurality of processors, at least one dedicated memory corresponding to each of the plurality of processors, and a shared memory shared among the plurality of processors. A memory access control device characterized in that it has means for transferring data from the shared memory to the dedicated memory and also transferring part or all of the data from the shared memory to the processor corresponding to the dedicated memory. 2. A memory access control device that controls data transfer between a plurality of processors, at least one dedicated memory corresponding to each of the plurality of processors, and a shared memory shared among the plurality of processors, wherein A memory access control device comprising means for transferring data to a dedicated memory corresponding to a processor and transferring the data to the shared memory.