JPS63316574A - Video signal synthesizer - Google Patents

Video signal synthesizer

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Publication number
JPS63316574A
JPS63316574A JP62152184A JP15218487A JPS63316574A JP S63316574 A JPS63316574 A JP S63316574A JP 62152184 A JP62152184 A JP 62152184A JP 15218487 A JP15218487 A JP 15218487A JP S63316574 A JPS63316574 A JP S63316574A
Authority
JP
Japan
Prior art keywords
circuit
signal
video
delay
key signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62152184A
Other languages
Japanese (ja)
Inventor
Hiroyasu Tagami
田上 博康
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62152184A priority Critical patent/JPS63316574A/en
Publication of JPS63316574A publication Critical patent/JPS63316574A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To remove a field delay difference and to attain smooth image movement by adding a variable delay circuit to a digital video specific effect(DVE) generator, a video synthesizing circuit, a key signal generating circuit and a control circuit for managing size processing. CONSTITUTION:The DVE generator 5 executes size processing based on a key signal or a signal outputted from a control circuit 7 and a signal to which a contraction effect is added is supplied to the video synthesizing circuit 4. The circuit 4 synthesizes plural video signals based on a key signal obtained through a variable delay circuit 8 and supplies the synthesized signal to an output terminal 3. The delay circuit 8 can vary a delay variable in each field to absorb the delay of the DVE generator 5 in each field. Since a field delay difference is removed, a gap based upon a response time difference is removed and a smooth image movement can be attained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はテレビジョン伝送装置に関し、特に映像信号を
合成するための映像合成装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a television transmission device, and particularly to a video synthesis device for synthesizing video signals.

〔従来の技術〕[Conventional technology]

従来の映像合成装置を第3図に示す。 A conventional video compositing device is shown in FIG.

図において、入力端子11.12に入力映像信号が供給
される。前記入力映像信号はデジタル特殊効果発生装置
(以下、DVE装置という)15及び映像合成回路14
へ供給される。映像合成回路14の他に、サイズ処理を
管理する制御回路17と、その制御信号を受け、キー信
号を発生させるキー信号発生回路16と、前記キー信号
又は前記制御回路17からの制御信号でサイズが決定す
るDVE装@15がある。
In the figure, input video signals are supplied to input terminals 11 and 12. The input video signal is sent to a digital special effect generator (hereinafter referred to as a DVE device) 15 and a video synthesis circuit 14.
supplied to In addition to the video synthesis circuit 14, there is a control circuit 17 that manages size processing, a key signal generation circuit 16 that receives the control signal and generates a key signal, and a control circuit 16 that generates a size using the key signal or the control signal from the control circuit 17. There is a DVE equipment @15 determined by

サイズ処理され、縮小効果のかかった出力映像信号は、
映像合成回路14に供給される。映像合成回路14では
キー信号発生回路16からのキー信号により、複数の映
像を合成し、出力端子13へ供給する。
The output video signal that has undergone size processing and reduction effects is
The signal is supplied to the video synthesis circuit 14. The video synthesis circuit 14 synthesizes a plurality of videos using the key signal from the key signal generation circuit 16 and supplies the synthesized video to the output terminal 13.

第4図にこの効果例を示す。Figure 4 shows an example of this effect.

制御回路よりキー信号発生回路ではワイプ信号Cが発生
している。DVE装置15はb信号が入力され、前記ワ
イプ信号Cにより、dのような縮小効果を行っている。
A wipe signal C is generated in the key signal generation circuit from the control circuit. The DVE device 15 receives the b signal and uses the wipe signal C to perform a reduction effect as shown in d.

映像合成回路14では、aとbの図をCの図のワイプ信
号で合成し、eの図を得る。
The video synthesis circuit 14 combines figures a and b with the wipe signal of figure C to obtain figure e.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、制御回路17よりワイプの波形を動かした場合
、DVE装置15ではCの図に連動してdの図のサイズ
が決定されるため、DVE装置15の処理時間によるフ
ィールド遅延が生ずる。このdの図の信号を、映像合成
回路14にてCの図の信号で合成すると、フィールド遅
延差があるため、eの図のように応答時間差によるスキ
マが出る欠点があった。
However, when the wipe waveform is moved by the control circuit 17, the size of the diagram d is determined in conjunction with the diagram C in the DVE device 15, so a field delay occurs due to the processing time of the DVE device 15. When the signal shown in Fig. d is combined with the signal shown in Fig. C in the video synthesis circuit 14, there is a difference in field delay, so there is a drawback that a gap occurs due to the difference in response time as shown in Fig. e.

本発明の目的は前記問題点を解決した映像信号合成装置
を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a video signal synthesis device that solves the above-mentioned problems.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は複数の映像信号を合成する映像信号合成装置に
おいて、サイズ処理を管理する制御回路と、前記制御回
路からの制御情報で動作するキー信号発生回路と、映像
信号を入力し前記キー信号発生回路からのキー信号又は
前記制御回路からのサイズ制御信号で映像信号のサイズ
が決定するデジタル特殊効果発生装置と、前記キー信号
発生回路の出力を受け、前記制御回路からの制御信号で
制御される可変遅延回路と、前記デジタル特殊効果発生
装置の出力信号及び他の映像信号を入力とし、前記遅延
回路からのキー信号により映像信号を合成する映像合成
回路とを有することを特徴とする映像信号合成装置であ
る。
The present invention provides a video signal synthesis device for synthesizing a plurality of video signals, including a control circuit that manages size processing, a key signal generation circuit that operates based on control information from the control circuit, and a video signal input circuit that generates the key signal. a digital special effect generating device in which the size of a video signal is determined by a key signal from a circuit or a size control signal from the control circuit; and a digital special effect generating device that receives an output from the key signal generating circuit and is controlled by a control signal from the control circuit. A video signal synthesis circuit comprising: a variable delay circuit; and a video synthesis circuit that receives the output signal of the digital special effect generator and other video signals as input, and synthesizes a video signal using a key signal from the delay circuit. It is a device.

〔実施例〕〔Example〕

以下、本発明の一実施例を図により説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

第1図において、本発明はサイズ処理管理する制御回路
7と、その出力の制御信号で動作するキー信号発生回路
6と、映像信号を入力し、キー信号発生回路6からのキ
ー信号又は前記制御回路7からのサイズ制御信号でサイ
ズが決定するDVE装置5と、前記キー信号を受け、前
記制御回路7からの制御信号で制御され、前記DVE装
置5のフィールド遅延を吸収するための可変遅延回路8
と、前記DYE装置5の出力信号と他の映像信号を前記
キー信号により合成する映像合成回路4を備えている。
In FIG. 1, the present invention includes a control circuit 7 that manages size processing, a key signal generation circuit 6 that operates based on the control signal output from the control circuit 7, and a key signal generation circuit 6 that inputs a video signal and receives the key signal from the key signal generation circuit 6 or the control a DVE device 5 whose size is determined by a size control signal from a circuit 7; and a variable delay circuit that receives the key signal, is controlled by a control signal from the control circuit 7, and absorbs the field delay of the DVE device 5. 8
and a video synthesis circuit 4 for synthesizing the output signal of the DYE device 5 and other video signals using the key signal.

図において、入力端子1.2に入力映像信号が供給され
る。前記入力映像信号はDVE装置5及び映像合成回路
4へ供給される。サイズ処理を管理する制御回路7とそ
の制御信号を受け、キー信号を発生させるキー信号発生
回路6と、前記キー信号又は前記制御回路7からの制御
信号でサイズが決定するDVE装M5がある。サイズ処
理され、縮小効果のかかった出力映像信号は、映像合成
回路4に供給される。映像合成回路4では、キー信号発
生回路6から可変遅延回路8を経たキー信号により、複
数の映像を合成し、出力端子3へ供給する。
In the figure, an input video signal is supplied to input terminal 1.2. The input video signal is supplied to the DVE device 5 and the video synthesis circuit 4. There is a control circuit 7 that manages size processing, a key signal generation circuit 6 that receives the control signal and generates a key signal, and a DVE device M5 whose size is determined by the key signal or the control signal from the control circuit 7. The size-processed and reduced output video signal is supplied to the video synthesis circuit 4. The video synthesis circuit 4 synthesizes a plurality of videos using a key signal passed from the key signal generation circuit 6 through the variable delay circuit 8, and supplies the synthesized video to the output terminal 3.

ここで、前記可変遅延回路8は、DVE装置5でのフィ
ールド単位での遅延分を吸収するためのもので、フィー
ルド単位に遅延量を可変できるものである。
Here, the variable delay circuit 8 is for absorbing the delay in units of fields in the DVE device 5, and can vary the amount of delay in units of fields.

第2図にこの画面効果例を示す。Figure 2 shows an example of this screen effect.

制御回路7によりキー信号発生回路6では、ワイプ信号
Cが発生している。DVE装置5はb信号を入力し、前
記ワイプ信号Cによりdの図のような縮小効果を行って
いる。映像合成回路4では、aの図とbの図をワイプ信
号Cで合成し、eの図を得る。ここで、eの図の合成画
面を得る場合、bの図はDVE装置5によりフィールド
遅延しているため、Cの図に可変遅延回路8によりフィ
ールド遅延させることにより、bの図とCの図が同位相
となる。これにより、制御回路7により、ワイプ信号を
動かした場合にも、eの図は応答時間差のないスムーズ
な動きが実現できる。
A wipe signal C is generated in the key signal generation circuit 6 by the control circuit 7. The DVE device 5 inputs the b signal, and uses the wipe signal C to perform a reduction effect as shown in the diagram d. The video synthesis circuit 4 combines the diagram a and the diagram b using the wipe signal C to obtain the diagram e. Here, when obtaining the composite screen of figure e, since figure b has been field delayed by the DVE device 5, by field delaying figure C by variable delay circuit 8, figure b and figure C can be obtained. are in phase. Thereby, even when the wipe signal is moved by the control circuit 7, smooth movement without any difference in response time can be realized as shown in the figure e.

本実施例では、ワイプ信号を例に述べたが、あらゆる種
類のキー信号にも同様に実現でき、かつDYE装置が装
置によってフィールド遅延が異なる場合には、可変遅延
回路により調整することが可能である。
In this embodiment, a wipe signal is used as an example, but it can be similarly implemented for all types of key signals, and if the field delay of the DYE device differs depending on the device, it can be adjusted using a variable delay circuit. be.

〔発明の効果〕 以上説明したように本発明によれば、フィールド遅延差
をなくしたため、応答時間差によるスキマをなくしスム
ーズな画像の動きを実現できる効果を有するものである
[Effects of the Invention] As described above, according to the present invention, since field delay differences are eliminated, gaps due to response time differences can be eliminated and smooth image motion can be realized.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の映像合成装置の回路図、第2図は本発
明の画面効果例を示す図、第3図は従来の映像合成装置
の回路図、第4図は従来の画面効果例を示す図である。 】、2・・・映像入力端子  3・・・映像出力端子4
・・・映像合成回路   5・・・DVE (デジタル
特殊効果発生装置)6・・キー信号発生回路 7・・・
制御回路8・・・可変遅延回路
Fig. 1 is a circuit diagram of a video synthesis device of the present invention, Fig. 2 is a diagram showing an example of a screen effect of the present invention, Fig. 3 is a circuit diagram of a conventional video synthesis device, and Fig. 4 is an example of a conventional screen effect. FIG. ], 2...Video input terminal 3...Video output terminal 4
...Video synthesis circuit 5...DVE (digital special effect generator) 6...Key signal generation circuit 7...
Control circuit 8...variable delay circuit

Claims (1)

【特許請求の範囲】[Claims] (1)複数の映像信号を合成する映像信号合成装置にお
いて、サイズ処理を管理する制御回路と、前記制御回路
からの制御情報で動作するキー信号発生回路と、映像信
号を入力し前記キー信号発生回路からのキー信号又は前
記制御回路からのサイズ制御信号で映像信号のサイズが
決定するデジタル特殊効果発生装置と、前記キー信号発
生回路の出力を受け、前記制御回路からの制御信号で制
御される可変遅延回路と、前記デジタル特殊効果発生装
置の出力信号及び他の映像信号を入力とし、前記遅延回
路からのキー信号により映像信号を合成する映像合成回
路とを有することを特徴とする映像信号合成装置。
(1) A video signal synthesis device that synthesizes multiple video signals, including a control circuit that manages size processing, a key signal generation circuit that operates based on control information from the control circuit, and a video signal input and generation of the key signal. a digital special effect generating device in which the size of a video signal is determined by a key signal from a circuit or a size control signal from the control circuit; and a digital special effect generating device that receives an output from the key signal generating circuit and is controlled by a control signal from the control circuit. A video signal synthesis circuit comprising: a variable delay circuit; and a video synthesis circuit that receives the output signal of the digital special effect generator and other video signals as input, and synthesizes a video signal using a key signal from the delay circuit. Device.
JP62152184A 1987-06-18 1987-06-18 Video signal synthesizer Pending JPS63316574A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62152184A JPS63316574A (en) 1987-06-18 1987-06-18 Video signal synthesizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62152184A JPS63316574A (en) 1987-06-18 1987-06-18 Video signal synthesizer

Publications (1)

Publication Number Publication Date
JPS63316574A true JPS63316574A (en) 1988-12-23

Family

ID=15534892

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62152184A Pending JPS63316574A (en) 1987-06-18 1987-06-18 Video signal synthesizer

Country Status (1)

Country Link
JP (1) JPS63316574A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04167773A (en) * 1990-10-30 1992-06-15 Nec Corp Super signal generator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04167773A (en) * 1990-10-30 1992-06-15 Nec Corp Super signal generator

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