JPS63316510A - Boosting circuit - Google Patents
Boosting circuitInfo
- Publication number
- JPS63316510A JPS63316510A JP62152562A JP15256287A JPS63316510A JP S63316510 A JPS63316510 A JP S63316510A JP 62152562 A JP62152562 A JP 62152562A JP 15256287 A JP15256287 A JP 15256287A JP S63316510 A JPS63316510 A JP S63316510A
- Authority
- JP
- Japan
- Prior art keywords
- fet
- conductivity type
- voltage
- channel
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 18
- 230000005669 field effect Effects 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 10
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 9
- 230000000087 stabilizing effect Effects 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Dc-Dc Converters (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は昇圧回路に関し、特にＩＧ−ＦＥＴを利用し、
与えられる電源電圧よりも高い電圧出力を効率的に得る
ことを図った昇圧回路に関する。[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a booster circuit, in particular, a booster circuit that uses an IG-FET,
The present invention relates to a booster circuit that aims to efficiently obtain a voltage output higher than a given power supply voltage.
従来、この種のＩＧ−ＦＥＴでｉｖｉされた昇圧回路の
１つの第３図に示す昇圧回路がある。この種の昇圧回路
は、クロック入力端子６．７から入力するクロックφ、
「で駆動し昇圧回路が動作する２この昇圧回路の■Ｇ−
ＦＥＴ ＴＤｏ〜ＴＤｎはダイオード接続されている為
、逆流することはなくクロック半サイクルごとに電荷が
吹成と後段に伝達されていき、出力端子８に付加された
出力電圧安定化用コンデンサＣＬが充電され、第２の電
源端子５から入力した電圧Ｖ１が最終的には（１）弐Ｖ
ｏ：出力端子８の出力電圧
Ｖｌ ：第２の電源端子の入力電圧
ＶＴ：バックゲート効果を含んだＴＤｏ〜ＴＤｎのしき
い値電圧
Ｎ ：ＩＧ−ＦＥＴとコンデンサで構成された回路の
段数
■ｌ：クロツクφ、Ｔの出力振幅電圧
■ｏ ：出力端子８から流れる負荷電流ｆ ：クロック
周波数
〔発明が解決しようとする問題点〕
上述した従来の昇圧回路では、（１）式のカッコ内にバ
ックゲート効果を含んだＴＤｏ〜ＴＤｎのしきい値電圧
７丁の項があり、このＶＴは製造条件に依存し、出力電
圧はわずかなＶＴの変動でもＮ倍されて大きく変動する
という欠点がある。さらにこのＶＴの項がある為にクロ
ック入力の出力振幅電圧Ｖβの値を小さくできないとい
う欠点がある。Conventionally, there is a booster circuit shown in FIG. 3, which is one of the booster circuits that are ivized using this type of IG-FET. This type of booster circuit has a clock φ input from the clock input terminal 6.7,
2 The booster circuit operates by driving with
Since FETs TDo to TDn are diode-connected, there is no reverse flow, and the charge is blown and transmitted to the subsequent stage every half cycle of the clock, and the output voltage stabilizing capacitor CL attached to the output terminal 8 is charged. The voltage V1 input from the second power supply terminal 5 is finally (1)2V
o: Output voltage Vl of output terminal 8: Input voltage of second power supply terminal VT: Threshold voltage of TDo to TDn including back gate effect N: Number of stages of the circuit composed of IG-FET and capacitor ■l : Output amplitude voltage of clock φ, T ■o : Load current f flowing from output terminal 8 : Clock frequency [Problem to be solved by the invention] In the above-mentioned conventional booster circuit, the equation (1) has a back value in parentheses. There are seven threshold voltage terms, TDo to TDn, including gate effects, and this VT depends on manufacturing conditions, and even a slight variation in VT causes the output voltage to vary greatly by a factor of N, which is a drawback. Furthermore, because of this VT term, there is a drawback that the value of the output amplitude voltage Vβ of the clock input cannot be reduced.
また、（１）式のＶｌはバックゲート効果を含んでおり
、Ｖｏが（２）式の条件になると出力電圧Ｖ。はそれ以
上昇圧されないことを示している。Further, Vl in equation (1) includes a back gate effect, and when Vo meets the condition of equation (2), the output voltage V. indicates that the voltage will not be boosted any further.
■
ＶＴ＞Ｖφ−「ト ・・・・・・（２）し
たがって、従来の昇圧回路では入力する電源電圧が低く
なると昇圧可能な電圧が著しく低くなるという欠点があ
る。(2) Therefore, the conventional booster circuit has the disadvantage that when the input power supply voltage becomes low, the voltage that can be boosted becomes significantly lower.
本発明の目的は上述した欠点を除去し、製造条件の影響
やバックゲート効果の影響を排除して低電圧電源からの
効果的昇圧が可能な昇圧回路を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks, and to provide a booster circuit that can effectively boost voltage from a low voltage power supply by eliminating the influence of manufacturing conditions and the back gate effect.
本発明の昇圧回路は、ＩＧ−ＦＥＴで構成される集積回
路の第１の導電型の第１のＩＧ−ＦＥＴのドレインと第
２の導電型の第２のＩＧ、ＦＥＴのドレインとコンデン
サの一方の端子とを接続し前記第２の導電型の第２のＩ
Ｇ−ＦＥＴのソースと第１の電源のグランドとを接続し
、前記第２の導電型の第２のＩＧ−ＦＥＴとしきい値が
異なる第２の導電型の第３のＩＧ−ＦＥＴのソースと第
２の入力電源とを接続し、前記第１の導電型の第１のＩ
Ｇ−ＦＥＴのゲートと前記第２の導電型の第２のＩＧ−
ＦＥＴのゲートと前記第２の導電型の第３のＩＧ−ＦＥ
Ｔのゲートとクロック入力端子とを接続したうえ、前記
コンデンサの他方端子と前記第２の導電型の第３のＩＧ
−ＦＥＴのドレインとを接続してこれを出力としかつ前
記第１の導電型の第１のＩＧ−ＦＥＴのソースを入力と
する昇圧回路ブロックをＮ（Ｎ＝２．３・・・・・・）
段直列に接続して構成される。The booster circuit of the present invention includes a drain of a first IG-FET of a first conductivity type, a second IG of a second conductivity type, and one of the drain of the FET and a capacitor of an integrated circuit configured of IG-FETs. and the second I of the second conductivity type.
The source of the G-FET is connected to the ground of the first power supply, and the source of a third IG-FET of a second conductivity type having a different threshold value from that of the second IG-FET of the second conductivity type. a second input power source, and a first I of the first conductivity type.
the gate of the G-FET and the second IG- of the second conductivity type.
the gate of the FET and the third IG-FE of the second conductivity type
The gate of T and the clock input terminal are connected, and the other terminal of the capacitor and the third IG of the second conductivity type are connected.
-N (N=2.3... )
Consists of stages connected in series.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例の回路図である。FIG. 1 is a circuit diagram of a first embodiment of the present invention.
Ｎ段の昇圧回路ブロック１０−１〜１０−Ｎから成り、
昇圧回路ブロック１０−１を例として説明すると、Ｐチ
ャンネルのエンハンスメント形ＩＧ・ＦＥＴのＴＡｌの
ドレインとＮチャンネルのエンハンスメント形ｌ０−Ｆ
ＥＴのＴＢｌのドレインと昇圧用コンデンサとを接続し
、Ｎチャンネルのエンハンスメント形ＩＧ、ＦＥＴのＴ
Ｂｌのソースと第１の電源端子３とを接続し、Ｎチャン
ネルのデプレッション形ＩＧ−ＦＥＴのＴ。１のソース
と第２の電源端子２とを接続し、Ｐチャンネルのエンハ
ンスメント形ＩＧ−ＦＥＴのゲートとＮチャンネルのエ
ンハンスメント形ＩＧ−ＦＥＴのＴＢｌのゲートとＮチ
ャンネルのデプレッション形ＩＧ・ＦＥＴのＴｃ１のゲ
ートとクロック入力端子１とを接続し、昇圧用コンデン
サＣ１の他の端子とＮチャンネルのデプレッション形Ｉ
Ｇ、ＦＥＴのＴｃ１のドレインとを接続してこれを出力
とし、かつＴＡｌのソースを入力したものを１つの回路
ブロックとし、この回路ブロックをＮ段直列に接続し、
１段目の昇圧回路ブロック１０−１の入力１１と第２の
電源端子２とを接続し、以下Ｎ段の昇圧ブロックを吹成
に直列に接続したあとＮ段目の昇圧６一
回路ブロック１０−Ｎの出力ＯｎとダイオードＤ１のア
ノードとを接続し、ダイオードＤ１のカソードと出力電
圧安定化用コンデンサＣＬと出力端子４とを接続し、ク
ロック入力端子１にはクロック入力、第２の電源端子２
には入力電源を、さらに第１の電源端子３はグランドに
接続した回路で構成される。Consisting of N stage booster circuit blocks 10-1 to 10-N,
Taking the booster circuit block 10-1 as an example, the drain of P-channel enhancement type IG FET TAL and the N-channel enhancement type l0-F
Connect the drain of TBl of ET and the boost capacitor, and connect the N-channel enhancement type IG and T of FET.
The source of Bl and the first power supply terminal 3 are connected to T of an N-channel depression type IG-FET. 1 and the second power supply terminal 2, and connect the gate of the P-channel enhancement type IG-FET, the gate of TB1 of the N-channel enhancement type IG-FET, and the Tc1 of the N-channel depletion type IG-FET. The gate and clock input terminal 1 are connected, and the other terminal of the boost capacitor C1 and the N-channel depletion type I
G, the drain of FET Tc1 is connected to output this, and the source of TAL is inputted as one circuit block, and this circuit block is connected in series in N stages,
The input 11 of the first stage booster circuit block 10-1 and the second power supply terminal 2 are connected, and after the N stage booster blocks are connected in series to the blower, the Nth stage booster 6-circuit block 10 is connected. -N output On is connected to the anode of the diode D1, the cathode of the diode D1 is connected to the output voltage stabilizing capacitor CL, and the output terminal 4 is connected to the clock input terminal 1, and the second power supply terminal is connected to the clock input terminal 1. 2
The input power supply is connected to the input power supply terminal 3, and the first power supply terminal 3 is connected to the ground.
本実施例の昇圧回路の場合、クロック人力ＣＫのＬレベ
ルが第１の電源電位（ＯＶ）、Ｈレベルが第２の電源電
位（Ｖｌ ）で駆動されているとすると、タロツク人力
ＣＫがＨレベルの時、Ｎチャンネルのエンハンスメント
形ＩＧ−ＦＥＴのＴＢ１〜ＴＢｎ、及びＮチャンネルの
デプレッション形■Ｇ・ＦＥＴのＴ。１〜Ｔｏｎがオン
、Ｐチャンネルのエンハンスメント形ＩＧ−ＦＥＴのＴ
Ａ１〜ＴＡｆｌがオフとなり、昇圧用コンデンサＣ１〜
Ｃｎを充電する。In the case of the booster circuit of this embodiment, assuming that the L level of the clock manual power CK is driven by the first power supply potential (OV) and the H level is driven by the second power supply potential (Vl), the clock manual power CK is driven by the H level. When , TB1 to TBn of the N-channel enhancement type IG-FET and T of the N-channel depression type ■G-FET. 1~Ton is on, T of P channel enhancement type IG-FET
A1~TAfl is turned off, and the boost capacitor C1~
Charge Cn.
次にクロック入力ＣＫがＬレベルになると、Ｎチャンネ
ルのエンハンスメント形ＩＧ−ＦＥＴのＴＢＩ〜ＴＢｎ
及びＮチャンネルのデプレッション形■Ｇ・ＦＥＴの’
ｐｃ、−’ｒｃｎがオフ、Ｐチャンネルのエンハンスメ
ント形ＩＧ−ＦＥＴのＴＡ１〜ＴＡｌｌがオンとなり、
充電された昇圧用コンデンサＣ１〜Ｃｎが直列に接続さ
れた状態となる。Next, when the clock input CK goes to L level, the N-channel enhancement type IG-FETs TBI to TBn
and N-channel depression type G FET'
pc, -'rcn are off, P-channel enhancement type IG-FETs TA1 to TAll are on,
The charged boost capacitors C1 to Cn are connected in series.
したがって、出力端子４に出力される電圧は次Ｖｏ：出
力端子４の出力電圧
■、：第２の電源端子２の入力電圧
Ｎ ：昇圧回路ブロックの段数
■。：昇圧用コンデンサＣ，〜Ｃｎを充電した時のコン
デンサの両端の電
位差
■ｏ：出力端子８から流れる負荷電流
ａ ：クロックのデユーティ−比などで決まる係数
ｆ ：クロック周波数
Ｃ：昇圧用コンデンサＣ１〜Ｃｎの容
量値
■Ｄ：ダイオードの順方向電圧
上述した（３）式から明らかな如く、ｌｏ−ＦＥＴのし
きい値ＶＴの項を含まないため製造条件の影響やバック
ゲート効果による影響を受けず低電圧電源からの昇圧も
可能となる。Therefore, the voltage output to the output terminal 4 is as follows: Vo: the output voltage of the output terminal 4 (■): input voltage of the second power supply terminal 2 N: the number of stages of the booster circuit block (■). : Potential difference across the capacitors when charging the boost capacitors C, ~Cn o: Load current a flowing from the output terminal 8 : Coefficient f determined by clock duty ratio, etc. : Clock frequency C: Boost capacitor C1 ~ Capacitance value of Cn ■D: Forward voltage of diode As is clear from equation (3) above, it does not include the term of the lo-FET threshold VT, so it is not affected by manufacturing conditions or the back gate effect. It also becomes possible to boost the voltage from a low-voltage power supply.
第２図は第１図の実施例の出力波形の電圧／時間特性図
であり、第４図は第３図の従来の昇圧回路の出力波形の
電圧／時間特性図である。第４図の場合に比し、第３図
の特性では昇圧回路ブロックの段数に対応して出力電圧
が逐次増大していき、これに対応する出力が得られるの
に比し、第４図の場合は昇圧可能な電圧が制限される状
況を示している。なお、第４図の場合は出力電圧の変動
の可能性が高いことも前述したとおりである。2 is a voltage/time characteristic diagram of the output waveform of the embodiment of FIG. 1, and FIG. 4 is a voltage/time characteristic diagram of the output waveform of the conventional booster circuit of FIG. 3. Compared to the case shown in Fig. 4, in the characteristic shown in Fig. 3, the output voltage increases successively in accordance with the number of stages of the booster circuit block, and a corresponding output is obtained. This indicates a situation where the voltage that can be boosted is limited. In addition, as mentioned above, in the case of FIG. 4, there is a high possibility that the output voltage will fluctuate.
第５図は本発明の第２の実施例を示す回路図であり、第
１図の実施例の各ＩＧ−ＦＥＴのＰチャンネルとＮチャ
ンネルを入れ替えた状態として構成され、従ってこれら
ＩＧ−ＦＥＴの動作のオン。FIG. 5 is a circuit diagram showing a second embodiment of the present invention, in which the P channel and N channel of each IG-FET in the embodiment of FIG. Operation on.
オフ状態が第１図の場合と逆になるほかは、基本−９＝ 的にはほぼ同一の機能を提供するものである。Basically -9 = except that the off state is the opposite of that in Figure 1. In general, they provide almost the same functionality.
以上説明したように本発明によれば、ＩＧ−ＦＥＴのし
きい値による影響を排除した昇圧回路構成とすることに
より、ＩＧ−ＦＥＴの製造条件の影響やバックゲート効
果による影響を受けず、低電圧電源からの昇圧が可能と
なる昇圧回路が実現できるという効果がある。As explained above, according to the present invention, by creating a booster circuit configuration that eliminates the influence of the threshold value of the IG-FET, it is not influenced by the manufacturing conditions of the IG-FET or the back gate effect, and has a low This has the effect of realizing a booster circuit that can boost the voltage from a voltage power source.
第１図は本発明の第１の実施例の回路図、第２図は第１
図の実施例の出力波形の電圧／時間特性図、第３図は従
来の昇圧回路の例を示す回路図、第４図は第３図に示す
昇圧回路の出力波形の電圧／時間特性図、第５図は本発
明の第２の実施例を示す回路図である。
１・・・クロック入力端子、２．５・・・第２の電源端
子、３・・・第１の電源端子、４．８・・・出力端子、
６゜７・・・クロック入力端子、１０−１〜１０−Ｎ、
２０−１〜２０−Ｎ・・・昇圧回路ブロック、ｉ、〜ｉ
ｎ・・・昇圧回路ブロック入力、０〜Ｏｎ・・・昇圧回
路ブロック出力、ＴＡＩ〜ＴＡｎ、 ＴＥ、〜’ｒＥｎ
−・−Ｐチャンネルのエンハンスメント形ＩＧ−ＦＥＴ
、ＴＢｌ〜ＴＢ！、、 Ｔ、、〜ＴＦｎ・・・Ｎチャン
ネルのエンハンスメン）、形Ｉ Ｇ−Ｆ、Ｅ Ｔ 、Ｔ
ｃ＋〜Ｔｃｆｌ−Ｎチャンネルのデプレッション形Ｉ
Ｇ−Ｆ ＥＴ、 Ｔｏｏ〜Ｔｇｎ−Ｉ Ｇ−Ｆ Ｅ Ｔ
、ＴＧ、〜ＴＧｎ”’ Ｐチャンネルのデプレッショ
ン形ＩＧ−ＦＥＴ、ｃｌ〜Ｃｎ・・・昇圧用コンデンサ
、ＣＬ・・・出力電圧安定化用コンデンサ、Ｄ＋・・・
ダイオード。
−１１デ＼FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG. 2 is a circuit diagram of a first embodiment of the present invention.
3 is a circuit diagram showing an example of a conventional booster circuit; FIG. 4 is a voltage/time characteristic diagram of the output waveform of the booster circuit shown in FIG. 3; FIG. 5 is a circuit diagram showing a second embodiment of the present invention. 1... Clock input terminal, 2.5... Second power supply terminal, 3... First power supply terminal, 4.8... Output terminal,
6゜7...Clock input terminal, 10-1 to 10-N,
20-1 to 20-N...boost circuit block, i, ~i
n... Boost circuit block input, 0~On... Boost circuit block output, TAI~TAn, TE, ~'rEn
-・-P channel enhancement type IG-FET
, TBL~TB! ,, T, , ~TFn... N channel enhancement member), form I G-F, E T , T
c+~Tcfl-N channel depression form I
G-FET, Too~Tgn-I G-FET
, TG, ~TGn"' P-channel depression type IG-FET, cl~Cn...boosting capacitor, CL...output voltage stabilization capacitor, D+...
diode. -11 de\
Claims (1)
ｄＧａｔｅＦｉｅｌｄＥｆｆｅｃｔＴｒａｎｓｉｓｔｏ
ｒ以下ＩＧ・ＦＥＴと省略する）で構成される集積回路
の第１の導電型の第１のＩＧ・ＦＥＴのドレインと第２
の導電型の第２のＩＧ・ＦＥＴのドレインとコンデンサ
の一方の端子とを接続し、前記第２の導電型の第２のＩ
Ｇ・ＦＥＴのソースと第１の電源のグランドとを接続し
、前記第２の導電型の第２のＩＧ・ＦＥＴとしきい値が
異なる第２の導電型の第３のＩＧ・ＦＥＴのソースと第
２の入力電源とを接続し、前記第１の導電型の第１のＩ
Ｇ・ＦＥＴのゲートと前記第２の導電型の第２のＩＧ・
ＦＥＴのゲートと前記第２の導電型の第３のＩＧ・ＦＥ
Ｔのゲートとクロック入力端子とを接続したうえ前記コ
ンデンサの他方の端子と前記第２の導電型の第３のＩＧ
・ＦＥＴのドレインとを接続してこれを出力としかつ前
記第１の導電型の第１のＩＧ・ＦＥＴのソースを入力と
する昇圧回路ブロックをＮ（Ｎ＝２、３……）段直列に
接続して成ることを特徴とする昇圧回路。Insulated gate field effect transistor
dGateFieldEffectTransisto
The drain of the first IG/FET of the first conductivity type and the second
The drain of the second IG-FET of the conductivity type is connected to one terminal of the capacitor, and the second IG-FET of the second conductivity type is connected.
The source of the G-FET is connected to the ground of the first power supply, and the source of a third IG-FET of a second conductivity type has a different threshold value from that of the second IG-FET of the second conductivity type. a second input power source, and a first I of the first conductivity type.
The gate of the G-FET and the second IG-FET of the second conductivity type.
The gate of the FET and the third IG/FE of the second conductivity type
The gate of T and the clock input terminal are connected, and the other terminal of the capacitor and the third IG of the second conductivity type are connected.
・N (N=2, 3...) stages of booster circuit blocks connected in series to the drain of the FET and using this as an output and the source of the first IG FET of the first conductivity type as an input. A booster circuit characterized by being connected to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62152562A JPS63316510A (en) | 1987-06-18 | 1987-06-18 | Boosting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62152562A JPS63316510A (en) | 1987-06-18 | 1987-06-18 | Boosting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63316510A true JPS63316510A (en) | 1988-12-23 |
Family
ID=15543192
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62152562A Pending JPS63316510A (en) | 1987-06-18 | 1987-06-18 | Boosting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63316510A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5892267A (en) * | 1996-05-12 | 1999-04-06 | Oki Electric Industry Co., Ltd. | Multi-stage voltage-boosting circuit with boosted back-gate bias |
| US6838928B2 (en) | 2002-07-31 | 2005-01-04 | Renesas Technology Corp. | Boosting circuit configured with plurality of boosting circuit units in series |
-
1987
- 1987-06-18 JP JP62152562A patent/JPS63316510A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5892267A (en) * | 1996-05-12 | 1999-04-06 | Oki Electric Industry Co., Ltd. | Multi-stage voltage-boosting circuit with boosted back-gate bias |
| US6838928B2 (en) | 2002-07-31 | 2005-01-04 | Renesas Technology Corp. | Boosting circuit configured with plurality of boosting circuit units in series |
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