CN117639785A

CN117639785A - Grid voltage bootstrapping sampling hold circuit

Info

Publication number: CN117639785A
Application number: CN202311873010.1A
Authority: CN
Inventors: 左成杰; 吴洪成
Original assignee: University of Science and Technology of China USTC
Current assignee: University of Science and Technology of China USTC
Priority date: 2023-12-31
Filing date: 2023-12-31
Publication date: 2024-03-01

Abstract

The disclosure provides a gate voltage bootstrap sample hold circuit which can be applied to the technical field of analog integrated circuits. The circuit comprises: the first control module, the second control module, the first switching tube and the second switching tube; the input end of the first control module is connected with an input signal and a clock signal, and the output end of the first control module is connected to the control end of the first switching tube; the first end of the first switching tube is connected with the output end of the circuit and the first end of the second switching tube respectively, and the second end of the first switching tube is connected with an input signal; the input end of the second control module is connected with an input signal and a clock signal, and the output end of the second control module is connected to the control end of the second switching tube; the first end of the second switching tube is connected to the output end of the circuit, and the second end of the second switching tube is connected to an input signal; the output of the circuit is configured to output a target signal based on the first sampled signal and the second sampled signal.

Description

Grid voltage bootstrapping sampling hold circuit

Technical Field

The present disclosure relates to the field of analog integrated circuit technology, and more particularly, to a gate voltage bootstrap sample-and-hold circuit.

Background

With the development of the current circuit integration technology, in the design of modules such as an analog-digital converter and a phase discriminator, the requirements on response speed and sampling precision of the modules are gradually improved. In the prior art, a traditional sampling hold circuit adopts a transistor as a sampling switch, and the sampling switch is controlled to realize sampling by charging and discharging a capacitor.

However, in practical application, due to the influence of the lining bias effect, the threshold voltage of the sampling switch in the traditional sampling hold circuit can change along with the change of the input signal, so that nonlinearity is introduced into the on-resistance of the sampling switch, the linearity of the sampling switch is limited, and the sampling precision and the sampling efficiency of the sampling hold circuit are affected.

Disclosure of Invention

In view of this, the present disclosure provides a gate voltage bootstrap sample-and-hold circuit, including: the first control module, the second control module, the first switching tube and the second switching tube; the input end of the first control module is connected with an input signal and a clock signal, the output end of the first control module is connected to the control end of the first switch tube, and the first control module is configured to output a first control signal to the first switch tube based on the input signal and the clock signal; the first end of the first switching tube is respectively connected with the output end of the grid voltage bootstrap sampling and holding circuit and the first end of the second switching tube, the second end of the first switching tube is connected with an input signal, and the first switching tube is configured to generate a first sampling signal under the condition of conduction based on the input signal and the first control signal; the input end of the second control module is connected with the input signal and the clock signal, the output end of the second control module is connected to the control end of the second switching tube, and the second control module is configured to output a second control signal to the second switching tube based on the input signal and the clock signal; the first end of the second switching tube is connected to the output end of the grid voltage bootstrap sampling and holding circuit, the second end of the second switching tube is connected to the input signal, the second switching tube is configured to generate a second sampling signal under the condition of conduction based on the input signal and the second control signal, and the first control signal and the second control signal are opposite-level signals, so that the first switching tube and the second switching tube are simultaneously conducted or simultaneously turned off; the output terminal of the gate voltage bootstrap sample-and-hold circuit is configured to output a target signal based on the first sampling signal and the second sampling signal.

According to an embodiment of the disclosure, the first control module includes a first signal input sub-module and a first control sub-module, an input end of the first signal input sub-module is connected to the input signal, and an output end of the first signal input sub-module is connected to the first control sub-module; the input end of the first control sub-module is connected with the clock signal, and the output end of the first control sub-module is connected to the control end of the first switch tube.

According to an embodiment of the present disclosure, the first control submodule includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor; the control end of the first transistor is connected with a first clock signal, the first end of the first transistor is grounded, and the second end of the first transistor is connected to a first node; the control end of the second transistor is connected to the first clock signal, the first end of the second transistor is grounded, and the second end of the second transistor is connected to a second node; the control end of the third transistor is connected with a second clock signal, the first end of the third transistor is connected to the first node, and the second end of the third transistor is connected to the first end of the fourth transistor; the control end of the fourth transistor is connected with the second clock signal, and the second end of the fourth transistor is connected with a power supply voltage; the control end of the fifth transistor is connected to the second clock signal, the first end of the fifth transistor is connected to a third node, and the second end of the fifth transistor is connected to the power supply voltage; the control end of the sixth transistor is connected to the first clock signal, the first end of the sixth transistor is connected to the second node, and the second end of the sixth transistor is connected to the third node; the first plate of the first capacitor is connected to the first node, the second plate of the first capacitor is connected to the third node, the first plate potential of the first capacitor is configured to be determined based on a voltage corresponding to the first node, and the second plate potential of the first capacitor is configured to be determined based on a voltage corresponding to the third node.

According to an embodiment of the disclosure, the first signal input submodule includes a seventh transistor and an eighth transistor, a control terminal of the seventh transistor is connected to the second node, a first terminal of the seventh transistor is connected to the first node and a first terminal of the eighth transistor, a second terminal of the seventh transistor is connected to the input signal, and a second terminal of the seventh transistor is connected to a second terminal of the eighth transistor; the control end of the eighth transistor is connected to the output end of the second control module, and the second end of the eighth transistor is connected to the input signal.

According to an embodiment of the disclosure, the second control module includes a second signal input sub-module and a second control sub-module, an input end of the second signal input sub-module is connected to the input signal, and an output end of the second signal input sub-module is connected to the second control sub-module; the input end of the second control sub-module is connected with the clock signal, and the output end of the second control sub-module is connected to the control end of the second switch tube.

According to an embodiment of the present disclosure, the second control submodule includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a second capacitor; the control terminal of the ninth transistor is connected to the first clock signal, the first terminal of the ninth transistor is grounded, and the second terminal of the ninth transistor is connected to the first terminal of the fourteenth transistor; the control end of the tenth transistor is connected to the first clock signal, the first end of the tenth transistor is grounded, and the second end of the tenth transistor is connected to a fourth node; the control end of the eleventh transistor is connected to the second clock signal, the first end of the eleventh transistor is connected to the fourth node, and the second end of the eleventh transistor is connected to the fifth node; the control end of the twelfth transistor is connected to the second clock signal, the first end of the twelfth transistor is connected to the fifth node, and the second end of the twelfth transistor is connected to the power supply voltage; the control end of the thirteenth transistor is connected to the second clock signal, the first end of the thirteenth transistor is connected to the sixth node, and the second end of the thirteenth transistor is connected to the power supply voltage; the control end of the fourteenth transistor is connected to the second clock signal, and the second end of the fourteenth transistor is connected to the sixth node; the first plate of the second capacitor is connected to the fourth node, the second plate of the second capacitor is connected to the sixth node, the first plate potential of the second capacitor is configured to be determined based on a voltage corresponding to the fourth node, and the second plate potential of the second capacitor is configured to be determined based on a voltage corresponding to the sixth node.

According to an embodiment of the present disclosure, the second signal input sub-circuit includes a fifteenth transistor and a sixteenth transistor, a control terminal of the fifteenth transistor is connected to the second node of the first control sub-circuit, a first terminal of the fifteenth transistor is connected to the first terminal of the sixteenth transistor and the sixth node, respectively, a second terminal of the fifteenth transistor is connected to the input signal, and a second terminal of the fifteenth transistor is connected to a second terminal of the sixteenth transistor; the control terminal of the sixteenth transistor is connected to the fifth node, the first terminal of the sixteenth transistor is connected to the sixth node, the second terminal of the sixteenth transistor is connected to the input signal, wherein the second node is configured as the output terminal of the first control module, and the fifth node is configured as the output terminal of the second control module.

According to an embodiment of the disclosure, the gate voltage bootstrap sample-and-hold circuit further includes a first substrate input module, wherein a first end of the first substrate input module is connected to the input signal, and a second end of the first substrate input module is connected to a third end of the first switching tube; the first substrate module comprises a seventeenth transistor and an eighteenth transistor, wherein the control end of the seventeenth transistor is connected to the second node, the first end of the seventeenth transistor is respectively connected with the first end of the eighteenth transistor and the third end of the first switch transistor, the second end of the seventeenth transistor is connected with the input signal, and the second end of the seventeenth transistor is connected to the second end of the eighteenth transistor; the control terminal of the eighteenth transistor is connected to the fifth node, the first terminal of the eighteenth transistor is connected to the first terminal of the seventeenth transistor and the third terminal of the first switching transistor, the second terminal of the eighteenth transistor is connected to the input signal, and the second terminal of the eighteenth transistor is connected to the second terminal of the seventeenth transistor.

According to an embodiment of the disclosure, the gate voltage bootstrap sample-and-hold circuit further includes a second substrate module, wherein a first end of the second substrate module is connected to the input signal, and a second end is connected to a third end of the second switching tube; the second substrate module comprises a nineteenth transistor and a twentieth transistor, wherein the control end of the nineteenth transistor is connected to the second node, the first end of the nineteenth transistor is respectively connected with the first end of the twentieth transistor and the third end of the second switch transistor, the second end of the nineteenth transistor is connected with the input signal, and the second end of the nineteenth transistor is connected to the second end of the twentieth transistor; a control terminal of the twentieth transistor is connected to the fifth node, a first terminal of the twentieth transistor is connected to the first terminal of the nineteenth transistor and the third terminal of the second switching transistor, a second terminal of the twentieth transistor is connected to the input voltage, and a second terminal of the twentieth transistor is connected to the second terminal of the nineteenth transistor.

According to an embodiment of the present disclosure, the first control signal is configured to be the same as the voltage value at the second node, and the second control signal is configured to be the same as the voltage value at the fifth node.

The embodiment of the disclosure adopts a first control module and a second control module, and based on the cooperative work of input signals, the first control signal output by the first control module and the second control signal output by the second control module are of opposite levels, the first switching tube and the second switching tube are in a sampling state under the condition of being simultaneously conducted, and are in a holding state under the condition of being simultaneously turned off, so that the grid voltage bootstrap sampling holding circuit is controlled to sample; in addition, based on the first control signal and the input signal, a stable voltage difference can be formed between the control end of the first switching tube and the first end of the first switching tube, and based on the second control signal and the input signal, a stable high voltage difference can be formed between the control end of the second switching tube and the first end of the second switching tube, so that the on-resistance of the first switching tube and the second switching tube is effectively reduced, the sampling resistance is kept stable during the sampling period, and the sampling speed and the sampling precision of the grid voltage bootstrap sampling and holding circuit are further improved.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments thereof with reference to the accompanying drawings in which:

Fig. 1 schematically illustrates a schematic structure of a gate voltage bootstrap sample-and-hold circuit in accordance with an embodiment of the present disclosure;

FIG. 2 schematically illustrates a circuit schematic of a first control sub-module according to an embodiment of the present disclosure;

FIG. 3 schematically illustrates a circuit schematic of a first signal input sub-module according to an embodiment of the disclosure;

FIG. 4 schematically illustrates a circuit schematic of a second control sub-module according to an embodiment of the present disclosure;

fig. 5 schematically illustrates a circuit schematic of a second signal input sub-module according to an embodiment of the disclosure;

FIG. 6 schematically illustrates a circuit schematic of a first substrate input module according to an embodiment of the disclosure;

FIG. 7 schematically illustrates a circuit schematic of a second substrate input module according to an embodiment of the disclosure;

fig. 8 schematically illustrates a circuit schematic of a gate voltage bootstrapped sample-and-hold circuit according to a specific embodiment of the present disclosure.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The terms "comprises," "comprising," and/or the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.

All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It should be noted that the terms used herein should be construed to have meanings consistent with the context of the present specification and should not be construed in an idealized or overly formal manner.

Where expressions like at least one of "A, B and C, etc. are used, the expressions should generally be interpreted in accordance with the meaning as commonly understood by those skilled in the art (e.g.," a system having at least one of A, B and C "shall include, but not be limited to, a system having a alone, B alone, C alone, a and B together, a and C together, B and C together, and/or A, B, C together, etc.).

With the development of the current circuit integration technology, in the design of modules such as an analog-digital converter and a phase discriminator, the requirements on response speed and sampling precision of the modules are gradually improved. In the prior art, a sampling hold circuit conventionally and commonly adopted adopts a transistor as a sampling switch, and the sampling switch is controlled to realize sampling by charging and discharging a capacitor.

However, in practical application, due to the influence of the lining bias effect, the threshold voltage of the sampling switch in the traditional sampling hold circuit can change along with the change of an input signal, so that nonlinearity is introduced into the on-resistance of the sampling switch, the linearity of the sampling switch is limited, and due to the fact that larger on-resistance exists when the sampling switch is conducted, the nonlinearity distortion of a voltage sampling value can be caused, and the sampling precision and the sampling efficiency of the sampling hold circuit are influenced.

In view of this, an embodiment of the present disclosure proposes a gate voltage bootstrap sample-and-hold circuit, including: the first control module, the second control module, the first switching tube and the second switching tube; the input end of the first control module is connected with an input signal and a clock signal, the output end of the first control module is connected to the control end of the first switching tube, and the first control module is configured to output a first control signal to the first switching tube based on the input signal and the clock signal; the first end of the first switching tube is connected with the output end of the grid voltage bootstrapping sampling and holding circuit and the first end of the second switching tube respectively, the second end of the first switching tube is connected with an input signal, and the first switching tube is configured to generate a first sampling signal under the condition of conduction based on the input signal and a first control signal; the input end of the second control module is connected with an input signal and a clock signal, the output end of the second control module is connected to the control end of the second switching tube, and the second control module is configured to output a second control signal to the second switching tube based on the input signal and the clock signal; the first end of the second switching tube is connected to the output end of the grid voltage bootstrapping sampling and holding circuit, the second end of the second switching tube is connected to an input signal, the second switching tube is configured to generate a second sampling signal under the condition of conduction based on the input signal and a second control signal, and the first control signal and the second control signal are opposite level signals, so that the first switching tube and the second switching tube are simultaneously conducted or simultaneously turned off; the output of the gate voltage bootstrapping sample-and-hold circuit is configured to output a target signal based on the first and second sampled signals.

Unless defined otherwise, technical or scientific terms used in the embodiments of the present disclosure should be in a general sense understood by those skilled in the art. The terms "first," "second," and the like, as used in embodiments of the present disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another.

Furthermore, in the description of embodiments of the present disclosure, the term "connected to" or "connected to" may refer to two components being directly connected, or may refer to two components being connected via one or more other components. Furthermore, the two components may be connected or coupled by wire or wirelessly.

The transistors employed in the embodiments of the present disclosure may include switching transistors and driving transistors, depending on their functions. The switching transistor and the driving transistor may be thin film transistors or field effect transistors or other devices having the same characteristics. In embodiments of the present disclosure, the gate may be referred to as a control electrode, one of the source and the drain may be referred to as a first terminal, and the other of the source and the drain may be referred to as a second terminal, depending on its function.

Furthermore, in the description of the embodiments of the present disclosure, the terms "first control signal" and "second control signal" are used only to distinguish between the differences in the magnitudes of the two signal voltages. Those skilled in the art will appreciate that the present disclosure is not so limited.

Fig. 1 schematically illustrates a schematic structure of a gate voltage bootstrap sample-and-hold circuit according to an embodiment of the present disclosure.

As shown in fig. 1, the gate voltage bootstrap sample-and-hold circuit includes a first control module 101, a first switching tube 102, a second switching tube 103, and a second control module 104.

According to an embodiment of the present disclosure, an input terminal of the first control module 101 is connected to an input signal and a clock signal, and an output terminal of the first control module 101 is connected to a control terminal of the first switching tube 102; the first end of the first switching tube 102 is respectively connected with the output end of the grid voltage bootstrap sampling holding circuit and the first end of the second switching tube 103, and the second end of the first switching tube 102 is connected with an input signal; the input end of the second control module 104 is connected with an input signal and a clock signal, and the output end of the second control module 104 is connected to the control end of the second switching tube 103; the first end of the second switching tube 103 is connected to the output end of the gate voltage bootstrapping sample-and-hold circuit, and the second end of the second switching tube 103 is connected to an input signal.

The first control module 101 may be configured to output a first control signal to the first switching tube 102, wherein the first control signal may be configured to determine the first voltage control signal based on a power supply voltage signal, an input signal, and a clock signal of the first control module 101, and the first control signal may be used to control on and off of the first switching tube 102.

The second control module 104 may be configured to output a second control signal to the second switching tube 103, wherein the second control signal may be configured to determine the second voltage control signal based on a power supply voltage signal, an input signal, and a clock signal of the second control module 104, and the second control signal may be used to control on and off of the second switching tube 103.

According to embodiments of the present disclosure, the clock signals may be configured as two non-overlapping clock signals, which may be provided by external circuitry, e.g., when one of the clock signals is high, the other is low, and vice versa.

According to an embodiment of the present disclosure, the first switching tube 102 and the second switching tube 103 may be any set of sampling switches of the gate voltage bootstrap sample-and-hold circuit, wherein the first switching tube 102 may be used to generate the first sampling signal based on the input signal and the first control signal. Specifically, the first switching tube 102 may be configured to be turned on or off based on the level of the first control signal, and in the case of being turned on, generate the first sampling signal based on the input signal.

According to an embodiment of the present disclosure, the second switching tube 103 may be used to generate the second sampling signal based on the input signal and the second control signal. Specifically, the second switching tube 103 may be configured to be turned on or off based on the level of the second control signal, and in the case of being turned on, generate the second sampling signal based on the input signal.

According to an embodiment of the present disclosure, the first switching tube 102 and the second switching tube 103 may each be a complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) field effect tube, where the complementary CMOS may be formed by connecting an N-channel field effect tube and a P-channel field effect tube in parallel, for example, the first switching tube 102 may be configured as an N-channel field effect tube, and turned on when the control terminal receives a high level signal; the second switching tube 103 may be configured as a P-channel field effect tube, turned on at the moment when the control terminal receives the low level signal, and the first switching tube 102 and the second switching tube 103 may be configured to be connected in parallel.

According to embodiments of the present disclosure, the output of the gate voltage bootstrapping sample-and-hold circuit may be configured to output a target signal based on the first and second sampled signals, wherein the target signal may be used to characterize the sampling result of the sample-and-hold circuit.

According to an embodiment of the present disclosure, the first control signal output by the first control module 101 and the second control signal output by the second control module 104 may be configured such that the first control signal and the second control signal are at opposite levels, so that the control ends of the first switch tube 102 and the second switch tube 103 are turned on or off simultaneously in response to receiving the control signals, respectively, in a case where the first switch tube 102 and the second switch tube 103 are turned off simultaneously, the gate voltage bootstrap sample-hold circuit is in a hold state, and in a case where the first switch tube 102 and the second switch tube 103 are turned on simultaneously, the gate voltage bootstrap sample-hold circuit is in a sample state.

For example, in the case where the first switching tube 102 is configured as an N-channel field effect tube and the second switching tube 103 is configured as a P-channel field effect tube, the first end of the first switching tube 102 may be denoted as a source of the first switching tube 102, the second end of the first switching tube 102 may be denoted as a drain of the first switching tube 102, and the control end of the first switching tube 102 may be denoted as a gate of the first switching tube 102. The first end of the second switching tube 103 may be denoted as a source of the second switching tube 103, the second end of the second switching tube 103 may be denoted as a drain of the second switching tube 103, and the control end of the second switching tube 103 may be denoted as a gate of the second switching tube 103.

Specifically, if the control end of the first switching tube 102 responds to the received first control signal as a low-level signal, the control end of the second switching tube 103 responds to the received second control signal as a high-level signal, at this time, both the first switching tube 102 and the second switching tube 103 are in an off state, and at this time, the gate voltage bootstrap sampling hold circuit is in an un-sampled hold state; if the control end of the first switching tube 102 responds to the received first control signal as a high level signal, the control end of the second switching tube 103 responds to the received second control signal as a low level signal, at this time, both the first switching tube 102 and the second switching tube 103 are in a conducting state, and at this time, the gate voltage bootstrap sampling hold circuit is in a sampling state of continuous sampling.

According to the embodiment of the present disclosure, in the case that the first switching tube 102 is turned on, a stable voltage difference may be formed between the control terminal of the first switching tube 102 and the first terminal of the first switching tube 102, i.e., the gate and the source of the first switching tube 102, based on the first control signal and the input signal; in addition, under the condition that the second switching tube 103 is turned on, based on the second control signal and the input signal, a stable high voltage difference can be formed between the control end of the second switching tube 103 and the first end of the second switching tube 103, namely, the gate electrode and the source electrode of the second switching tube 103, so that the fluctuation of the on-resistance and the resistance of the first switching tube and the second switching tube is effectively reduced, and the sampling speed and the sampling precision of the grid voltage bootstrap sampling hold circuit are further improved.

The embodiment of the disclosure adopts a first control module and a second control module, and based on the cooperative work of input signals, the first control signal output by the first control module and the second control signal output by the second control module are of opposite levels, the first switching tube and the second switching tube are in a sampling state under the condition of being simultaneously conducted, and are in a holding state under the condition of being simultaneously turned off, so that the grid voltage bootstrap sampling holding circuit is controlled to sample; in addition, based on the first control signal and the input signal, a stable high voltage difference can be formed between the control end of the first switching tube and the first end of the first switching tube, and based on the second control signal and the input signal, a stable high voltage difference can also be formed between the control end of the second switching tube and the first end of the second switching tube, so that on-resistance and resistance fluctuation of the first switching tube and the second switching tube are effectively reduced, the sampling resistor is kept stable in the sampling period, and the sampling speed and the sampling precision of the grid voltage bootstrap sampling and holding circuit are further improved.

According to an embodiment of the disclosure, the first control module includes a first signal input sub-module and a first control sub-module, an input end of the first signal input sub-module is connected with an input signal, and an output end of the first signal input sub-module is connected to the first control sub-module; the input end of the first control submodule is connected with a clock signal, and the output end of the first control submodule is connected to the control end of the first switching tube.

The first control sub-module and the first signal input sub-module are further described below with reference to fig. 2 and 3.

Fig. 2 schematically illustrates a circuit schematic of a first control sub-module according to an embodiment of the disclosure.

As shown in fig. 2, the first control submodule includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a first capacitor C1, and further includes a first node a, a second node b, and a third node C, where the clock signals in the embodiments of the present disclosure may be configured as two non-overlapping clock signals, the clock signals include a first clock signal and a second clock signal, and the first clock signal and the second clock signal may be configured as opposite levels to each other.

According to an embodiment of the present disclosure, a control terminal of the first transistor M1 is connected to a first clock signal, a first terminal of the first transistor M1 is grounded, and a second terminal of the first transistor M1 is connected to the first node a. The control end of the second transistor M2 is connected to the first clock signal, the first end of the second transistor M2 is grounded, and the second end of the second transistor M2 is connected to the second node b. The control terminal of the third transistor M3 is connected to the second clock signal, the first terminal of the third transistor M3 is connected to the first node a, and the second terminal of the third transistor M3 is connected to the first terminal of the fourth transistor M4. The control terminal of the fourth transistor M4 is connected to the second clock signal, and the second terminal of the fourth transistor M4 is connected to the power supply voltage. The control terminal of the fifth transistor M5 is connected to the second clock signal, the first terminal of the fifth transistor M5 is connected to the third node c, and the second terminal of the fifth transistor M5 is connected to the power supply voltage. The control terminal of the sixth transistor M6 is connected to the first clock signal, the first terminal of the sixth transistor M6 is connected to the second node b, and the second terminal of the sixth transistor M6 is connected to the third node c. The first polar plate of the first capacitor C1 is connected to the first node a, and the second polar plate of the first capacitor C1 is connected to the third node C.

According to the embodiment of the disclosure, the first capacitor C1 may be used as a bootstrap capacitor of the first control sub-module, and the first capacitor C1 may be used to raise the dc bias voltage of the second plate of the capacitor, so that the amplitude of the output signal may be enhanced. Wherein the potential of the first plate of the first capacitor C1 may be configured to be determined based on the voltage corresponding to the first node a, and the potential of the second plate of the first capacitor C1 is determined based on the voltage corresponding to the third node C.

In the embodiment of the present disclosure, the first node a may be used as an access terminal of the first signal input sub-module, and the second node b may be used as an output terminal of the first control signal of the first control sub-module.

Specifically, as shown in fig. 2, the first transistor M1, the second transistor M2, and the third transistor M3 may be configured as N-type transistors, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 may be configured as P-type transistors, wherein a first end of the N-type transistor may be denoted as a source, a second end may be denoted as a drain, a control end may be denoted as a gate, a first end of the P-type transistor may be denoted as a drain, a second end may be denoted as a source, and a control end may be denoted as a gate. The power supply voltage may be configured as a high level voltage VDD, and the voltage at the ground may be configured as a low level voltage GND, wherein the voltage value of the power supply voltage VDD may be set to 1v, and the voltage value of the ground voltage GND may be set to 0v.

Since the control terminals of the first transistor M1, the second transistor M2, and the sixth transistor M6 are all configured to be connected to the first clock signal ck, the control terminals of the third transistor M3, the fourth transistor M4, and the fifth transistor M5 are all configured to be connected to the second clock signal ckb.

Therefore, when the first clock signal ck is at a high level and the second clock signal ckb is at a low level, the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5 are turned on, and the third transistor M3 and the sixth transistor M6 are turned off. At this time, the voltage at the first node a is set to a low level voltage, and the corresponding first node voltage va=gnd=0 at the first node a, the voltage at the third node C is set to a high level voltage, and the corresponding third node voltage vc=vdd at the third node C, so that the first plate of the first capacitor C1 is connected to the first node a, i.e. the first plate voltage of the first capacitor C1 is va=0, the second plate of the first capacitor C1 is connected to the third node C, i.e. the second plate voltage of the first capacitor C1 is vc=vdd, and the voltage difference between the two plates of the first capacitor C1 is VDD; since the voltage at the second node b is set to the low-level voltage, and the corresponding second node voltage vb=gnd=0 at the second node b. Therefore, when the first clock signal ck is at a high level and the second clock signal ckb is at a low level, the first control signal outputted by the first control sub-module is vb=gnd=0.

When the first clock signal ck is at a low level and the second clock signal ckb is at a high level, the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5 are turned off, and the third transistor M3 and the sixth transistor M6 are turned on. At this time, since the first plate of the first capacitor C1 has no discharge path, the first capacitor C1 is in a floating state, and thus the corresponding first node voltage Va at the first node a remains GND unchanged. The voltage at the second node b is the same as the voltage at the third node c and both are kept in the floating state, so that the second node voltage Vb corresponding to the second node b is the same as the third node voltage Vc corresponding to the third node c, and the second node voltage Vb and the third node voltage Vc are both the voltage VDD before floating. At this time, since the first and second plates of the first capacitor C1 are in a floating state, and the first terminal voltage is the first node voltage va=gnd, the second terminal voltage is the third node voltage vc=vdd, and the voltage difference between the two plates of the first capacitor C1 is still VDD. Therefore, when the first clock signal ck is at a low level and the second clock signal ckb is at a high level, the first control signal outputted by the first control sub-module is vb=vdd.

Fig. 3 schematically illustrates a circuit schematic of a first signal input sub-module according to an embodiment of the disclosure.

As shown in fig. 3, the first signal input sub-module includes a seventh transistor M7 and an eighth transistor M8, the control terminal of the seventh transistor M7 is connected to the second node b, the first terminal of the seventh transistor M7 is connected to the first node a and the first terminal of the eighth transistor M8, the second terminal of the seventh transistor M7 is connected to the input signal Vin, and the second terminal of the seventh transistor M7 is connected to the second terminal of the eighth transistor M8; the control terminal of the eighth transistor M8 is connected to the output terminal of the second control module, and the second terminal of the eighth transistor is connected to the input signal Vin.

According to an embodiment of the present disclosure, the seventh transistor M7 may be configured as an N-type transistor, the eighth transistor M8 may be configured as a P-type transistor, wherein a first terminal of the N-type transistor may be denoted as a source, a second terminal may be denoted as a drain, a control terminal may be denoted as a gate, a first terminal of the P-type transistor may be denoted as a drain, a second terminal may be denoted as a source, and a control terminal may be denoted as a gate.

Specifically, when the first clock signal ck is at a high level and the second clock signal ckb is at a low level, the corresponding second node voltage vb=gnd at the second node b. Therefore, the seventh transistor M7 is in an off state.

When the first clock signal ck is at a low level and the second clock signal ckb is at a high level, the corresponding second node voltage vb=vdd at the second node b, and therefore, the seventh transistor M7 is in a conducting state, the input signal Vin may be input to the first node a through the seventh transistor M7, and at this time, the corresponding first node voltage va=vin at the first node a, and therefore, the first signal input sub-module may be capable of switching the input signal Vin into the first control sub-module.

When the corresponding first node voltage Va at the first node a changes from GND to Vin, at this time, the first plate voltage of the first capacitor C1 changes from GND to Vin, and since the voltage difference between the two plates of the first capacitor C1 needs to be kept constant by VDD, the second plate voltage of the first capacitor, that is, the third node voltage Vc, rises from VDD to vdd+vin, that is, vc=vb=vdd+vin, at this time, the first control signal output by the first control submodule is vdd+vin, and voltage bootstrap of the first capacitor C1 is completed.

According to an embodiment of the disclosure, the second control module includes a second signal input sub-module and a second control sub-module, an input end of the second signal input sub-module is connected to an input signal, and an output end of the second signal input sub-module is connected to the second control sub-module; the input end of the second control submodule is connected with a clock signal, and the output end of the second control submodule is connected to the control end of the second switching tube.

The second control sub-module and the second signal input sub-module are further described below with reference to fig. 4 and 5.

Fig. 4 schematically illustrates a circuit schematic of a second control sub-module according to an embodiment of the disclosure.

As shown in fig. 4, the second control submodule includes a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, and a second capacitor C2. The second control sub-module further comprises a fourth node e, a fifth node f and a sixth node g.

According to an embodiment of the present disclosure, a control terminal of the ninth transistor M9 is connected to the first clock signal, a first terminal of the ninth transistor M9 is grounded, and a second terminal of the ninth transistor M9 is connected to a first terminal of the fourteenth transistor M14; the control end of the tenth transistor M10 is connected to the first clock signal, the first end of the tenth transistor M10 is grounded, and the second end of the tenth transistor M10 is connected to the fourth node e; the control end of the eleventh transistor M11 is connected with the second clock signal, the first end of the eleventh transistor M11 is connected to the fourth node e, and the second end of the eleventh transistor M11 is connected to the fifth node f; the control end of the twelfth transistor M12 is connected to the second clock signal, the first end of the twelfth transistor M12 is connected to the fifth node f, and the second end of the twelfth transistor M12 is connected to the power supply voltage; the control end of the thirteenth transistor M13 is connected to the second clock signal, the first end of the thirteenth transistor M13 is connected to the sixth node g, and the second end of the thirteenth transistor M13 is connected to the power supply voltage; the control end of the fourteenth transistor M14 is connected with a second clock signal, and the second end of the fourteenth transistor M14 is connected to a sixth node g; the second plate of the second capacitor C2 is connected to the sixth node g, the first plate of the second capacitor C2 is connected to the fourth node e, and the first plate potential of the second capacitor C2 is configured to be determined based on the voltage corresponding to the fourth node e, and the second plate potential of the second capacitor C2 is determined based on the voltage corresponding to the sixth node g.

According to the embodiment of the disclosure, the second capacitor C2 may be used as a bootstrap capacitor of the second control sub-module, and the second capacitor C2 may be used to reduce the dc bias voltage of the first plate of the capacitor, so that the amplitude of the output signal may be reduced.

In an embodiment of the present disclosure, the sixth node g may be used as an access terminal of the second signal input sub-module, and the fifth node f may be used as an output terminal of the second control signal of the second control sub-module.

Specifically, as shown in fig. 4, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the fourteenth transistor M14 may be configured as N-type transistors, the twelfth transistor M12, and the thirteenth transistor M13 may be configured as P-type transistors, wherein a first end of the N-type transistors may be denoted as a source, a second end may be denoted as a drain, a control end may be denoted as a gate, a first end of the P-type transistors may be denoted as a drain, a second end may be denoted as a source, and a control end may be denoted as a gate. The power supply voltage may be configured as a high level voltage VDD, and the voltage at the ground may be configured as a low level voltage GND, wherein the voltage value of the power supply voltage VDD may be set to 1v, and the voltage value of the ground voltage GND may be set to 0v.

Since the control terminals of the ninth transistor M9 and the tenth transistor M10 are each configured to be connected to the first clock signal ck, the control terminals of the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13 and the fourteenth transistor M14 are each configured to be connected to the second clock signal ckb.

Therefore, when the first clock signal ck is at a high level and the second clock signal ckb is at a low level, the ninth transistor M9, the tenth transistor M10, the twelfth transistor M12, the thirteenth transistor M13 are turned on, and the eleventh transistor M11, the fourteenth transistor M14 are turned off. At this time, the voltage at the fourth node e is set to a low level voltage, and the corresponding fourth node voltage ve=gnd=0 at the fourth node e, the voltage at the fifth node f is set to a high level voltage, and the corresponding fifth node voltage vf=vdd at the fifth node f, the voltage at the sixth node g is set to a high level voltage, and the corresponding sixth node voltage vg=vdd at the sixth node g. Therefore, the first plate of the second capacitor C2 is connected to the fourth node e, i.e. the voltage of the first plate of the second capacitor C2 is ve=0, and the second plate of the second capacitor C2 is connected to the sixth node g, i.e. the voltage of the second plate of the second capacitor C2 is vg=vdd, at which time the voltage difference between the two plates of the second capacitor C2 is VDD; since the voltage at the fifth node f is set to the high level voltage, and the corresponding fifth node voltage vf=vdd at the fifth node f. Therefore, when the first clock signal ck is at a high level and the second clock signal ckb is at a low level, the second control signal of the second control sub-module is output as a high level voltage signal vf=vdd.

When the first clock signal ck is at a low level and the second clock signal ckb is at a high level, the ninth transistor M9, the tenth transistor M10, the twelfth transistor M12, the thirteenth transistor M13 are turned off, and the eleventh transistor M11, the fourteenth transistor M14 are turned on. At this time, since the first plate of the second capacitor C2 has no discharge path, the second capacitor C2 is in a floating state, and thus the fourth node voltage Ve corresponding to the fourth node e and the fifth node voltage Vf corresponding to the fifth node f are the same, and ve=vf=gnd=0, and the sixth node voltage vg=vdd corresponding to the sixth node g. At this time, the voltage of the first plate of the second capacitor C2 is the voltage ve=gnd=0 before the suspension of the fourth node voltage Ve, the voltage of the second plate of the second capacitor C2 is the sixth node voltage vg=vdd, and the voltage difference between the two plates of the second capacitor C2 is still VDD, so when the first clock signal ck is at a low level and the second clock signal ckb is at a high level, the second control signal of the second control submodule is output as the low-level voltage signal vf=gnd.

The first control module, the second control module, the first switching tube and the second switching tube of the embodiment of the disclosure form a switch complementary structure, and the polarities of channel charges corresponding to the two switch structures are opposite, so that the channel charges can be mutually offset, and the influence of channel charge injection is weakened. In addition, the switch complementary structure formed by the first control module, the second control module, the first switch tube and the second switch tube can reduce the influence of clock feed-through so as to improve the output sampling precision.

Fig. 5 schematically illustrates a circuit schematic of a second signal input sub-module according to an embodiment of the disclosure.

As shown in fig. 5, the second signal input sub-circuit includes a fifteenth transistor M15 and a sixteenth transistor M16, the control terminal of the fifteenth transistor M15 is connected to the second node b of the first control sub-circuit, the first terminal of the fifteenth transistor M15 is connected to the first terminal of the sixteenth transistor M16 and the sixth node g, respectively, the second terminal of the fifteenth transistor M15 is connected to the input signal Vin, and the second terminal of the fifteenth transistor M15 is connected to the second terminal of the sixteenth transistor M16; the control terminal of the sixteenth transistor M16 is connected to the fifth node f, the first terminal of the sixteenth transistor M16 is connected to the sixth node g, and the second terminal of the sixteenth transistor M16 is connected to the input signal Vin.

According to an embodiment of the present disclosure, the fifteenth transistor M15 may be configured as an N-type transistor, and the sixteenth transistor M16 may be configured as a P-type transistor. The first terminal of the N-type transistor may be denoted as a source, the second terminal may be denoted as a drain, the control terminal may be denoted as a gate, the first terminal of the P-type transistor may be denoted as a drain, the second terminal may be denoted as a source, and the control terminal may be denoted as a gate.

Specifically, when the first clock signal ck is at a high level and the second clock signal ckb is at a low level, the corresponding second node voltage vb=gnd at the second node b. Therefore, the fifteenth transistor M15 is in an off state.

When the first clock signal ck is at a low level and the second clock signal ckb is at a high level, the corresponding second node voltage vb=vdd at the second node b, and therefore, the fifteenth transistor M15 is in a conductive state, the input signal Vin may be input to the sixth node g through the fifteenth transistor M15, and at this time, the corresponding sixth node voltage vg=vin at the sixth node g, and therefore, the second signal input sub-module may be capable of switching the input signal Vin into the second control sub-module.

When the corresponding sixth node voltage Vg at the sixth node g changes from VDD to Vin, the second plate voltage of the second capacitor C2 changes from VDD to Vin, and since the voltage difference between the plates of the second capacitor C2 needs to be kept constant by VDD, the first plate voltage of the second capacitor, i.e., the fourth node voltage Ve, is adjusted down from GND to Vin-VDD, i.e., ve=vf=vin-VDD. Therefore, when the first clock signal ck is at a low level and the second clock signal ckb is at a high level, the second control signal outputted by the second control submodule is vf=vin-VDD, so that the voltage down-regulation of the second capacitor C2 is completed.

According to the embodiment of the disclosure, as can be seen from fig. 1, when the first switching tube 102 is configured as an N-type transistor and the second switching tube 103 is configured as a P-type transistor, when the first clock signal ck is at a high level and the second clock signal ckb is at a low level, the first control signal outputted by the first control sub-module 101 is vb=gnd=0, the second control signal outputted by the second control sub-module is a high-level voltage signal vf=vdd, and at this time, the first switching tube 102 and the second switching tube 103 are both in an off state, and the output voltage is kept unchanged, i.e. is kept.

According to the embodiment of the disclosure, when the first clock signal ck is at a low level and the second clock signal ckb is at a high level, the first control signal output by the first control submodule is vb=vdd+vin, the second control signal output by the second control submodule is vf=vin-VDD, at this time, the first switching tube 102 and the second switching tube 103 are both in an on state, and the voltage Vb after the bootstrap boost is greater and is changed from VDD to vin+vdd, so that the on resistance of the first switching tube 102 is reduced, and at the same time, the voltage Vf after the bootstrap boost is lower and is changed from GND to Vin-VDD, so that the on resistance of the second switching tube 103 is reduced.

According to an embodiment of the present disclosure, the gate voltage bootstrap sample-and-hold circuit further includes a first substrate input module, wherein a first end of the first substrate input module is connected to the input signal, and a second end of the first substrate input module is connected to a third end of the first switching tube 102.

Fig. 6 schematically illustrates a circuit schematic of a first substrate input module according to an embodiment of the disclosure.

As shown in fig. 6, the first substrate module includes a seventeenth transistor M17 and an eighteenth transistor M18, the control terminal of the seventeenth transistor M17 is connected to the second node b, the first terminal of the seventeenth transistor M17 is connected to the first terminal of the eighteenth transistor M18 and the third terminal of the first switching transistor 102, the second terminal of the seventeenth transistor M17 is connected to the input signal Vin, and the second terminal of the seventeenth transistor M17 is connected to the second terminal of the eighteenth transistor M18; the control terminal of the eighteenth transistor M18 is connected to the fifth node f, the first terminal of the eighteenth transistor M18 is connected to the first terminal of the seventeenth transistor M17 and the third terminal of the first switching transistor 102, the second terminal of the eighteenth transistor M18 is connected to the input signal Vin, and the second terminal of the eighteenth transistor M18 is connected to the second terminal of the seventeenth transistor M17.

According to an embodiment of the present disclosure, the seventeenth transistor M17 may be configured as an N-type transistor, and the eighteenth transistor M18 may be configured as a P-type transistor.

Specifically, when the first clock signal ck is at a high level and the second clock signal ckb is at a low level, the corresponding second node voltage vb=gnd at the second node b and the corresponding fifth node voltage vf=vdd at the fifth node f. Thus, the seventeenth transistor M17 and the eighteenth transistor M18 are both in an off state.

When the first clock signal ck is at a low level and the second clock signal ckb is at a high level, the corresponding second node voltage vb=vin+vdd at the second node b and the corresponding fifth node voltage vf=vin-VDD at the fifth node f are both in an on state, and therefore, the seventeenth transistor M17 and the eighteenth transistor M18 are both in an on state. At this time, the input signal Vin may be input into the substrate of the first switching transistor through the seventeenth transistor M17 and the eighteenth transistor M18.

According to an embodiment of the disclosure, the voltage of the control electrode of the first switch tube is vin+vdd, and the voltages of the first end and the second end of the first switch tube are approximately equal and are both input signals Vin. The voltage difference between its gate and the first terminal, i.e. the first switching tube gate and source, is VDD and remains stable during the whole sampling period. Since the input signal Vin is injected into the substrate of the first switching transistor through the seventeenth transistor M17 and the eighteenth transistor M18, the voltage difference between the substrate and the source of the first switching transistor is 0, so that the threshold voltage Vth1 of the first switching transistor is stabilized.

According to an embodiment of the disclosure, the gate voltage bootstrapping sample-and-hold circuit further comprises a second substrate module, wherein a first end of the second substrate module is connected with an input signal, and a second end of the second substrate module is connected to a third end of the second switching tube.

Fig. 7 schematically illustrates a circuit schematic of a second substrate input module according to an embodiment of the disclosure.

As shown in fig. 7, the second substrate module includes a nineteenth transistor M19 and a twentieth transistor M20, wherein a control terminal of the nineteenth transistor M19 is connected to the second node b, a first terminal of the nineteenth transistor M19 is connected to a first terminal of the twentieth transistor M20 and a third terminal of the second switching transistor, respectively, a second terminal of the nineteenth transistor M19 is connected to the input signal Vin, and a second terminal of the nineteenth transistor M19 is connected to a second terminal of the twentieth transistor M20; the control terminal of the twentieth transistor M20 is connected to the fifth node f, the first terminal of the twentieth transistor M20 is connected to the first terminal of the nineteenth transistor M19 and the third terminal of the second switching transistor, respectively, the second terminal of the twentieth transistor M20 is connected to the input signal Vin, and the second terminal of the twentieth transistor M20 is connected to the second terminal of the nineteenth transistor M19.

According to an embodiment of the present disclosure, the nineteenth transistor M19 may be configured as an N-type transistor, and the twentieth transistor M20 may be configured as a P-type transistor.

Specifically, when the first clock signal ck is at a high level and the second clock signal ckb is at a low level, the corresponding second node voltage vb=gnd at the second node b and the corresponding fifth node voltage vf=vdd at the fifth node f. Therefore, the nineteenth transistor M19 and the twentieth transistor M20 are both in an off state.

When the first clock signal ck is at a low level and the second clock signal ckb is at a high level, the corresponding second node voltage vb=vin+vdd at the second node b and the corresponding fifth node voltage vf=vin-VDD at the fifth node f are both in an on state, and therefore, the nineteenth transistor M19 and the twentieth transistor M20 are both in an on state. At this time, the input signal Vin may be input into the substrate of the second switching transistor through the nineteenth transistor M19, the twentieth transistor M20.

According to the embodiment of the disclosure, the voltage of the control electrode of the second switching tube is Vin-VDD, and the voltages of the first end and the second end of the second switching tube are approximately equal and are both input signals Vin. The voltage difference between the gate and the second terminal thereof is VDD and remains stable throughout the sampling period, and since the input signal Vin is injected into the substrate of the second switching transistor through the nineteenth transistor M19 and the twentieth transistor M20, the voltage difference between the substrate of the second switching transistor and the second terminal is 0, which stabilizes the threshold voltage Vth2 of the second switching transistor.

According to the embodiment of the disclosure, the first substrate input module and the second substrate input module are used for inputting the same signals to the substrates of the first switch tube and the second switch tube, and the voltage difference between the first end of the first switch tube and the second end of the second switch tube is 0, so that the influence of the lining bias effect on the threshold voltage of the switch tube is eliminated, the switch resistor is kept constant during sampling, and the switch linearity is improved.

The operation method of the gate voltage bootstrap sample-and-hold circuit proposed in the present disclosure is further described with reference to fig. 8.

As shown in fig. 8, the gate voltage bootstrapping sample-and-hold circuit includes a first control module 101, a first switch tube 102, a second switch tube 103, a second control module 104, a first substrate input module 801, a second substrate input module 802, and a sampling capacitor C3.

According to an embodiment of the present disclosure, the gate voltage bootstrap sample-and-hold circuit proposed by the present disclosure further includes a sampling capacitor C3, where the sampling capacitor C3 is used to maintain the output voltage value when the gate voltage bootstrap sample-and-hold circuit is in a hold state.

According to an embodiment of the present disclosure, when the first clock signal ck is at a high level and the second clock signal ckb is at a low level, in the first control module 101, the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5 are turned on, and the third transistor M3, the sixth transistor M6 are turned off. At this time, the voltage at the first node a is set to a low level voltage, and the corresponding first node voltage va=gnd=0 at the first node a, the voltage at the third node C is set to a high level voltage, and the corresponding third node voltage vc=vdd at the third node C, so that the first plate of the first capacitor C1 is connected to the first node a, i.e. the first plate voltage of the first capacitor C1 is va=0, the second plate of the first capacitor C1 is connected to the third node C, i.e. the second plate voltage of the first capacitor C1 is vc=vdd, and the voltage difference between the two plates of the first capacitor C1 is VDD; since the voltage at the second node b is set to the low-level voltage, and the corresponding second node voltage vb=gnd=0 at the second node b. The first control signal output by the first control submodule is vb=gnd=0.

According to an embodiment of the present disclosure, when the first clock signal ck is at a high level and the second clock signal ckb is at a low level, in the second control module 102, the ninth transistor M9, the tenth transistor M10, the twelfth transistor M12, the thirteenth transistor M13 are turned on, and the eleventh transistor M11, the fourteenth transistor M14 are turned off. At this time, the voltage at the fourth node e is set to a low level voltage, and the corresponding fourth node voltage ve=gnd=0 at the fourth node e, the voltage at the fifth node f is set to a high level voltage, and the corresponding fifth node voltage vf=vdd at the fifth node f, the voltage at the sixth node g is set to a high level voltage, and the corresponding sixth node voltage vg=vdd at the sixth node g. Therefore, the first plate of the second capacitor C2 is connected to the fourth node e, i.e. the voltage of the first plate of the second capacitor C2 is ve=0, and the second plate of the second capacitor C2 is connected to the sixth node g, i.e. the voltage of the second plate of the second capacitor C2 is vg=vdd, at which time the voltage difference between the two plates of the second capacitor C2 is VDD; since the voltage at the fifth node f is set to the high level voltage, and the corresponding fifth node voltage vf=vdd at the fifth node f. Accordingly, the second control signal of the second control sub-module is output as the high-level voltage signal vf=vdd.

Further, since the second node voltage vb=gnd=0, the seventh transistor M7 of the first control module 101, the fifteenth transistor M15 of the second control module 102, the seventeenth transistor M17 in the first substrate input module 801, the nineteenth transistor M19 in the second substrate input module 802 are turned off, and the first switching transistor 102 is turned off; since the fifth node voltage vf=vdd, the eighth transistor M8 of the first control module 101, the sixteenth transistor M16 of the second control module 102, the eighteenth transistor M18 in the first substrate input module 801, the twentieth transistor M20 in the second substrate input module 802 are turned off, and the second switching transistor 103 is turned off. Therefore, when the first clock signal ck is at a high level and the second clock signal ckb is at a low level, the gate voltage bootstrapping sample-and-hold circuit is in a hold state.

According to an embodiment of the present disclosure, when the first clock signal ck is at a low level and the second clock signal ckb is at a high level, in the first control module 101, the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5 are turned off, and the third transistor M3 and the sixth transistor M6 are turned on. At this time, since the first plate of the first capacitor C1 has no discharge path, the first capacitor C1 is in a floating state, and thus the corresponding first node voltage Va at the first node a remains GND unchanged. The voltage at the second node b is the same as the voltage at the third node c and both are kept in the floating state, so that the second node voltage Vb corresponding to the second node b is the same as the third node voltage Vc corresponding to the third node c, and the second node voltage Vb and the third node voltage Vc are both the voltage VDD before floating. At this time, the first electrode plate and the second electrode plate of the first capacitor C1 are in a floating state, the first electrode plate voltage is the first node voltage va=gnd, the second electrode plate voltage is the third node voltage vc=vdd, and the voltage difference between the two electrode plates of the first capacitor C1 is still VDD. Therefore, when the first clock signal ck is at a low level and the second clock signal ckb is at a high level, the first control signal outputted by the first control sub-module is vb=vdd.

According to the embodiment of the disclosure, the second node voltage vb=vdd corresponding to the second node b, and therefore, the seventh transistor M7 is in the on state, the input signal Vin may be input to the first node a through the seventh transistor M7, and at this time, the first node voltage va=vin corresponding to the first node a, and thus, the first signal input sub-module may be able to switch the input signal Vin into the first control sub-module.

According to the embodiment of the disclosure, when the corresponding first node voltage Va at the first node a changes from GND to Vin, at this time, the first end voltage of the first capacitor C1 changes from GND to Vin, and since the voltage difference between the two plates of the first capacitor C1 needs to be kept constant by VDD, the second plate voltage of the first capacitor, that is, the third node voltage Vc, is raised from VDD to vdd+vin, that is, vc=vb=vdd+vin, at this time, the first control signal output by the first control submodule is vdd+vin, and voltage bootstrap of the first capacitor C1 is completed.

According to an embodiment of the present disclosure, when the first clock signal ck is at a low level and the second clock signal ckb is at a high level, in the second control module 102, the ninth transistor M9, the tenth transistor M10, the twelfth transistor M12, the thirteenth transistor M13 are turned off, and the eleventh transistor M11, the fourteenth transistor M14 are turned on. At this time, since the first plate of the second capacitor C2 has no discharge path, the second capacitor C2 is in a floating state, and thus the fourth node voltage Ve corresponding to the fourth node e and the fifth node voltage Vf corresponding to the fifth node f are the same, and ve=vf=gnd=0, and the sixth node voltage vg=vdd corresponding to the sixth node g. At this time, the voltage of the first plate of the second capacitor C2 is the voltage ve=gnd=0 before the suspension of the fourth node voltage Ve, the voltage of the second plate of the second capacitor C2 is the sixth node voltage vg=vdd, and the voltage difference between the two plates of the second capacitor C2 is still VDD, so when the first clock signal ck is at a low level and the second clock signal ckb is at a high level, the second control signal of the second control submodule is output as the low-level voltage signal vf=gnd.

According to the embodiment of the disclosure, when the first clock signal ck is at a low level and the second clock signal ckb is at a high level, the corresponding second node voltage vb=vdd at the second node b, and thus the fifteenth transistor M15 is in an on state, the input signal Vin may be input to the sixth node g through the fifteenth transistor M15, and at this time, the corresponding sixth node voltage vg=vin at the sixth node g, and thus the second signal input sub-module may be able to switch the input signal Vin into the second control sub-module.

According to the embodiment of the present disclosure, when the corresponding sixth node voltage Vg at the sixth node g changes from VDD to Vin, at this time, the second plate voltage of the second capacitor C2 changes from VDD to Vin, and since the second capacitor C2 plate voltage difference needs to be kept constant by VDD, the first plate voltage of the second capacitor, i.e., the fourth node voltage Ve, is adjusted down from GND to Vin-VDD, i.e., ve=vf=vin-VDD. Therefore, when the first clock signal ck is at a low level and the second clock signal ckb is at a high level, the second control signal outputted by the second control submodule is vf=vin-VDD, so that the voltage down-regulation of the second capacitor C2 is completed.

Further, since the second node voltage vb=vdd+vin, the seventh transistor M7 of the first control module 101, the fifteenth transistor M15 of the second control module 102, the seventeenth transistor M17 in the first substrate input module 801, the nineteenth transistor M19 in the second substrate input module 802 are turned on, and the first switching transistor 102 is turned on; since the fifth node voltage vf=vin-VDD, the eighth transistor M8 of the first control module 101, the sixteenth transistor M16 of the second control module 102, the eighteenth transistor M18 of the first substrate input module 801, and the twentieth transistor M20 of the second substrate input module 802 are turned on, and the second switching transistor 103 is turned on, the on-resistances of the switches Vin to Vout transfer, vin to va transfer, and Vin to vg transfer are further reduced, and therefore, when the first clock signal ck is at a low level and the second clock signal ckb is at a high level, the gate voltage bootstrap sampling hold circuit is in a sampling state.

According to an embodiment of the disclosure, the voltage of the control electrode of the first switch tube is vin+vdd, and the voltages of the first end and the second end of the first switch tube are approximately equal and are both input signals Vin. The voltage difference between its gate and the first terminal is VDD and remains stable throughout the sampling period. Since the input signal Vin is injected into the substrate of the first switching transistor through the seventeenth transistor M17 and the eighteenth transistor M18, the voltage difference between the substrate and the first terminal of the first switching transistor is 0, so that the threshold voltage Vth1 of the first switching transistor is stabilized.

According to the embodiment of the disclosure, the voltage of the control electrode of the second switching tube is Vin-VDD, and the voltages of the first end and the second end of the second switching tube are approximately equal and are both input signals Vin. The voltage difference between the gate and the second terminal thereof is VDD, and since the input signal Vin is injected into the substrate of the second switching tube through the nineteenth and twentieth transistors M19 and M20, the voltage difference between the substrate and the second terminal of the second switching tube is 0 and remains stable throughout the sampling period, which stabilizes the threshold voltage Vth2 of the second switching tube.

The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.

Claims

1. A gate voltage bootstrapping sample-and-hold circuit comprising:

the first control module, the second control module, the first switching tube and the second switching tube;

the input end of the first control module is connected with an input signal and a clock signal, the output end of the first control module is connected to the control end of the first switching tube, and the first control module is configured to output a first control signal to the first switching tube based on the input signal and the clock signal;

the first end of the first switching tube is connected with the output end of the grid voltage bootstrap sampling and holding circuit and the first end of the second switching tube respectively, the second end of the first switching tube is connected with an input signal, and the first switching tube is configured to generate a first sampling signal under the condition of conduction based on the input signal and the first control signal;

the input end of the second control module is connected with the input signal and the clock signal, the output end of the second control module is connected to the control end of the second switching tube, and the second control module is configured to output a second control signal to the second switching tube based on the input signal and the clock signal;

The first end of the second switching tube is connected to the output end of the grid voltage bootstrap sampling and holding circuit, the second end of the second switching tube is connected to the input signal, the second switching tube is configured to generate a second sampling signal under the condition of conduction based on the input signal and the second control signal, and the first control signal and the second control signal are opposite-level signals, so that the first switching tube and the second switching tube are conducted simultaneously or are turned off simultaneously;

the output terminal of the gate voltage bootstrapping sample-and-hold circuit is configured to output a target signal based on the first sample signal and the second sample signal.

2. The gate voltage bootstrapping sample-and-hold circuit of claim 1 wherein the first control module comprises a first signal input sub-module and a first control sub-module,

the input end of the first signal input sub-module is connected with the input signal, and the output end of the first signal input sub-module is connected to the first control sub-module;

the input end of the first control sub-module is connected with the clock signal, and the output end of the first control sub-module is connected to the control end of the first switching tube.

3. The gate voltage bootstrapped sample and hold circuit of claim 2, wherein the clock signal includes a first clock signal and a second clock signal, the first clock signal and the second clock signal configured as opposite level clock signals; the first control submodule comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a first capacitor;

the control end of the first transistor is connected to the first clock signal, the first end of the first transistor is grounded, and the second end of the first transistor is connected to a first node;

the control end of the second transistor is connected to the first clock signal, the first end of the second transistor is grounded, and the second end of the second transistor is connected to a second node;

the control end of the third transistor is connected with a second clock signal, the first end of the third transistor is connected to the first node, and the second end of the third transistor is connected to the first end of the fourth transistor;

the control end of the fourth transistor is connected with the second clock signal, and the second end of the fourth transistor is connected with a power supply voltage;

The control end of the fifth transistor is connected to the second clock signal, the first end of the fifth transistor is connected to a third node, and the second end of the fifth transistor is connected to the power supply voltage;

the control end of the sixth transistor is connected to the first clock signal, the first end of the sixth transistor is connected to the second node, and the second end of the sixth transistor is connected to the third node;

a first plate of the first capacitor is connected to the first node, a second plate of the first capacitor is connected to the third node, the first plate potential of the first capacitor is configured to be determined based on a voltage corresponding to the first node, and the second plate potential of the first capacitor is configured to be determined based on a voltage corresponding to the third node.

4. The gate voltage bootstrapping sample-and-hold circuit of claim 2 wherein the first signal input submodule includes a seventh transistor, an eighth transistor, a control terminal of the seventh transistor connected to the second node, a first terminal of the seventh transistor connected to the first node and a first terminal of the eighth transistor, respectively, a second terminal of the seventh transistor connected to the input signal, a second terminal of the seventh transistor connected to a second terminal of the eighth transistor;

The control end of the eighth transistor is connected to the output end of the second control module, and the second end of the eighth transistor is connected to the input signal.

5. The gate voltage bootstrapping sample-and-hold circuit of claim 1 wherein the second control module comprises a second signal input sub-module and a second control sub-module,

the input end of the second signal input sub-module is connected with the input signal, and the output end of the second signal input sub-module is connected to the second control sub-module;

the input end of the second control sub-module is connected with the clock signal, and the output end of the second control sub-module is connected to the control end of the second switching tube.

6. The gate voltage bootstrapping sample-and-hold circuit of claim 5 wherein the second control submodule includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a second capacitor;

the control end of the ninth transistor is connected to the first clock signal, the first end of the ninth transistor is grounded, and the second end of the ninth transistor is connected to the first end of the fourteenth transistor;

The control end of the tenth transistor is connected to the first clock signal, the first end of the tenth transistor is grounded, and the second end of the tenth transistor is connected to a fourth node;

the control end of the eleventh transistor is connected to the second clock signal, the first end of the eleventh transistor is connected to the fourth node, and the second end of the eleventh transistor is connected to the fifth node;

the control end of the twelfth transistor is connected to the second clock signal, the first end of the twelfth transistor is connected to the fifth node, and the second end of the twelfth transistor is connected to the power supply voltage;

the control end of the thirteenth transistor is connected to the second clock signal, the first end of the thirteenth transistor is connected to a sixth node, and the second end of the thirteenth transistor is connected to the power supply voltage;

the control end of the fourteenth transistor is connected to the second clock signal, and the second end of the fourteenth transistor is connected to the sixth node;

a first plate of the second capacitor is connected to the fourth node, a second plate of the second capacitor is connected to the sixth node, the first plate potential of the second capacitor is configured to be determined based on a voltage corresponding to the fourth node, and the second plate potential of the second capacitor is configured to be determined based on a voltage corresponding to the sixth node.

7. The gate voltage bootstrapping sample-and-hold circuit of claim 5 wherein the second signal input subcircuit comprises a fifteenth transistor and a sixteenth transistor,

a control terminal of the fifteenth transistor is connected to the second node of the first control sub-circuit, a first terminal of the fifteenth transistor is connected to the first terminal of the sixteenth transistor and the sixth node, a second terminal of the fifteenth transistor is connected to the input signal, and a second terminal of the fifteenth transistor is connected to a second terminal of the sixteenth transistor;

the control terminal of the sixteenth transistor is connected to the fifth node, the first terminal of the sixteenth transistor is connected to the sixth node, and the second terminal of the sixteenth transistor is connected to the input signal, wherein the second node is configured as the output terminal of the first control module, and the fifth node is configured as the output terminal of the second control module.

8. The gate voltage bootstrapping sample-and-hold circuit of claim 1 further comprising a first substrate input module, wherein a first end of the first substrate input module is connected to the input signal, and a second end of the first substrate input module is connected to a third end of the first switching tube;

The first substrate module includes a seventeenth transistor and an eighteenth transistor,

a control terminal of the seventeenth transistor is connected to the second node, a first terminal of the seventeenth transistor is connected to the first terminal of the eighteenth transistor and a third terminal of the first switching transistor, a second terminal of the seventeenth transistor is connected to the input signal, and a second terminal of the seventeenth transistor is connected to a second terminal of the eighteenth transistor;

the control terminal of the eighteenth transistor is connected to the fifth node, the first terminal of the eighteenth transistor is connected to the first terminal of the seventeenth transistor and the third terminal of the first switching transistor, the second terminal of the eighteenth transistor is connected to the input signal, and the second terminal of the eighteenth transistor is connected to the second terminal of the seventeenth transistor.

9. The gate voltage bootstrapping sample-and-hold circuit of claim 1 further comprising a second substrate module, wherein a first end of the second substrate module is connected to the input signal and a second end is connected to a third end of the second switching tube;

the second substrate module includes a nineteenth transistor and a twentieth transistor,

A control terminal of the nineteenth transistor is connected to the second node, a first terminal of the nineteenth transistor is connected to the first terminal of the twentieth transistor and a third terminal of the second switching transistor, a second terminal of the nineteenth transistor is connected to the input signal, and a second terminal of the nineteenth transistor is connected to the second terminal of the twentieth transistor;

the control terminal of the twentieth transistor is connected to the fifth node, the first terminal of the twentieth transistor is connected to the first terminal of the nineteenth transistor and the third terminal of the second switching transistor, the second terminal of the twentieth transistor is connected to the input signal, and the second terminal of the twentieth transistor is connected to the second terminal of the nineteenth transistor.

10. The gate voltage bootstrapping sample-and-hold circuit of claim 1 wherein the first control signal is configured to be the same as a voltage value at the second node and the second control signal is configured to be the same as a voltage value at the fifth node.