JPS63316254A - Parallel processor - Google Patents

Abstract

PURPOSE:To increase efficiency to use a transfer channel by providing in a one-dimensional transfer channel plural switch circuits with a means to electri cally disconnect or connect a one-dimensional transfer channel. CONSTITUTION:One data transfer channel commonly used by plural processor elements PE1-PE3 is divided into the transfer channels P1-P3 of an arbitrary number and an arbitrary length by distributed and inserted switch circuits SW1-SW4. Switch circuits SW1-SW3 are constituted of a circuit regarding the transfer channel of right and left directions. A transfer circuit changing-over circuit SC electrically connects and disconnects a transfer channel DRi of an input side and a transfer channel D'Ri of an output side, based on a change-over controlling signal S from a transfer channel deciding circuit PD, a transfer channel is formed without depending on far and near transfer distances, in accordance with the transfer request of the processor elements PE1-PE3 asynchronously generated.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention has a small amount of hardware, is compact, has high efficiency in the use of transfer paths, and has no contention for transfer paths between arbitrary arithmetic processors. It relates to parallel processors that exchange data.

[Conventional technology]

As a device for mutually transferring data between a plurality of processors, a twelfth processor in which each processor uses a common transfer path is used.
The helical structure shown in the figure has the smallest amount of hardware and is a configuration that can be miniaturized as a parallel processor. However, in parallel processors using this bus, only two processors can use the transfer path at a time, and many other processors must suspend processing and wait until the transfer path becomes free.

Therefore, as the number of parallel processors increases, the total effective processing time including arithmetic processing and transfer increases significantly, resulting in a decrease in processing speed. In FIG. 12, PEI to PE6 are processor elements, BS is a bus, and AB is a bus arbiter.

[Problem that the invention seeks to solve]

On the other hand, in order to eliminate data conflicts on the transfer path, in a parallel processor loaded with a dedicated transfer device such as a loss bar switch C8 or a multi-stage switch as shown in Fig. It is possible to realize a transfer path with the processor and improve the efficiency and speed of transfer. However, the problem with such high-speed transfer devices is that
Signal lines are concentrated in the transfer device independently from all the processors, the number of connection cables becomes enormous, and the scale becomes unrealizable as the number of parallel processors increases.

The present invention has been made in view of these points, and its purpose is to simultaneously realize a large number of transfer paths, increase the efficiency of using each transfer path, and improve the effective processing speed of parallel processors. The object of the present invention is to provide a parallel processor that achieves both compactness and high speed of a transfer device.

[Means for solving problems]

In order to achieve such an object, the present invention configures a transfer path between a plurality of processor elements and any two processor elements of the plurality of processor elements, and transfers and transfers data.
A parallel processor comprising a transfer device that sends and receives information, which includes a one-dimensional transfer path and a plurality of switch circuits in the transfer path that have means for electrically disconnecting or connecting the one-dimensional transfer path. , a processor element is connected to each transfer path separated by a switch circuit.

[Effect]

The parallel processor according to the present invention is based on a bus structure with a small hardware scale, and can divide one signal transfer path into transfer paths of an arbitrary number and arbitrary length using switch circuits inserted in a distributed manner. enable. In addition, the transfer path itself can perform transfer path division and free space management control for use in a simple manner, and the transfer path can be dynamically changed in response to requests from the processor.
A large number of transfer paths between two processors can be secured at a time.

〔Example〕

The first feature of the present invention is that, as shown in FIG. 2, although one data transfer line is shared by a plurality of processor elements PE1 to PE3, switch circuits are distributed over one data transfer line. 5wt-5w4 are inserted, and the transfer paths PI, P2 . Processor elements PEl, PE2 . This is a configuration in which PE3 is connected.

The second feature of the present invention is that one transfer path can be arbitrarily divided and used as independent transfer paths, and that each processor element is configured as a transfer device without contention based on a transfer path use schedule. The point is that it has a means to automatically perform the diversion reservation procedure.

The third feature of the present invention is that the transfer is performed dynamically at the time when it is determined which available transfer paths are available, the occurrence of a request to use each processor element, and the transfer distance between the processor and the processor that requires data exchange. The point is that it has a control means that allows route setting.

This feature is that the transfer path is configured with transfer lines with independent directions of right and left, and the switch circuit arranged on the - dimension is configured to efficiently and automatically transfer signals by simply sending and receiving signals. , determines the starting point of the transfer path from the request signal from the previous stage and the request signal from the individually managed processor element,
As a result, a transfer path is formed in response to transfer requests of processor elements that occur completely asynchronously, and without depending on the required transfer distance between processor elements.

The fourth feature of the present invention is that the transfer path is configured with a plurality of signal lines, and the transfer of the previous stage is based on the information on the availability of the signal line of the next stage transfer path so that the signal line can be transferred between switch circuits. The switch circuit is configured with a circuit that independently connects the signal line of the transfer path and the signal line of the subsequent transfer path.

The configuration of a parallel processor as an embodiment of the invention described in claims 1 and 2 is shown in FIG. 1, a switch circuit is shown in FIG. 3, and a processing flow of the switch circuit is shown in FIG. FIG. 5 shows changes in the operating state of the switch circuit of the parallel processor, and FIG. 6 shows the transfer path interface of the processor element.

In FIG. 1, switches SW1 to SW3 are switch circuits inserted into a transfer path, and PEI to PE3 are processor elements connected to the transfer path sandwiched between the switch circuits. In FIG. 1, DR and DL are data transfer paths from left to right and from right to left, respectively, and QDR, AD
R, QDL, and ADL are left-to-right and right-to-left transfer route reservation information QD (Query Di
stance) and its transfer route confirmation information A D (Ac
required Distance). LR
eqR and LReqL are transfer request signals (Local
ReqR,L).

In FIG. 1, switch circuits SW1 to SW3 are constructed of circuits related to rightward and leftward transfer paths.

Figure 3 shows the switch circuit SWj (j=1.2.
・) This shows the circuit related to the rightward transfer path of S.
C is a transfer path switching circuit, and a transfer request processing circuit RP is also included.
and a transfer route determination circuit PD. The same applies to the rightward transfer path. Here, the transfer path switching circuit SC is a buffer BU that takes three values including high impedance.
Based on the switching control signal S from the transfer route determination circuit PD, the input side transfer route DRi (
i=0. 1. ..., m) and the output side transfer path D'
It electrically connects and disconnects Ri (i=0.1. . . . , m). Below, right and left subscripts R1
Omit L.

Next, the operation of the circuit shown in FIG. 3 will be explained.

1.1) Transfer request processing circuit RP receives RReqin from the previous switch and LReq from the connected processor element.
in is input.

1.2) RReqin inputs the remote bus state (Remote Path) to the flip-flop FFI.
5tate, RPS) and LReqi
n is the local bus state (LocalPath 5tate, L P S
). If there is a request from the processor element connected to the front-stage switch, RPS and LPS become 1.

1.3) Control logic means PCON (priority controller) monitors RPS, LPS. RPS has higher priority. When RPS=1, the origin (ORG) is set to O regardless of the LPS, and requests from connected processor elements are ignored. RReqout
Output RReqin to .

When RP, S = O, look at LPS. When LPS = 1, there is a request from the connected processor element, so 0RG
=1 (step 1.2 in FIG. 4).

When LPS=0, there is no request, so set 0RG=0 (step 1.3 in Figure 4) o RReqout=
0 is output.

Next, the operation of the circuit shown in FIG. 3 will be explained using FIG. 4.

Figure 4 shows the basic processing of the switch circuit, and depending on whether there is a request to use the transfer path from the processor element and the previous switch, and whether there is a match between the input information of the transfer route reservation information and the transfer route confirmation information, Transfer route reservation information QDout and transfer route confirmation information A to the processor element
Output Dout.

2.1) Q from the previous stage switch to the transfer path determination circuit PD
D in % ADin is input from the subsequent switch. QDout is output to the rear switch, and ADout and ACKR (coincidence signal) are output to the front switch.

2.2) Control logic means SD (Status Detector) monitors ORG and RReqout. RPS.

When both LPS are O (when moving from step 4 to step 5), 1 is added to ADin from the subsequent stage, and A Dout=A Din+ 1 is output to the previous stage switch circuit (step 5). Since there are no demands of their own,
It adds its own section to the number of empty sections in the subsequent section and transmits the result to the previous section. INC in FIG. 3 is an incrementer that adds 1.

2.3) If either RPS or LPS is 1, proceed to step 6. Steps 1 to 4) If 0RG = 0, destroy 1 in QD□ka from the previous stage (step 7),
Q Dout=Q D in 1 is output to the subsequent stage (steps 6 to 10). QDout indicates the number of requested sections and sets itself as the section, so this is subtracted and transmitted to the subsequent stage. DEC is a decrementer that subtracts 1. If 0RG = 1, the QD required by the contact EPB
in is output to the subsequent stage (step 9.10).

2.4) Also, ADin and QDout are compared, and as long as they do not match, regardless of ORG, if there is a transfer route request, A Dout-0 and ACK=0 are output to the previous stage (step 12.13). If they match, connect (turn on) the switch and A Dout=A Din+L AC
Output K=1 to the previous stage (step 14).

2.5) When either LPS or RPS is 1, if QDout=0, it is determined that the request transfer path is at the end, and at this time, the switch is disconnected (off) L, ADout
=0, ACK=1 in front, QDout=Q, RRe
Output q=o to the subsequent stage (step 15).

3.1) FIG. 5 shows the temporal transition of the outputs of QDout and ADout of eight switch circuits executed based on the basic processing shown in FIG. 4. In FIG. 5, initially ADout=FF (maximum value) for all switches SWi, which means that all sections in the subsequent stage can be used. QDout=0 because there is no request for a transfer path.

3.2) Now, assume that an origin occurs in the switch SWI at clock l and that the number of transfer path sections - 3 is requested. That is, the processor element PE connected to the switch SWI
Processor element PE connected from O to switch SW4
The case where a transfer request is made in 3 will be explained as an example. In this case, QDout=3. from switch SW1. ADout
=O is output.

Here, ADout-0 indicates that a transfer path cannot be formed from the switch SWI to the right side. Transfer route reservation procedure is started.

3.3) At clock 2, switch SW2 becomes switch S
At the request of WI, Q Dout= 2,' A D
Output out=0 (steps 9, 10, 12.1
3).

At clock 3, switch SW3 is QDout=1°A D
Output out=O (steps 9, 10, 12.1
3).

In Kuro-7ri4, RReq=1 is input to switch SW4, and QDout=0, so ADout-
〇, outputs ACK=1. ACK = 1 is passed to the previous stage (step 8.15).

3.4) At clock 5, ACK=1, switch SW3 adds 1 to ADout=0 of switch SW4,
Q Dout = A Dout = 1, the switch is turned on, and ACK = 1 (steps 6.7, 9, 10.12.14).

At clock 6, QDout=ADou at switch SW2
Outputs t-2, turns on the switch, and receives ACK.
= 1 is output to the previous stage (step 6゜7.9,10,
12.14).

At clock 7, QDout=ADou with switch SWI
Outputs t=3, turns on the switch, and ACKs
Output = 1 to the previous stage (step 6゜7.9, 11,
12.14).

Here, a transfer path from switch SWI to SW4 and from processor element PEI to PE4 is secured.

4.1) LRe from processor element PEI to PE4
By keeping q at 1, the Q of switches SWI to SW4
The states of DouL, A Dout and the switch on are kept unchanged (step 6.16), during which data transfer takes place.

5.1) When the data transfer is finished, processor element PEI sets LReq to O, that is, at clock 101, switch SWI sets LPS=O1ORG=0, RReqou
t=O (step 4.5), the control logic means SD of FIG. 3 detects this and immediately turns off the stitching, Q
Set Dout=0 (step 4.5). Transfer reservation cancellation is started.

5.2) By transmitting RReq to switches SW1 to SW4, at clock 102, RR from SWI is sent to switch SW2.
eqout-0 is input, QDout=O1ADou
At t=2, the switch turns off, and at clock 103, QDout of switch SW3=0,
A Dout = 1, switch off, clock 1
04, QDout=O, ADout of switch SW4
=FF (steps 4 and 5).

5.3) If 0RG=0 in switch SW3, RReqin=0 is set at clock 105 to the number of usable transfer path sections for the subsequent switch. That is, ADout=F F + 1 = F F (maximum usable section FF) is output (step 4.5).

At clock 106, switch SW3 switches to ADou of SW4.
Add 1 to t and output ADout.

At clock 107, switch SW2 switches to ADou of SW3.
Add 1 to t and output ADout.

At the clock 108, the switch SWI sequentially outputs ADout to which 1 has been added, and the release of the transfer path is completed here (steps 4 and 5).

Figure 6 shows the transfer path interface circuit of the processor element, in which a tri-state I/O is connected to the DR as the transfer path.
The transfer path check signal QD is connected to the 10 buffer B1, and the transfer path check signal QD is connected to the tristate input buffer B2.
D is connected to the output sofa B3, which is also tri-state. Transfer request signal LReq and ACK signal are directly connected to the switch circuit. In FIG. 6, a serial-parallel shift register SPR is used when bit length conversion is required. In the figure, IDE is an internal data bus, CDB is a control data bus, and 20 is an interface control circuit.

Next, specific effects of this embodiment will be explained.

In this case, as shown in FIG. 9, there are nine switch circuits and eight arithmetic processors (processor elements) PEO-PE.
Taking as an example a parallel processor consisting of 7 processors, we will compare it with a conventional bus configuration and a crossbar switch configuration.

In parallel calculations in Monte Carlo simulations, which are particularly difficult to speed up in device simulations, there is a problem in which all processors send data almost simultaneously to all other processors. Regarding this problem, the effects of this embodiment will be explained. Now, if one data is sent almost simultaneously from each of the eight processors to the other seven processors, in a parallel processor with a bus structure, as shown in FIG. 7, 28 transfers are required. In a parallel processor having a crossbar switch as the most ideal transfer device, only four transfers are required as shown in FIG. On the other hand, in the parallel processor of this embodiment, which is composed of one set of right-direction and left-direction transfer paths, as shown in FIG.
0 times, and if a parallel processor configuration with another set of transfer path configurations is adopted, the number becomes 10 times. The dotted line in FIG. 9 indicates the transfer path in other times, but this figure shows a case where it can be changed.

In general, the relational expression between the number of transfers and the number of cables in this embodiment when the number of processor elements is n and the number of transfer paths is 2'' is shown in the table. In the table, 2'' is the number of processor elements, and b is one transfer. is the bit width of the path. FIGS. 10 and 11 show the number of transfers and the number of cables when the number of processor elements is changed as a function of the number of transfer paths in this embodiment. The maximum number of transfer paths is 1/4 of the number required for a crossbar switch, and the transfer speed at this time is almost comparable to that of a crossbar switch. As can be seen from FIGS. 10 and 11, a great advantage of this embodiment is that the number of transfer paths can be changed arbitrarily depending on the scale of the device and the transfer speed requirements.

In this case, several combinations can be selected for the relationship between the number of transfers and the number of cables as shown in the table. Figure 10, 1st
In Figure 1, St, S3 are the characteristic lines of the crossbar switch, S2. S4 indicates the characteristic line of the normal bus, and 40.50 indicates the selection range in this embodiment.

〔Effect of the invention〕

As explained above, by arranging switch circuits distributed over one transfer path, the present invention can realize multiple transfer paths with arbitrary section lengths on one transfer path at the same time. Usage efficiency can be increased. In addition, the processor element connected to the transfer path looks at the section length information as the available transfer path information output from the switch circuit, and sends the necessary transfer section length information along with the transfer request signal, so that the transfer path is secured. If an ACK is received, the transfer path can be used. With such simple control, the necessary transfer paths between two processors can be dynamically changed by individual processor elements in the middle of processing, making it possible to achieve both high efficiency and high speed.

[Brief explanation of drawings]

FIG. 1 is a block system diagram showing an embodiment of a parallel processor according to the present invention, FIG. 2 is a block system diagram showing a parallel processor for explaining the invention in detail, and FIG. 3 is a block system diagram showing a switch circuit. System diagram, Fig. 4 is a flowchart showing the processing flow of the switch circuit, and Fig. 5 is an explanation showing the temporal transition of the outputs of QDout and ADout of the eight switch circuits executed based on the basic processing of Fig. 4. Figure 6 is a block system diagram showing the transfer path interface circuit of the processor element, Figure 7 is an explanatory diagram of the number of transfers in a parallel processor with a bus configuration, and Figure 8 is a parallel diagram of a crossbar switch configuration with bidirectional transfer paths. FIG. 9 is an explanatory diagram showing the number of transfers in a processor. FIG. 9 is an explanatory diagram showing the number of transfers in a parallel processor according to the present invention. FIGS. 12 is a block diagram showing a parallel processor with a conventional bus configuration, and FIG. 13 is a block diagram showing a parallel processor with a conventional crossbar switch configuration. PEI~PE3...processor element, SWI~SW4
...Switch circuit, DR, DL...Signal line, Pl~
P3... Transfer path, SC... Transfer path switching circuit, P, D
...Transfer route determination circuit, RP...Transfer request processing circuit, BUF...Buffer circuit, SD, PCON...Control logic means, INC...Incrementer, DEC...
・Decrementer, FFI, FF2...Flip-flop.

Claims (3)

[Claims] (1) In a parallel processor consisting of a plurality of processor elements and a transfer device that configures a transfer path between any two processor elements of the plurality of processor elements and transfers data and exchanges information, one-dimensional A transfer path and a plurality of switch circuits having means for electrically disconnecting or connecting the one-dimensional transfer path in the transfer path, and a processor element is connected to each transfer path separated by the switch circuit. A parallel processor featuring (2) A transfer path divided by a plurality of switch circuits has two sets of unidirectional data transfer directions, from left to right and from right to left, and a right direction and a left direction. Claim 1, characterized in that the switch circuit is constructed of a switch circuit having means for arbitrarily electrically connecting or disconnecting between a transfer path that inputs from the right and a transfer path that outputs to the right or left of the switch circuit. Parallel processors as described. (3) The processor element PEi connected to the transfer path Pi sandwiched between the i-th and i+1-th switch circuits is connected to the p section of the rightward or leftward transfer path up to the i+p or i-pth switch circuit. The switch circuit SWi has means for outputting transfer route reservation information for the transfer route in the right direction, and the switch circuit SWi outputs the transfer route reservation information for the transfer route in the right direction.
A request signal indicating whether or not a transfer path request is generated from the transfer path Pi is generated by inputting the transfer path use request signal of transfer path 1 and the transfer path request signal of transfer path Pi+1 from the arithmetic processor PEi connected to the transfer path Pi. It has a means for generating an original confirmation signal, outputs a transfer path use request signal of the transfer path Pi+1 to the i+1th switch circuit SWi+1 in the next stage, and transfers from the i+1th switch circuit to the leftward transfer path. Transfer path use request signal of path Pi-1 and transfer path Pi
A transfer request processing circuit inputs a transfer path request signal from the processor element PEi connected to the processor element PEi from the right and outputs a transfer path use request signal for the transfer path Pi-1; inputting transfer route confirmation information regarding the transfer route at that point from the switch circuit of the next stage, and using this to determine whether the transfer route requested from the previous stage has been secured to the next switch circuit;
a transfer route determination circuit that outputs a transfer route use permission signal (rightward) to a processor element connected to the previous transport route, and similarly outputs a transfer route use permission signal (leftward) for the leftward direction; Based on the transfer path request generation confirmation signal (right direction and left direction) generated in the request processing circuit and the transfer path usage permission signal (right direction and left direction) generated in the transfer path determination circuit, the previous stage request transfer path and the subsequent stage are determined. 2. The parallel processor according to claim 1, further comprising a transfer path switching circuit that electrically connects or disconnects the free transfer path.