JPS63314013A - Reactance circuit - Google Patents

Abstract

PURPOSE:To prevent oscillation from being generated, by providing first and second negative feedback type reactance circuits, and an input terminal connected commonly to the input terminals of those circuits. CONSTITUTION:The first negative feedback type reactance circuit 13 which represents positive equivalent reactance of a prescribed times the first reactance element (capacitor 20) by controlling a current on a first variable current source 16 is provided. Also, the input terminal 19 to the second negative feedback type reactance circuit 22 which represents negative equivalent reactance of the prescribed times the second reactance element (capacitor 26 and 27) by controlling the current on a second variable current source 25 is used commonly. In such a way, since no positive feedback path is prepared in the second reactance circuit 22, no oscillation is generated even when a large current is permitted to flow on the second variable current source 25.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a reactance circuit that can generate an equivalent reactance that changes from a predetermined negative value to a predetermined positive value, and particularly relates to a reactance circuit that can generate an equivalent reactance that changes from a predetermined negative value to a predetermined positive value. This invention relates to a reactance circuit suitable for frequency control.

(B) Prior art] A variable reactance circuit capable of generating an equivalent reactance that changes from a predetermined negative value to a predetermined positive value based on basic reactance elements such as capacitors and coils is disclosed in Japanese Patent Laid-Open No. 59-57515. It is completely described. FIG. 2 is a circuit diagram showing the variable reactance circuit, (1)
are first and second transistors (2) and (3) whose emitters are commonly connected, and the first and second transistors (2).
) and (3); a resistor (5) connected between the bases of the first and second transistors (2) and (3); 1st
A capacitor (6) connected between the base and collector of the transistor (2), and the first and second transistors (
and a current mirror circuit (7) connected between the collectors of transistors 2) and (3), and as a positive equivalent reactance when viewed from the input terminal (8) connected to the collector of the first transistor (2). The operating first reactance circuit and (9) are the third and fourth transistors (10) and (11) whose emitters are commonly connected, and the common emitter of the third and fourth transistors (10> and (11)). a second variable current source (12) connected to the second variable current source (12); a resistor (5) connected between the bases of the third and fourth transistors (10) and (11); )
and a current mirror circuit (7) connected between the collectors of the third transistor (11), and operates as a negative equivalent reactance when viewed from the input terminal (8) connected to the collector of the third transistor (10). This is the second reactance circuit.

Therefore, the reactance X of the first reactance circuit (1) that operates as a positive equivalent reactance is: X,=2ωgmRICr
(1), and the reactance X2 of the second reactance circuit (2) that operates as a negative equivalent reactance is L-2ωgfnRtc+.・・・・・・
......(2). In addition, the mutual conductance gm of the differential amplification section is
It can be expressed as (3), so the second
The reactance circuit shown in the figure has a positive reactance xI shown by the above equation (1) and a negative reactance X shown by the above equation (2), and the positive and negative reactances X and Xs can be said to be a variable reactance circuit that can be varied by changing the first and second variable currents m(4) and (12). Therefore, the variable reactance circuit of FIG. 2 changes linearly from a negative predetermined value to a positive predetermined value by appropriately adjusting the current flowing through the first and second variable current sources (4) and (12). You can get reactance.

(c) Problems to be solved by the invention However, the second reactance circuit (2) in FIG. 2 has a positive feedback loop, and in order to obtain a large negative reactance, the first variable current source (4) When turned off and the current flowing through the second variable current source (12) is increased, the gain of the differential amplifier circuit consisting of the third and fourth transistors (10) and (11) increases, potentially causing oscillation. was there.

That is, when the base voltage of the fourth younger transistor (11) increases in response to the input signal from the input terminal (8) and the collector current of the fourth transistor (11) increases by Δi,
Since the current on the input side of the current mirror circuit (7) increases by Δi, the current on the output side thereof also increases by Δi. On the other hand, the fourth
As the collector current of the transistor (11) increases, the collector current of the third transistor (10) decreases by Δi. Then, a high level voltage is generated at the input terminal (8) in response to the output current of 2Δi from the current mirror circuit (7). And the high level of heavy pressure is caused by a capacitor (
6) to the base of the fourth transistor (11), there was a possibility that oscillation would occur. In order to prevent the oscillation, for example, a phase correction capacitor may be inserted between the collector and base of the fourth transistor (11). This will form a negative feedback path and work to cancel out the oscillation. However, when the above-mentioned phase correction capacitor is inserted, a problem arises in that a positive feedback path is formed in the first reactance circuit (1) during operation of the first reactance circuit (1). That is, the first reactance circuit (1) originally includes the base of the first transistor (2), the collector of the second transistor (<3), the input side of the current mirror circuit (7), the output side of the current mirror circuit (Z),
A negative feedback path is formed by the capacitor (6) and the base of the first transistor (2). However, when a capacitor for phase correction as described above is inserted, the base of the first transistor (2), the collector of the second transistor (3), the capacitor for phase correction and the base of the first transistor (2) are connected to each other. A positive feedback path is formed in the loop,
There is a problem in that the negative feedback path has an adverse effect such as parasitic oscillation.

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned points. A first reactance circuit of a negative feedback type that exhibits a positive equivalent reactance by connecting the elements and controlling the operating current of the first and second transistors, and a third and fourth reactance circuit that are differentially connected. A negative feedback type in which a second reactance element is connected between the base of one of the transistors and a reference power source and the operating currents of the third and fourth transistors are controlled to exhibit a negative equivalent reactance. and an input terminal commonly connected to the input terminals of the first and second reactance circuits.

(*) Effect According to the present invention, the negative feedback type first reactance circuit exhibits a positive equivalent reactance that is a predetermined times that of the first reactance element by controlling the current flowing through the first variable current source. and a negative feedback type second reactance circuit that exhibits a negative equivalent reactance a predetermined times that of the second reactance element by controlling the current flowing through the second variable current source. Therefore, by appropriately adjusting the current flowing through the first and second variable current sources, it is possible to obtain an equivalent reactance at the input terminal from a negative predetermined value to a positive predetermined value.

(f) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention, and (b) shows first and second transistors whose emitters are commonly connected (
14) and (15), and the first and second transistors (
a first variable current source (16) connected to the common emitters of the first and second transistors (14) and (15);
A resistor (17) connected between the bases of (14) and (15)
) and (18), a first capacitor (20) whose one end is connected to the resistor (17) and the other end to the input terminal (19), and the first and second transistors (14) and (15).
and a current mirror circuit (c) connected between the collectors of the first transistor (14), the first reactance circuit operates as a positive equivalent reactance when viewed from the input terminal (19) connected to the collector of the first transistor (14). , and (η) are the third and fourth transistors whose emitters are commonly connected (
23) and (24), and the third and fourth transistors (
a second variable current source (25) connected to the common emitter of transistors 23) and (24); and a second capacitor (26) connected between the base of the third transistor (23) and point A.
) and a resistor (27), and the fourth transistor (24)
and a resistor (28) connected between the base of the third transistor (23) and the input terminal (19).
) and a current mirror circuit () connected between the collectors of the third and fourth transistors (23) and (24);
C), which operates as a negative equivalent reactance when viewed from the input terminal (19) connected to the collector of the third transistor (23).

Now, the first variable current source (16) has a current of 1. It is assumed that no current flows through the second variable current source (25). Then, the circuit in Figure 1 has the same configuration as the first reactance circuit (1) in Figure 2, and if the value of the resistor (17) is R1 and the value of the first capacitor (20) is C8, the input The positive equivalent reactance seen from the terminal (19) has a value equal to equation (1). Therefore, the current flowing through the first variable current source (4) is
Depending on the value, a variable reactance circuit is obtained that generates an equivalent reactance from zero to a positive predetermined value.

Next, assume that no current is passed through the first variable current source (4) and current I0 is passed through the second variable current source (12).In this state, the input signal of C6 is applied to the input terminal (19), If a current of jc flows through the coupling capacitor (29) accordingly, the current ic is as follows: IC=Zbluet ・・・・・・・・・・・・・・・・・・
...(4). In addition, composite impedance 2
□ and 2. is Z, = Ra + 17jωCI...
・・・・・・・・・・・・・・・・・・・・・(5) z, w
,-1 ・・・・・・・・・・・・・・・
...(6) It is expressed as 1/R+ + JωCa. The base voltage ec of the third transistor (23) is ec" f cL...
・・・・・・・・・・・・・・・(7) Then, the collector current i+ of the third transistor (23) is 11−gmec ・・・・・・・・・・・・・・・・
......(8) Therefore, by substituting equation (7) into equation (8), the collector current 11 becomes I I= gm 1 cZt ......・・・
・・・・・・・・・・・・・・・・・・(9) e to the input terminal (19). The current i flowing through the input terminal (19) when an input signal of is applied is 1=2i++ic
・・・・・・・・・・・・・・・・・・・・・・・・
(10) Therefore, by substituting the equations (4> and (9)) into the equation (10), the current i can be expressed as follows.

Here, in equation (10)′, Ra)1/ωc+, R,>1
By substituting the condition /ωCa, the current i becomes, and by further substituting the condition Ra)1/ωCa into the equation (10), the current i can be approximated as When viewed, the second reactance circuit (η) in Fig. 1 is composed of a resistor (31) with a resistance value Ra and a fill (32) with an induced reactance ωCaRa/2gm, as shown in Fig. 3. This shows that it is equivalently converted to a parallel circuit.

Furthermore, if gm is expressed as αI, /104 based on equation (3), the above-mentioned inductive reactance X is: X-ωCaRa(104/α1.)...
......(11), and it can be seen that by changing the current I0 of the second variable current source (25), the second reactance circuit (η) operates as a variable reactance circuit. .

Therefore, the first and second reactance circuits (S) and (η
) are connected as shown in Figure 1, and the first and second variable current sources (1
By varying the current flowing through 6) and (25), it is possible to provide a reactance circuit that can change the equivalent reactance seen from the input terminal (19) from a predetermined negative value to a predetermined positive value.

By the way, the second reactance circuit (η) in FIG. 1 does not have a positive feedback path. Therefore, the second variable current source (25)
There is no possibility that oscillation will occur even if the current flowing through is increased.

Further, the second reactance circuit (?2) has two negative feedback loops. Therefore, it has the advantage of stable operation.

In the embodiment shown in FIG. 1, a current mirror circuit (?l) is used.
We explained the case where the output is taken out as a load, but
A load such as a resistor may be connected between the collectors of the first and fourth transistors (14) and (23) and the power supply.

FIG. 4 shows another embodiment of the present invention, in which coils (33) and (34) are connected instead of the first and second capacitors (20) and (26) in FIG. Terminal (1
9) to generate an equivalent reactance from a predetermined negative value to a predetermined positive value. The circuit operation is similar to that shown in FIG. 1, and an equivalent reactance of a predetermined times the value of the coils (33) and (34) is generated at the input terminal (19). Therefore, the first and second variable current sources (16) and (25
), it is possible to obtain an equivalent reactance ranging from a positive predetermined value to a negative predetermined value.

(G) Effects of the Invention As described above, according to the present invention, a negative reactance circuit can be constructed without using a positive feedback loop, so the current flowing through the second variable current source can be increased and a large negative It is possible to prevent oscillation from occurring even when trying to obtain a reactance of . Therefore, when used in combination with a positive reactance circuit, the equivalent reactance can be adjusted over a wide range from a negative predetermined value to a positive predetermined value depending on the value of the current flowing through the first and second variable current sources. When used in combination with an oscillation circuit, the oscillation frequency can be stably controlled in positive and negative directions.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional variable reactance circuit, FIG. 3 is an equivalent circuit diagram of FIG. 1, and FIG. FIG. 3 is a circuit diagram showing another embodiment of the invention. (su)...first reactance circuit, (14)...
First transistor, (15)...Second transistor, (16)...First variable current source, (17)...Resistor, (19)...Input terminal, (20)...First transistor 1
Capacitor, (hereinafter)...Current mirror circuit, (η
〉...Second reactance circuit, (23)...Third
Transistor, (24)...Fourth transistor, (
25)...Second variable current source, (26)...Second capacitor, (27)...Resistor, (29)...Coupling capacitor, (30)...Resistor.

Claims (1)

[Claims] (1) A positive a negative feedback type first reactance circuit exhibiting equivalent reactance;
A negative a negative feedback type second reactance circuit configured to exhibit equivalent reactance; and an input terminal commonly connected to the input terminals of the first and second reactance circuits; and a reactance circuit characterized in that the equivalent reactance seen from the input terminal is changed from a predetermined negative value to a predetermined positive value by controlling the operating currents of the third and fourth transistors, respectively. .