JPS63313916A - Level conversion circuit - Google Patents

Abstract

PURPOSE:To level-convert a CMOS signal level into an ECL signal level at high speed with a simple circuit constitution by switching an ECL input bias voltage by a P type MOS transistor(TR), the gate input being a CMOS output signal, in a bipolar CMOS consolidation type integrated circuit device. CONSTITUTION:When a CMOS level input signal VI is a high level, the P type MOS TR M1 is in an OFF state, and the current of a constant current source IC1 flows in a resistor R1, and a bias potential VB goes to a potential which is a definite potential lower than VCC. Then, an ECL low level is inputted to the input of an ECL basic circuit, i.e., the base of a bipolar TR Q2, and the ECL low level is outputted to an ECL level output VO. Next, when the input signal VI goes to a low level, the P type MOS TR M1 goes to an ON state, and the current to flow in the constant current source IC1 flows in the P type MOS TR M1, and a bias potential VB goes to the potential, which is nearly close to the VCC. Accordingly, the input of the ECL bias circuit, i.e., the base of the bipolar TR Q2 goes to an ECL high level through an emitter follower circuit, and the output signal VO goes to the ECL high level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bipolar CMOS embedded integrated circuit device, and in particular, to a bipolar CMOS embedded integrated circuit device.

The present invention relates to a level conversion circuit for converting signal levels.

[Conventional technology]

In recent years, semiconductor integrated circuits incorporating bipolar and CMOS have been put into practical use, and it has become possible to create semiconductor integrated circuit devices that combine the characteristics of bipolar dual circuits, such as high speed, low power consumption, and high integration of 0M08 circuits. became.

[Problem that the invention seeks to solve]

In conventional semiconductor integrated circuit devices, when some circuits require high speed, all circuits are configured with bipolar transistors even though most other circuits do not require high speed. However, such semiconductor integrated circuits have disadvantages in that they have to sacrifice power consumption and circuit integration.

[Means for solving problems]

In order to solve the above-mentioned drawbacks, the present invention constructs a bipolar CMOS-embedded integrated circuit device in which the circuit portions that require high speed are configured with bipolar elements, and the circuit portions that do not require high speed are configured with CMOS elements. A level conversion circuit from the 4jtCMOS signal level to the ECL signal level is provided by a very simple circuit configuration in which the 9ECL input bias voltage is switched using a P-type MO8) resistor that uses the CMOS output signal as the gate input. It is something to do.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a first embodiment of the invention. VCC is a voltage source that provides the highest potential of the circuit, V) J is a voltage source that provides the lowest potential of the circuit, and V! is the CMOS level input signal, Vo
is an ECL level output signal, and Vref is an ECL reference potential. The ECL input bias potential VB is applied to the resistive element R, and the constant current source ICI, and the P-type M
O8) The gate of transistor M1 is a CMOS level input signal■! The source of the voltage source VccL is connected to the resistor hole 1 and the contact vBK of the constant current source ICI. The emitter follower circuit optionally composed of bipolar transistor Q1 and constant current source IC is Ml + "1 t
The level shift signal of the ECL input bias potential VB obtained by IC1 is transferred to the bipolar transistor Q*y Qs
y Q4 *Transmitted to the base of Ql of the ECL basic circuit composed of constant current source IC3mIC4 and resistor R8. still,
The base of Qs is connected to the ECL pin level Vref.

Next, the operation of this embodiment will be explained. First, CMOS level input signal V! is at a high level, the P-type MOS transistor M1 is off, and the current from the constant current source ICI flows through the resistor hole! The potential of VB flows through the emitter follower circuit composed of Ql and IC2, and the potential of VB is a constant lower potential than VCC.
4 p Engineering C3+ IC4* E composed of Rz
The ECL low level is input to the input of the CL basic circuit, that is, the base of Q2, and the ECL level output vo is the ECL low level.
L low level is output.

Next, when the CMOS level input signal v becomes low level, the P-type MO8 transistor M1 turns on.
The current flowing through the constant current source ICI flows as MIK, and the bias potential VB becomes almost a potential close to VCC. Therefore, input to the ECL basic circuit via the emitter 7 lower circuit,
The base of Q2 is ECL high level, output signal vo
ViECL becomes high level.

FIG. 2 shows the resistance value in the input bias potential setting circuit in FIG. is replaced with a diode DI, which improves the stability of the low level of VB and the high speed of switching.

[Effects of the Invention] - As explained above, the present invention enables high-speed level conversion from a CMOS level signal to an ECL level signal with a very simple circuit configuration. By employing the level conversion circuit according to the present invention, high speed bipolar 2 circuits can be achieved in bipolar CMOS embedded integrated circuits.

This has the effect of realizing a semiconductor integrated circuit device that has the features of the 0M08 circuit, such as low power consumption and high degree of integration.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG. 2 is a circuit diagram of a first embodiment of the present invention.
FIG. 3 is a circuit diagram of a second embodiment. vcc, vEE...Voltage source, Vr...
CMOS level signal, vo...ECI, level signal, VB...ECL input bias potential ref
...ECLIJ far/s potential, Ml-...
- P-type MOS transistor, Q++Q-, Q3. Q4・
... Bipolar transistor, Ic11 engineering C2+
IC3p Engineering C4... Constant current source, R,, R,
...Resistance element, DI- ...Diode.

Claims (1)

[Claims] In bipolar CMOS embedded integrated circuit devices, CM
A CMOS-ECL level conversion circuit characterized in that an ECL input bias voltage is switched by a P-type MOS transistor whose gate input is an OS output signal.