JPS59161920A - Logical circuit - Google Patents

Abstract

PURPOSE:To increase the working range of a CML circuit by varying the reference voltage in response to the variance of the current value of a constant current source of the CML circuit when it is produced. CONSTITUTION:The relation between load resistances R2 and R3 is set as R3= R2/2XalphaIc/alpha'I'c in order to obtain a fixed level of reference voltage Vref when the current Ic flowing to a constant current source Qc is set at alpha times as much as the designed value and the current I'c is set at alpha' times as much as the designed value owing to the variance of production. For two current sources consisting of FETs at the places close to each other on a crystal, either one of these two current values also varies if the other value varies owing to the variance of production. Therefore alpha and alpha' are approximately equal to each other. The value of the Vref is set between VH and VL despite the variance of the Ic value as long as R3=R2/2XIc/I'c is satisfied.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a logic circuit, and particularly to a current switching type logic circuit (hereinafter abbreviated as CML circuit) that has an expanded operable range against manufacturing variations.

[Prior art]

FIG. 1 is an example of a conventionally known CML circuit.

In Figure 1, % Qt + Qt is the current switching FET
, Qc are constant current source FETs, R, , R.

is the load resistance, Do, D are level shift diodes, Q, , , Q. is a constant current source FET in the output section. A is an input terminal to which an input voltage (In) is applied; %Bl is an output terminal from which an output voltage Vout4τi is applied, and C is a reference voltage input terminal to which a constant voltage terminal ir@f is applied. Ic is the current flowing through the constant current source Qc, Vs is Do
, Do, the forward voltage drop due to *IO is the current flowing through the constant current source Q,o, Q,o. Usually R3 and Rt -Qt and Q, t -Do and Do, Qo and Q.

f″i, are designed to have the same size. Here, V
When ln is low by ■r・f, Ql is blocked,
All ICs are fed through Rt, Qt. Therefore R
The voltage drop caused by 1 is different from that of the IC, and the voltage Vout generated at the output terminal B becomes -RtIcVs. (However, the voltage drop due to ■ flowing through R is ignored.) At this time,
The voltage ■out generated at the output terminal B is -Vg.

Further, when vIn is higher than vr cost f by υ light, Qt is cut off and Ic is all supplied through Rt - Qt.

In this case, Vout is -V B and V out is -R
I IC-VII, the output relationship is reversed. ■Ir
The relationship between I and vout is determined by the following equation.

However, β is a mutual conductance coefficient of F ET Q+ and Ql. Also, the value of Vout is V in the above equation.
It is expressed by a formula in which lll and V r@f are exchanged, and v, o
It is an inverted version of ut. Usually, ■ref is v, out
It is designed to have an intermediate value between the noi level (Vi) and the low level (VL), that is, the following. FIG. 2 shows the calculation of the first equation under these conditions. In FIG. 2, the horizontal axis shows the input voltage, and the vertical axis shows the output voltage. X and Y are each vout
, V out, while x' and y' are respectively X
, the input voltage and output voltage of Y are swapped □. The intersections P, Q, and R of X and Y' indicate the operating point at the low level (VL), the operating point at the high level (Vn), and the logical threshold point of V.at. Also, Y and Y
’ intersection point 8. T is the operating point of V out at VL and Vi.

However, the circuit shown in FIG. 1 has the following drawbacks. When a constant current source is configured with FETs as in the circuit shown in Figure 1, the current Ic flowing through the constant current source is
It is determined by the threshold voltage Vt of the UFET and the mutual conductance coefficient β, but these values vary greatly depending on variations in manufacturing conditions. In particular, IC is V2O3
Since it changes as a power, it is sensitive to fluctuations in Vy, and as a result, the value of Ic varies widely even in ECL circuits using Si bipolar elements. For example, consider a case where Ic decreases to 80% of the design value due to manufacturing variations.
: In this case, the input/output characteristics shown in FIG. 2 change as shown in FIG. 3, and the intersection point P between X and Y' disappears, making it impossible to operate as a logic circuit. Also, the IC is 180% of the design value.
In this case, the input/output characteristics become as shown in FIG. 4, and in this case as well, operation as a logic circuit becomes impossible.

[Purpose of the invention]

An object of the present invention is to provide a CML circuit that has a wide operable range with respect to variations in manufacturing conditions.

[Summary of the invention]

The present invention is characterized in that the operational range of the CML circuit is expanded by changing the reference voltage in response to manufacturing variations.

[Embodiments of the invention]

FIG. 5 shows an embodiment of the present invention. The circuit of this embodiment is different from the conventional circuit shown in FIG. 1 in that the potential V ref at six points changes depending on the value of IC'. In Figure 5, QC' is the second constant current source FET
, R, is the load resistance, Dr is the level shift diode, D
is a terminal to which a further voltage vO is applied. Ic' is QC
2B' is the forward voltage drop caused by the diode l)r. Other details are the same as in Figure 1. In this example circuit, V r@f is V r@f = Vo Rrs Ic 'Vs
' ---(3), which changes depending on the value of c'. Here, the value of V r@f is as described above ((
2) Since it is necessary to set the value between Vm and vL as shown in equation (2), V should be set as follows. e Set the value of Vs'*R.

When Ic is the designed value, the values of vr·f in equations (2) and (3) are the same, and the circuit of the present invention has the same DC characteristics as the conventional circuit. Next, consider a case where Ic varies due to manufacturing variations. Ic is α times the design value,
IC' changes to α' times the design value, αIc and α, respectively.
Suppose that it becomes 'IC'. In this case, equation (2) is “Va −RnαIc ・・・・・・・・・
・・・・・・It changes as shown in (5), and the equation (3) is V r@f = vo 7B4(1'Ic ' - Vg
''' = (6). Therefore, the condition for making the values of V r@f in equations (5) and (6) equal is as follows. If the current values of the two constant current sources fluctuate due to manufacturing variations, the other will fluctuate in the same way.Therefore, the above-mentioned α
and α′ are almost equal.

Therefore, if R1 is set to the value of equation (4), even if the value of Ic changes, the V refO value will be an intermediate value between Vi and VL. FIG. 6 shows the input/output characteristics when the value of Ic is reduced to 80% of the designed value under this condition. The meaning of each symbol in FIG. 6 is the same as in FIG. 2. In this case, P and Q are the operating points for Vs, , Vm of the output vout, respectively, and S and T are the operating points of the output port Vt, , Vm.
A logical operation is possible as an operating point for a. Moreover, FIG. 7 shows the input/output characteristics when the value of Ic increases to 180% of the design value. In this case as well, logical operation is possible.

Note that in the above explanation, manufacturing variations in the forward voltage drop of the diodes are ignored, but even if this cannot be ignored, there is no problem because the variations in Vs and Vs' cancel each other out. Further, as shown in FIG. 8, even if source followers Q and stσB are inserted in the output extraction portion, the operating principle remains the same. Further, in the present invention, as shown in FIG. 9, a source follower 8F may be provided between the current switching section and the reference voltage input section. Furthermore, as shown in FIG. 10, all or part of the level shift diode Dr may be provided in the source follower SF, and the operating principle is the same in this case as well. Furthermore, in the above embodiment, Q, t +Q
t e Qc + Qc ' * Q, o + Q, o
Although the case where these FETs are Schottky junction FETs has been described, it goes without saying that these FETs may be MO8 type FE'l' or PN junction FETs. Furthermore, even if the first element is composed of a resistor, the principle of operation remains the same.

Furthermore, the number of diodes is not limited, and the diodes D, D, and Dr may not be provided, or only one diodes may be provided. Furthermore, as shown in Figure 11, the input FE
It is clear from the operation mode of the present invention that two or more T may be provided.

〔Effect of the invention〕

As described above, the present invention enables operation as a logic circuit even under conditions where the current value of the constant current source fluctuates due to manufacturing variations, making it impossible for conventional circuits to operate as a logic circuit. .

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a conventional example, Figures 2 to 4 are diagrams showing the input/output characteristics of the circuit, Figure 5 is a circuit diagram showing an embodiment of the present invention, and Figures 6 and 7. is a diagram showing input/output characteristics of a logic circuit according to the present invention, and FIGS. 8 to 11 are circuit diagrams showing main parts of other embodiments of the present invention. A...Input terminal, B, B...Output terminal, C...Reference voltage input terminal, D...Terminal for applying constant voltage, Q, s t
Q, t lQc = Q, c'-Qo -Qo...
-FET%Rt, R1. R3...Load resistance L Do, Do, D,...
・Level shift'￥I 1 Figure Y 2 Oral input electrician's release 32 田Vpe+1- 人力电纫 4 Orally input electrician 1 Rokuka electrician 7 Figure 49

Claims (1)

[Claims] 1. First and second gallium arsenide field effect transistors (GaAsF) whose source electrodes are commonly connected to each other.
ET), a first resistance element connected between the drain electrode of the first GaAsFET and the high potential power supply, and a first resistance element connected between the drain electrode of the second QaAsFET and the high potential power supply. a third GaAsFET whose drain electrodes are connected to the source electrodes of the first and second QaAsFBTs and whose source and gate electrodes are connected to a low potential power supply; a fourth GaA electrode connected to the low potential side power supply;
sFET, a third resistance element provided between the drain electrode of the fourth QaAsPET and the constant voltage terminal, and a third resistance element for level-shifting the potential of the drain electrode of the fourth QaAsFET. 1. A logic circuit comprising means for connecting a drain electrode of the fortieth FET and a gate electrode of the second FET.