JPS6331309A - Differentiation circuit - Google Patents
Differentiation circuitInfo
- Publication number
- JPS6331309A JPS6331309A JP17595986A JP17595986A JPS6331309A JP S6331309 A JPS6331309 A JP S6331309A JP 17595986 A JP17595986 A JP 17595986A JP 17595986 A JP17595986 A JP 17595986A JP S6331309 A JPS6331309 A JP S6331309A
- Authority
- JP
- Japan
- Prior art keywords
- transistors
- differential
- circuit
- transistor
- collector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004069 differentiation Effects 0.000 title 1
- 238000010586 diagram Methods 0.000 description 10
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明は差動回路に関する。[Detailed description of the invention] Industrial applications The present invention relates to differential circuits.
従来の技術
従来の技術としては、第7図に示すようなトランジスタ
3個を1つの定電流源で恥!/)Jする回路がある。Conventional Technology Conventional technology uses three transistors as shown in Figure 7 in one constant current source! /) There is a circuit that does J.
発明が解決しようとする問題点
しかしながら、上述した従来の回路は、トランジスタ3
個の各々のベースを入力としているので、2個号を差動
入力で受けることは出来ないという欠点がある。Problems to be Solved by the Invention However, the conventional circuit described above
Since the bases of each number are used as inputs, there is a drawback that it is not possible to receive two numbers by differential input.
本発明は従来の上記実情に鑑みてなされたものであり、
従って本発明の目的は、従来の技術に内在する上記欠点
を解消することを可能とした新開な差υ1回路を提供す
ることにある。The present invention has been made in view of the above-mentioned conventional situation,
Accordingly, an object of the present invention is to provide a novel difference υ1 circuit which makes it possible to eliminate the above-mentioned drawbacks inherent in the conventional technology.
問題点を解決するための手段
上記目的を達成する為に、本発明に係る差動回路は、2
対のトランジスタ対と、1つの定電流源とを具備して構
成される。Means for Solving the Problems In order to achieve the above object, the differential circuit according to the present invention has two
It is configured to include a pair of transistors and one constant current source.
実施例
次に1本発明をその好ましい一実施例について図面を参
照して具体的に説明する。Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.
第1図は本発明の第1の実施例を示す回路構成図である
。FIG. 1 is a circuit configuration diagram showing a first embodiment of the present invention.
第1図を参照するに、トランジスタQ1. Q2は第1
の差動対を構成し、トランジスタQ3、Q4は第2の差
動対を構成し、2つの差動対は定電流源IOを共有して
いる。第1図に示すように、2つの差動入力V1.V2
を持っている。Referring to FIG. 1, transistor Q1. Q2 is the first
The transistors Q3 and Q4 constitute a second differential pair, and the two differential pairs share a constant current source IO. As shown in FIG. 1, two differential inputs V1. V2
have.
第2図は本発明の第2の実施例を示し、第1図の各トラ
ンジスタにエミッタ抵抗を挿入して各差動対の利得と各
トランジスタ間の入力オフセットの影響を小さくした回
路例である。FIG. 2 shows a second embodiment of the present invention, and is an example of a circuit in which an emitter resistor is inserted into each transistor in FIG. 1 to reduce the influence of the gain of each differential pair and the input offset between each transistor. .
今第1図、第2図において、各トランジスタのベース電
圧をvB、、 vB、、 VBs、VB、として、トラ
ンジスタQlのコレクタと02のコレクタを接続し。Now, in FIGS. 1 and 2, the base voltages of each transistor are set as vB, , vB, , VBs, and VB, and the collector of transistor Ql and the collector of transistor 02 are connected.
トランジスタQ3とQ4のコレクタを接続し。Connect the collectors of transistors Q3 and Q4.
VB3 = VB4 = 1/2 (VBI + VB
、)とすれば、入力V□に対してコレクタ電流Ic3+
Ic、の電流およびIC1+IC4の電流は互いに逆相
の2逓倍波形となる。VB3 = VB4 = 1/2 (VBI + VB
), then the collector current Ic3+ for the input V□
The current of Ic and the current of IC1+IC4 have double waveforms with mutually opposite phases.
第3図にこのときの回路図を示し、第4図に波形を示す
。FIG. 3 shows a circuit diagram at this time, and FIG. 4 shows waveforms.
第5図は本発明の応用回路例であり、マルチプライヤ回
路の例を示す。FIG. 5 is an example of an application circuit of the present invention, and shows an example of a multiplier circuit.
第6図にR1=R,、R,=n、、 R,=R,として
出力特性を示す。FIG. 6 shows the output characteristics as R1=R, R,=n, and R,=R.
発明の詳細
な説明したように、本発明によれば、2対のトランジス
タ対が1つの定電流を共有することにより、差動入力の
2信号を入力出来る効果が得られる。As described in detail, according to the present invention, two pairs of transistors share one constant current, thereby achieving the effect that two differential input signals can be input.
第1図は本発明の第1の一実施例を示す回路構成図、第
2図は本発明の第2の実施例を示し、エミッタ抵抗を挿
入した例として示した回路構成図、第3図は本発明の一
応用例として2逓倍回路を例に示した回路図、第4図は
第3図の特性図、第5図は本発明の一応用例としてマル
チプライヤ回路を例に示した回路図、第6図は第5図の
入出力特性を示す図、第7図は従来回路例を示す図であ
る。FIG. 1 is a circuit configuration diagram showing a first embodiment of the present invention, FIG. 2 is a circuit configuration diagram showing a second embodiment of the invention as an example in which an emitter resistor is inserted, and FIG. 3 is a circuit diagram showing a second embodiment of the invention. is a circuit diagram illustrating a double multiplier circuit as an example of an application of the present invention, FIG. 4 is a characteristic diagram of FIG. 3, and FIG. 5 is a circuit diagram illustrating a multiplier circuit as an example of an application of the invention. FIG. 6 is a diagram showing the input/output characteristics of FIG. 5, and FIG. 7 is a diagram showing an example of a conventional circuit.
Claims (1)
とする差動回路。A differential circuit characterized by two pairs of transistors having one constant current source.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17595986A JPS6331309A (en) | 1986-07-25 | 1986-07-25 | Differentiation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17595986A JPS6331309A (en) | 1986-07-25 | 1986-07-25 | Differentiation circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6331309A true JPS6331309A (en) | 1988-02-10 |
Family
ID=16005249
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17595986A Pending JPS6331309A (en) | 1986-07-25 | 1986-07-25 | Differentiation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6331309A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5396131A (en) * | 1992-03-05 | 1995-03-07 | Mitsubishi Denki Kabushiki Kaisha | Differential amplifier, comparator and high-speed A/D converter using the same |
JP2014517659A (en) * | 2011-06-20 | 2014-07-17 | ザ リージェンツ オブ ザ ユニヴァーシティー オブ カリフォルニア | Nerve amplifier |
-
1986
- 1986-07-25 JP JP17595986A patent/JPS6331309A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5396131A (en) * | 1992-03-05 | 1995-03-07 | Mitsubishi Denki Kabushiki Kaisha | Differential amplifier, comparator and high-speed A/D converter using the same |
JP2014517659A (en) * | 2011-06-20 | 2014-07-17 | ザ リージェンツ オブ ザ ユニヴァーシティー オブ カリフォルニア | Nerve amplifier |
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