JPS63311874A - Error correction circuit - Google Patents

Abstract

PURPOSE:To eliminate the level inclination of an output on the way of convergence when the loop is made stable by providing a pulse output circuit outputting the 1st voltage of a prescribed value when a pulse signal is generated and the code of an error signal is positive and outputting the 2nd voltage when negative and bringing the output at a high impedance during other period. CONSTITUTION:In obtaining, e.g., a pedestal control signal by a pulse signal, if the sign of the error signal 24 is positive, the 1st voltage of prescribed value is outputted and the 2nd voltage different from the 1st voltage when negative and the output is brought into a high impedance when no pulse signal is generated by the pulse output circuit 58, which is provided between an integration circuit 59 and a PWM generation circuit 57. Thus, the output of the integration circuit 59 is held during the luminance signal period in the process at convergence and held even after the convergence, then the production of gradient in the brightness having taken place in a conventional circuit is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an error correction circuit used in a digital television receiver or the like.

(Prior Art) In recent years, advances in semiconductor technology have led to advances in technology for digitizing and processing video signals.

When converting a video signal into a digital video signal using an analog-to-digital converter, in order to effectively utilize the dynamic range of the analog-to-digital converter, it is necessary to regenerate the DC component lost during signal transmission. The clamp circuit is a circuit that controls the pedestal level, which is the DC reference level of the video signal, to a predetermined value in order to reproduce this DC component.

FIG. 3 is a conventional clamp circuit for digital video signals. Analog video signal 11 is sent to analog adder 1
2. The analog adder 12 adds the analog video signal 11 and the clamp control signal 13,
A DC-controlled analog video signal 14 is obtained at its output.

This analog video signal 14 is supplied to an analog-to-digital converter 15, where it is digitized and output as a digital video signal 16.

The synchronization separation circuit 18 receives the analog video signal 11, separates the synchronization signal, and outputs a composite synchronization signal 19. The composite synchronization signal 19 is supplied to a timing generation circuit 20, and this circuit 20 outputs timing signals 21, 22, 23, etc. necessary for the entire circuit according to the composite synchronization signal 19. The pedestal error detection circuit 17 detects a pedestal level, which is a DC reference level, from the digital video signal 16 using a timing signal 21, calculates the difference from the target pedestal level, and outputs a pedestal error signal 24.

Pedestal error signal 24 is supplied to error integration circuit 25 . The error integration circuit 25 performs integration processing on the pedestal error signal 24 in synchronization with the timing signal, and plays the role of providing a time constant to the clamp loop, and outputs its integral output (clamp control amount is shown as a digital value). as the clamp signal 26 as a pulse width modulated wave (hereinafter referred to as PWM)
It is supplied to the generation circuit 27.

The PWM generation circuit 27 converts the clamp signal 26 into a PWM signal, that is, generates a pulse width modulated wave with a duty according to the value of the clamp signal 26, and outputs this as a PWM clamp signal 28.

The PWM clamp signal 28 is smoothed by an analog integration circuit 29 consisting of a resistor R and a capacitor C, converted into the above-mentioned clamp control signal 13, and supplied to the adder 12.

That is, the PWM generation circuit 27 and the analog integration circuit 2
9, the clamp signal 26 which is a digital signal becomes the clamp control signal 13 which is an analog voltage.

The clamp loop described above controls the DC level of the analog video signal 14 so that the pedestal error signal 24 is zero, that is, the pedestal level of the digital video signal 16 matches the target value.

The digital video signal 16 subjected to DC reproduction is subjected to various signal processing (luminance, chromaticity separation,
color amplitude control, etc.), and is converted into analog RGB signals or brightness and color signals by a digital-to-analog converter 31.

In the clamp circuit described above, the pedestal error is detected from the digital video signal, and the clamp loop functions so that this error becomes zero.

For this reason, automatic adjustment is performed that includes variations in the characteristics of the analog-to-digital converter 15 and variations in element values due to temperature changes, conversion over time, and the like. Furthermore, since the digital clamp signal is first converted into pulse width information by the PWM generation circuit 27 and then converted into an analog clamp control signal by an inexpensive smoothing integration circuit, the clamp loop requires an expensive digital/analog signal. It has the advantage of not requiring a converter.

(Problems to be Solved by the Invention) Although the conventional digital video signal clamp circuit has the above advantages, it also has the following problems.

FIG. 4 shows signal waveforms at various parts of a conventional clamp circuit. FIG. 4(a) shows the input analog video signal 11, which shows an example in which the intermediate level of the luminance signal is flat. FIG. 2B shows the digital video signal 16, in which the pedestal level has converged to the target pedestal level due to the action of the clamp loop. The same figure (C) shows the PWM clamp signal,
This pulse width indicates the clamp control amount.

FIG. 4(d) shows the smoothed clamp control signal 13, but as shown in the figure, there is a slope in the portion that could not be completely smoothed by the analog integration circuit 29. Since this is also added to the digital video signal 16 in FIG. 4(b), the digital video signal 16 has a slope in its brightness portion, which should be flat, resulting in significant deterioration on the screen. If the time constants of the two analog integration circuits are increased in order to improve this, the convergence time of the clamp loop becomes longer, making it impossible to follow fluctuations in the DC level of the analog video signal, and practical performance cannot be obtained.

Therefore, the present invention has an object to prevent an output level slope from occurring during convergence when the loop is stabilized in an error i correction loop such as the one described above in which a control signal is obtained by smoothing a PWM signal with an analog integrator. To provide an error correction circuit that has good followability for fluctuations in the DC level of an input signal, absorbs fluctuations due to aging, temperature changes, and element variations in an analog-to-digital converter, and can be realized with an inexpensive configuration. With the goal.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides an error detection circuit to which a signal under test is supplied and digitally obtains an error signal with respect to a reference signal; a value circuit, a pulse width modulated wave generation circuit that generates a pulse signal with a width according to the magnitude of the output of the absolute value circuit, and a period during which the pulse signal is generated;
If the sign of the error signal is positive, the predetermined first voltage is
A pulse output circuit that outputs a second voltage different from the first voltage when the voltage is negative and whose output is high impedance during a period when the pulse signal is not generated, and a loop using the output of the pulse output circuit as input. a loop filter that determines the convergence time constant of the signal under test, and a loop filter that directs the output of the loop filter in the direction in which the error between the signal under test and the reference signal becomes zero.
and means for supplying the constant signal to the control section of the circuit that outputs the constant signal.

(Function) When obtaining, for example, a pedestal control signal using a pulse signal by the above means, a predetermined first voltage is applied when the sign of the error signal is positive, and a second voltage different from the first voltage is applied when the sign of the error signal is negative. Since a pulse output circuit is provided between the integrating circuit and the PWM generating circuit, which outputs a high impedance output during the period when the pulse signal is not generated, the output of the integrating circuit is is held, and is also held after convergence, so the brightness gradient as in the conventional case does not occur.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows one embodiment of the invention, in which an analog video signal 11 is directed to an analog adder 12. An analog adder 12 adds the analog video signal 11 and the clamp control signal 13, and a DC-controlled analog video signal 14 is obtained as its output. This analog video signal 14 is supplied to an analog-to-digital converter 15, where it is digitized and becomes a digital video signal 16, which is outputted at 4.

The synchronization separation circuit 18 receives the analog video signal 11, separates the synchronization signal, and outputs a composite synchronization signal 19. The composite synchronization signal 19 is supplied to a timing generation circuit 20, and this circuit 20 outputs timing signals 41, 42, etc. necessary for the entire circuit according to the composite synchronization signal 19.

The pedestal error detection circuit 17 detects a pedestal level, which is a DC reference level, from the digital video signal 16 using a timing signal 41, calculates the difference from the target pedestal level, and outputs a pedestal error signal 24.

Pedestal error signal 24 is supplied to error absolute value circuit 55. The error absolute value circuit 55 receives the pedestal error signal 2.
The numerical value bit N1 or its inverted numerical value bit N2 is selected and derived according to the sign bit PR indicating positive or negative of 4. The inverter 55a inverts the numerical bits, and the selector 55b makes the selection. The selector 55b selects a numerical value when the sign bit PR is positive.
Select l, and if it is negative, select numerical bit N2 to derive. Error absolute value 5 output from error absolute value circuit 55
6, one bit of "1" level signal is added to its LSB side. This prevents the error signal from becoming zero,
This is to improve the influence of jitter due to the detection dead zone due to the resolution of the analog-to-digital converter 15.

The PWM generation circuit 57 generates a pulse having a width corresponding to the absolute error value 56 and supplies it to the pulse output circuit 58. The pulse output circuit 58 includes an AND circuit 58a158b to which an output pulse is supplied to one input terminal, and a previous sign bit P.
It is composed of inverters 58c and 58d that introduce R, and switches SWI and SW2 that are turned on or off by the output of each AND circuit 58a158b. The pulse output circuit 58 outputs the AND circuit 5 when the sign bit PR indicates positive.
8a is closed and AND circuit 58b is open. When the sign bit PR indicates a negative value, AND circuit 58a is open and AND circuit 58b is closed.

Therefore, a pulse having a width corresponding to the value of the pedestal error signal 24 is obtained from the AND circuit 58a or 58b.

Switch SWI outputs a positive voltage when turned on,
Further, the switch SW2 outputs the ground voltage when turned on. The outputs of the switches SW1 and SW2 are supplied to an analog integration circuit 59 consisting of a capacitor C and a low resistance.

In this case, the integrating circuit 59 is in a manually operated state only when the switch is on, and is in a hold state during other periods. In other words, on the input side, when the switch is off, the impedance is infinite.

The above pedestal control loop detects the pedestal error from the digital video signal and outputs the pedestal error signal 2.
It functions so that 4 becomes zero. The DC-regenerated digital video signal 16 is subjected to various signal processing (brightness, chromaticity separation, color amplitude control, etc.) in a video signal processing circuit 30.
The digital-to-analog converter 31 converts the signals into analog RGB signals or luminance and color difference signals.

Next, the operation of the clamp circuit will be further explained with reference to FIG.

2(a) shows the waveform of the input analog video signal 11, and FIG. 2(b) shows the digital video signal 16. In this example, the DC level deviates significantly in the positive direction in the initial state, and a large positive pedestal level error is detected. Therefore, as shown in FIG. 2(C), no output is output from the AND circuit 58a, and a pulse corresponding to the pedestal error is output from the AND circuit 58b. This pulse brings the terminal of the switch SW2 to ground voltage, and when the switch SW2 is turned on, the charge stored in the capacitor C of the integrating circuit 59 is discharged. As a result, the level of the clamp control signal 13 is lowered, and the DC level of the digital video signal 16 is also lowered. Therefore, the value of the pedestal error detected next also decreases, and the AND circuit 58b
The pulse width of is also reduced. As a result, the level of the clamp control signal 13 decreases by a small amount, but the DC level of the digital video signal 16 further decreases.

Therefore, the pedestal error is also further reduced.

By repeating the above operations, the pedestal error converges to zero. The digital video signal 16 in the converged state is transferred to the second
As shown in Figure Ce). At this time, as shown in FIGS. 2(f) and (g), the outputs of the AND circuits 58a and 58b become pulses with the minimum width, and the terminals of the switches SW1 and SW2 are kept at high impedance for most of the time. It will be done. Therefore, the brightness gradient in the picture area of the digital video signal 16 is no longer -0. Therefore, the convergence time constant of the clamp loop is also
It can be arbitrarily determined by the resistor R and capacitor C of 9.

The present invention is not limited to the above embodiments; for example, the positive voltage and the ground voltage can be any voltage as long as they are two different voltages. Alternatively, this may be used as two current sources with different polarities. Furthermore, the pedestal error detection function of the present invention is replaced with a burst phase detection circuit, and the structure of the integrating circuit is changed to lead the output of this integrating circuit to the control terminal of the voltage controlled oscillator, thereby applying it to a phase-locked loop circuit. Good too.

[Effects of the Invention] As explained above, the present invention absorbs fluctuations due to aging, temperature changes, and element variations in analog-to-digital converters, and eliminates the need for digital-to-analog converters in the error correction control loop, making it possible to reduce costs. In addition, it is possible to solve the conventional problems of fluctuations in the output signal level at the time of loop operation convergence and followability to human input signals.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a signal waveform diagram shown to explain the operation of Fig. 1, Fig. 3 is a diagram showing a conventional digital clamp circuit, and Fig. 4 is a diagram showing a conventional digital clamp circuit. The figure is a signal waveform diagram of each part of the circuit of FIG. 3. 12... Analog adder, 15... Analog-digital converter, 17... Pedestal error detection circuit, 18.
... Synchronization separation circuit, 20 ... Timing generation circuit, 5
5... Error absolute value circuit, 57... Pulse width modulated wave generation circuit, 58... Pulse output circuit, 59... Analog integration circuit. Figure 2

Claims (2)

[Claims] (1) An error detection circuit to which the signal to be measured is supplied, digitally obtains an error signal with respect to the reference signal, an absolute value circuit that obtains the absolute value of the error signal, and an error detection circuit that digitally obtains an error signal with respect to the reference signal; a pulse width modulated wave generation circuit that generates a pulse signal with a width of 100 nm; a pulse output circuit that outputs a second voltage different from the voltage of the pulse signal and whose output is high impedance during a period when the pulse signal is not generated; and a pulse output circuit that uses the output of the pulse output circuit as input to determine a convergence time constant of the loop. The method is characterized by comprising a loop filter and means for supplying the output of the loop filter to a control section of a circuit that outputs the signal under test in a direction in which an error between the signal under test and a reference signal becomes zero. Error correction circuit. (2) The circuit that outputs the signal under test includes an analog adder that receives an analog video signal as a first input, an analog-digital converter that converts the output of the analog adder into a digital signal, and the analog-digital converter that converts the output of the analog adder into a digital signal. A pedestal error detection circuit detects a pedestal level from a digital video signal output from a digital video signal, detects a difference from a predetermined reference level, and outputs a pedestal error signal as the error signal. The error correction circuit described in item 1.