JPS63311842A - Radio data demodulation circuit - Google Patents

Abstract

PURPOSE:To attain the low-cost for the device by adopting a constitution such that a multiplier for demodulating a radio data signal and a low pass filter are provided independently of a carrier reproducing circuit. CONSTITUTION:The titled circuit is provided with a synchronization detecting means, a phase locked loop means 300, a discrimination means 26 discriminating the constitution of a radio data signal and a signal switching means 25 switching the phase of an output recovered carrier of the phase locked loop means 300 by nearly 90 deg. in response to the output signal of the discrimination means 26. Then a multiplier 14 and a low pass filter 15 for demodulation are provided separately from the digital phase locked loop means 300. Then the phase locked loop means 300 has only to have the performance required and sufficient for the recovery of the carrier and only one system is enough for the multiplier 14 and the low pass filter 15 used for the demodulation. Thus, the circuit is constituted inexpensively.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a radio data demodulation circuit, particularly to a radio data demodulation circuit that uses broadcast waves by a radio data system (hereinafter referred to as RDS) based on the standards of the European Broadcasting Union (EBU). from R
The present invention relates to a radio data demodulation circuit for demodulating DS data signals.

[Prior Art] RDS is a system that provides a 57 KHz subcarrier for FM broadcast audio and multiplexes two types of data. The RDS data signal is a DPSK (Differential Phase Shift Keying) signal with a bit rate of 1187.5 bps.

The subcarrier is carrier-suppressed double-sideband modulation (hereinafter referred to as DSB
(called modulation) and is superimposed on the composite audio signal and transmitted. On the other hand, in countries such as West Germany and Austria.

ARI (Autofahrer Rundfu-nk)
A scheme using the same <57 KHz subcarrier called traffic information system is already in place. In this AR system, the audio signal of the station (traffic information station) that broadcasts traffic information on a regular basis is 57K.
Hz subcarrier, amplitude modulating this subcarrier with a 23-54 Hz sine wave corresponding to the station's service area, and an additional 125 Hz during traffic information broadcasts.
It is characterized by amplitude modulating this with a sine wave. If RDS is introduced in a country where this ARI system is currently in use, both systems will be implemented at the same time. In addition, these signals shift the phases of the subcarriers of ARI and RDS by 90 degrees from each other, and the frequency deviation of the main carrier due to the RDS signal is ±1.2KHz, and the frequency deviation due to the ARI signal is ±3.5KHz. It has been decided that As mentioned above, in the ART system, ARI
Signals are multiplexed only at the traffic information bureau.

RDS will be implemented for almost all FM stations. For this reason, the radio data demodulation circuit used to demodulate the RDS signal is divided into two types: one for RDS alone, and one for AR signal and RD.
It is necessary to operate for both cases where S signals are transmitted simultaneously.

FIG. 7 is a block diagram showing a conventional radio data demodulation circuit, for example, as disclosed in Japanese Patent Application No. 61-48940 "Radio Data Demodulation Circuit" previously filed by the same applicant. In the figure, (1) is a signal input terminal, (2)
and (3) are first and second multipliers, both of whose input sides are connected to the signal input terminal (1). (4
) and (5) are first and second low-pass filters whose input sides are connected to first and second multipliers (
It is connected to the output side of 2) and (3). (6) is the third
a multiplier whose input side is connected to the respective output sides of the first and second low-pass filters (4) and (5). (f) is a loop filter, the manual side of which is connected to the output side of the third multiplier (6).

(8) is a voltage controlled oscillator (Voltage Con-
trolled 0scillator, hereinafter referred to as VCO
), one of which is connected to the first multiplier (2), and the other input side is connected to the output side of the loop filter (7). (9) is 90
degree phase shifter, the first and second multipliers (2), (
3) Connected between. (10) is a signal output terminal, (
11) is a third low-pass filter, the input side of which is connected to the output side of the first low-pass filter (4). (
12) is a window comparator, the input side of which is connected to the output side of the third low-pass filter (11). (13) is a signal switching means, the input side of which is connected to the respective output sides of the first and second low-pass filters (4) and (5), and the window comparator (
12), and the output side thereof is connected to the signal output terminal (10). (100) is a phase-locked loop means, which includes first and second multipliers (2).
, ('3), first and second low-pass filters (4), (
5>, third multiplier (6), loop filter (7), V
Consists of CO (8) and 90 degree phase shifter (9).

In particular, it is of the type called Costas loop means.

(200) is a determination means, which is a third low-pass filter (
11) and a window comparator (12).

The conventional radio data demodulation circuit is configured as described above, and the signal input terminal (1) receives 57KH from the composite audio signal:
It is assumed that the RDS signal and ARI signal are extracted and applied by a z$ band filter.

■First, in the case of only RDS signals, the input signal (e,) can be expressed as follows.

e 1=E++Co sψ(t)・co s 6Je
t - (1) However, E, = RDS signal amplitude ψ (t) = 2πX1187.5

ωゎ=2×π×57000 radians t=time, E,・cosψ(1) are R, D to be demodulated
This is the S data signal.

Assume that the output of the V CO (8), that is, the reproduced carrier, is (er) and that there is a phase difference φ with respect to the RDS carrier.

Also, when a positive control voltage is applied to the VCO (8),
If the output frequency increases and a negative control voltage is applied, it is assumed that the frequency decreases.

er=Ev-cos(ωct 1φ) ・
...(2) The output signal (e-) of the 90 degree phase shifter (9) is.

e r+= Ev−cos (ωC1−+φ+π/
2〉=-Ev'S i n (ωaL+φ) ---
<3) The output signals (eco) and (e, .) of the first and second multipliers (2>, (, 3) are respectively.

e co= E o'c o sψ(t) (co
sφ+cos(2ωct+φ))...
(4) e ao= −E o・c o sψ(t)is
i nφ+5in(2ωet+φ))
...(5) However, E, = K-E P-E v/
2 is the coefficient of the multiplier.

2 by the first and second low-pass filters (4) and (5).
・ω. Since the component is removed, this output signal (e 0.)
.

(eIl,) are each.

ecl-Eo-CO8ψ(1)・cosφ ---(6
)e a+=-Eo'Co sψ(t)・sinφ
...(7).

The output signals <e c, ), (e Il,) are multiplied by the third multiplier (6), and the output signal (eEo) is given as follows.

el:o--2m' (1+co s2ψ(LH-s
i n2φ...(8) Here, E, = -E. ”/4.

This signal (e,.) is passed through a loop filter (7) to V
Since it is added to CO(8), this low-frequency component, ie, −E,·s i n2φ, mainly acts on phase synchronization.

φ-0. That is, when the carrier of the RDS signal and the output of the VCO (8) are approximately equal, when φ is positive, the control voltage becomes negative and the output frequency of the VCO (8) increases.

Bring φ closer to 0. Furthermore, when φ is negative, the control voltage becomes positive and the output frequency of the VCO (8) decreases.

Again, bring φ closer to O. Therefore, this loop has φ=0
It will be drawn into. Also.

5in2 (φ±nπ) = sin2φ (where n = 0
．． 1.2...), it is clear that a similar pull-in occurs also when φ=±π. The condition under which this phase-locked loop means (100) is synchronized, ie, φ=0. ±
The output signal (e c, ) of the first low-pass filter (4) at π, ±2π, .

ee+=±Eo−cosψ(t) −・
(9), and although there is a positive/negative reversal due to the synchronization phase, R
A DS data signal is being demodulated.

(2) On the other hand, when the ARI signal and RDS signal are transmitted simultaneously, the signal (e,) applied to the signal input terminal (1) can be expressed as follows.

e I= E *−COSψ(t)・CO8ωCt+e
^・sinωct...(10) Here, e^=E^(1+m+c OS ω+t+m2
cosωzt) m1 = regional code modulation degree (・0.6±5z)ω, = 2π
Six frequencies of ×23.75 to 2π×53.98 radians/sec each correspond to a service area.

m2 - on-air code modulation degree (=0.3th5$.

O except when traffic information is being broadcast) ω2-2πX125 radians/sec The output signal (e v) of VCO (8) is similar to ■.

Calculating as e v = E v - COS (ωc j + φ), the first and second low-pass filters (4), (5
), the output signals (e c,) and (e-,) are respectively.

eCI: EO°cosψ(t)−cosφ−El,
Sinφ...(11)e,,=
-Eooc os 7p(t)・sinφ-EI
CO5φ...(12) However, E
l = -EV-eA/2 Therefore, the output signal (e -, ) of the third multiplier (6) is as follows.

e to= (E +”Eo'cos 2ψ(
t)) sin2φ-1/2+ E o-E + co
sψ(t)・c.

s2φ ... (13) Since the second term of this equation (13) has a coefficient called cosψ(1), it does not give a fixed output of positive or negative to the phase error φ, but gives it to one phase synchronization. The impact is small.

Also, the first term of equation <13) is.

(El2−Eo'c o s2ψ(t)) s i r
+φ・1/2=2Ev2/IL(EAJ1+m1co
sω+t+m2c o Sωzz)2-ER2Co
s2+p(t)l sinφ
...(14), and from this we extract only the low frequency components that are mainly involved in phase synchronization.

eEO′=2EV2/8(EA”(1+m,”/2+
m2”/2)-ER”) s i n2φ −・(
15).

Here, the amplitudes of the ARI signal and RDS signal are as described above (this signal amplitude is proportional to the deviation of the main carrier wave)E
Since A>EA is established, (E A”(
1+ m,”/2+ m 2”/2)-E R”l
The inside is always positive. Therefore, in this case, unlike in case (2), the one-phase locked loop means (100) is not synchronized at φ-0, but rather the phase difference φ increases. In this case, the phase to which the phase-locked loop means (100) is synchronized is φ=±π/2. This can be expressed as θ=φ±π/2.

5in2(φ±π/2)=s i n2θ holds true.

As explained above, the one phase locked loop means (100) has θ=
0. It is clear from the fact that it is synchronized with . θ=±π5±2
The same goes for synchronizing with π, . . . .

Applying this result to equations (11) and (12) yields the following equations.

ecl-TEl...(16)e
gl°KingEo−cosψ(t) −・・(1
7) From this, when the RDS signal and ARI signal are applied at the same time, it is different from the case where only the RDS signal is applied.

The demodulated RDS data signal is passed through a second low-pass filter (5
) appears in the output.

The determining means (200) and the signal switching means (13) are AR
Depending on the presence or absence of the I signal, the signal extraction portion applied to the signal output terminal (10) is switched to constantly output the RDS signal.

The output of the first low-pass filter (4) is the third low-pass filter connected to the first low-pass filter (4), which becomes an RDS data signal as shown in equation (9) in the case of only an RDS signal. Since the band pass filter (11) is a filter with an extremely low cutoff frequency, its output voltage is approximately zero. On the other hand, ■ARI
When the signal and the RDS signal are transmitted simultaneously, E or -E is obtained as shown in equation (16), and as described above.

Since E+=KEv/2・EA・(1+mlcos to Lllt+m2COSω2t), the output voltage of the third low-pass filter (11) is -EV-EA/4 or -Ev-EA/4 becomes.

The window comparator (12) has an input voltage of K・EV−
If it is higher than EA/8 or lower than -Ev-EA/8.

A second low-pass filter (5) in the signal switching means (13)
A first control signal is applied to select and output the output of -EV-EA/8 and -K-E vll.
If it is between EA/8 and EA/8, the signal switching means (1
3) is configured to provide a second control signal for selecting and outputting the output of the first low-pass filter (4). As a result, the RDS data signal is applied to the signal output terminal (10).

[Problem to be solved by the invention] In a conventional radio data demodulation circuit like the one above.

The first and second multipliers <2), (3) and the first and second low-pass filters (4), (5) both demodulate the RDS data signal. In this demodulation, in order to correctly perform DPSK decoding in the subsequent stage and improve overall decoding performance, it is necessary to correctly reproduce the signal waveform and remove noise as much as possible. For this purpose a first and a second multiplier (2).

In (3), the demodulated signal is not distorted, and the first and second low-pass filters (4) and (5) have a small phase rotation in the pass band and a large attenuation in the stop band. It is necessary to use a waveform shaping filter, and since these are constructed of analog circuits, there is a problem that the device is expensive and difficult to integrate into an IC.

This invention was made to solve the above problems, and aims to provide a radio data demodulation circuit that is inexpensive and can be easily integrated into an IC.

[Means for Solving the Problems] A radio data demodulation circuit according to the present invention includes: synchronous detection means for demodulating a radio data signal; phase locked loop means for regenerating a carrier of the radio data signal;
determining means for determining the configuration of the radio data signal;
The apparatus further includes signal switching means for switching the output of the phase-locked loop means and the phase of the reproduced carrier by approximately 90 degrees in accordance with the output signal of the determining means.

[Operation] In this invention, since the demodulation multiplier and low-pass filter are provided separately from the digital phase-locked loop means, the phase-locked loop means only needs to have sufficient performance for carrier recovery. , only one system of multipliers and low-pass filters are needed for demodulation, resulting in an inexpensive configuration.

Furthermore, when digital phase-locked loop means and determination means for carrier reproduction are implemented as digital circuits, IC
This makes it easier to

Embodiment FIG. 1 is a block diagram showing a radio data demodulation circuit according to an embodiment of the present invention. In fig.

(14) is a multiplier, (15) is a low-pass filter, (16)
is a comparator, (17) and (18) are the first and second exclusive OR circuits (Exclusive OR
(hereinafter referred to as EOR circuit), (19), (20)
are the first and second counting circuits (hereinafter referred to as counters)
, (21) is the timing generator, (22) is the third FO
R circuit, <23) is a variable frequency divider, (24) is a 4 frequency divider,
(25> is a signal switching means, (26) is a determining means, (
27> is a crystal oscillator. (300) is a digital phase-locked loop means (hereinafter referred to as digital PLL means), and the first and second EOR circuits (17), (1
8), first and second counters (19), (20>,
Timing generator (21>, third EOR circuit (22)
and digitally controlled oscillator (D-digital C
controlled 0sc-i lator,
(hereinafter referred to as DCO) (400). Also,
The DCO (400) includes a variable frequency divider (23) and a 4-frequency divider (
24) and a crystal oscillator (27).

FIG. 2 is a diagram showing vectors of the input signal of FIG. 1.

FIG. 3 is a diagram showing the waveform of the RDS signal.

FIGS. 4 and 5 are diagrams for explaining the operation of the digital phase-locked loop means.

FIG. 6 is a detailed block diagram of the determination means of FIG. 1. In the figure, (30) is an input terminal to which the output of the first counter (19) is connected, and (31) is the input terminal to which the output of the first counter (19) is connected.
) reading timing signal input terminal, (32
) is the first (n+1) pit binary counter, (33
) is a FOR circuit, (34) is a D type flip-flop circuit (hereinafter referred to as DFF circuit), and (35) is a second
(n + 1) pit binary counter, (36)
is the output terminal.

In the radio data demodulation circuit configured as described above, the 1 multiplier (14) and the low-pass filter (15) convert the output signal of the signal switching means (25) to the input signal from the signal input terminal (1). It acts as a synchronous detector using the reference signal. Therefore, as shown in FIG. 2, when the input signal is only the ■RDS signal.

■When RDS signal and ARI signal exist at the same time.

In the case of ■, e t+=E*c o sψ(t
)・co sωct ... (18) In the case of ■+ e 12= Etco sψ(
t)-c o sωct t" e ^・sinωct ... (19) For each of -23', the RDS signal component Epc o sψ
(1) A reference signal (Ecc
osωct), the RDS signal component can be demodulated.

Multiplier (1) for input signal (e8.), (e-)
4) The output signals are respectively.

ep+=KEc/2-Etc o sψ(t> + K
E c/2ERCO5ψ(1)・cos2ωct...(20) ep2'=KEc/2・E+tc o sψ(t)+K
Ec/2E tsubac o sψ(t)・CO52ωct+K
Ec/2-eAs in2+u+ct=(2
1) However, is the coefficient of the multiplier.

The RDS signal components are respectively demodulated by the low-pass filter (15) and the ARI signal components are eliminated. Further, even if the reference signal includes many harmonic waveform components such as a square wave, the input signal from the input terminal (1) is normally filtered by a bandpass filter to reduce the angular frequency ω. Considering that there are only nearby components, the signal components generated at the output of the 5 multiplier (14) due to their harmonic components all have an angular frequency ω. All of them are low pass filters (15
) is excluded and there is no problem.

Next, a process of obtaining a reference signal synchronized with the RDS signal carrier at the output of the signal switching means (25) will be described.

In this embodiment, the phase-locked loop means is a digital P-type circuit composed of digital elements in order to reproduce the carrier of the input signal.
Use LL means.

The comparator (16) is connected to this digital PLL means (
300), the input signal from the signal input terminal (1) is binarized and given thereto.

■If the input signal is only RDS signal, comparator (1
As shown in Fig. 3, the input signal waveform and output signal waveform to 6) are such that the carrier phase changes by 180 degrees according to the positive/negative of the modulation signal ERCosψ(1).
FIG. 3 is for convenience of explanation.

Although the carrier period included in one period of the modulation signal is assumed to be 16, in reality, 48 periods of waves are included). Therefore, the digital PLL means (300) needs to be synchronized to one of the carrier phases regardless of the 180 degree reversal of the carrier phase. The digital PLL means (300) includes first and second EOR circuits (17) for phase comparison.
), (18), the first and second counters (19), (20) which average the comparison outputs for an appropriate period, and the frequency division ratio of the variable frequency divider (23) from the outputs of these two counters. A third EOR circuit (22>) to control, a variable frequency divider (23) that receives the control output and divides the output of the crystal oscillator (27) into 1/(N-1) or 1/(N+1). It is composed of a 4-frequency divider (24) that provides outputs whose phases are different from each other by 90 degrees, and a timing generator (21) for first and second counters (18) and (19).

Output angular frequency ω of the crystal oscillator (27). , and the average frequency division ratio N of the variable frequency divider (23) is.

ω. =4・N・ω. ...(22)
selected. Therefore, the frequency division ratio of the variable frequency divider (23) is approximately 1/2 at a rate of 1/(N-1) and 1/(N+1).
When the frequency divider (24) is controlled to have a frequency substantially equal to the carrier frequency, an output of the frequency divider (24) is obtained.

As the ratio of control to 1/(N-1) increases, the output phase advances (the frequency becomes higher). Conversely, 1/(N+1
), the output phase will be delayed (the frequency will become lower). The crystal oscillator (27), variable frequency divider (23), and 4-frequency divider (24) are collectively referred to as DCO.
It is called.

FIG. 4 is an explanatory diagram of the operation when the input signals (a) and (C) of the first EOR circuit (17) have substantially the same phase. Signals (a) and (b) are output signals of the 4-frequency divider (24), and have a phase difference of 90 degrees from each other, and are added to the first and second EOR circuits (17) and (18), respectively. It will be done. Signal (C) is the output signal of the comparator (16) and is the output signal of the first and second FOR circuits (17) and (18).
) are added to each. Signals (d) and (e) are output signals of the first and second EOR circuits (17) and (18), respectively. first and second counters (19);
(20) are binary up/down counters, respectively. n-bit up/down counter has clock input 1
For pulses, in the case of up-counting, increase the output by +1,
In the case of down counting, the output is -1, and when the count value is in the range of 2"-'-1 and -(2"-1), the most significant bit is "0" and is correct. can be viewed as a sign bit that indicates a negative value when it is "1". Therefore, a signal is input to the up/down control terminal, the initial value of the counter is set to zero, and counting is performed for an appropriate period using a clock that is sufficiently fast with respect to changes in the input signal.

Moreover, for any input condition, the number of counts is (2'
If the number of counter bits n is set so that it does not exceed -'-1) and does not fall below +-(2'-hard), the most significant bit output of the counter will be determined by the input signal being “
If the period of 0” (up count) is long, set it to “O”, and if the period of 1” (down count) of the input signal is long, set it to 1”
This will give the output of Thus, the first and second
The counters (19) and (20) output the cumulative judgment value for a certain section of this input signal.

In Fig. 4, the signals (c), (d), (
e).

The phase of the input signal (c) is determined by digital PPL means (300
) shows the same phase (φ=O゛) as the output signal (a) of the first EOR circuit (17,), and the output signal (d) of the first EOR circuit (17,)
becomes "O", and the output of the first counter (19) becomes 0" at the end of counting. The output of the second EOR circuit (18
The output signal (e) of ) is approximately 50/50 between "0" and "1", and the output of the second counter (20) is also approximately 50/50 between "0" and 1/2. Therefore, there is only a slight phase change in the output of the DCO (400), and the synchronized state is maintained.

Next, when the output phase of the DCO (400) is delayed (φ〉0°) (Fig. 4 (B)) with respect to the input signal (c'H,: (c', d', e'') Then, the average value of the signal (d'), and therefore the output of the first counter (19), is 0'', and the average value of the signal (e') is close to 1, so the second
The output of the counter (20) becomes "1". Therefore, the third EOR circuit (22) outputs the output of the first and second counter (20).
19).

(20) becomes 1" at the end of counting. At this timing, the output ("1") of the third EOR circuit (22) is set to the variable frequency divider (23), and the frequency division ratio is set to 1/ (
As a result, the output phase of the DCO (400) advances and synchronizes the phase difference φ with the input signal (e') to 0. ) is leading the output phase (φ 0°) (4th IJ (
In C), the waveforms are shown at e'', d'', and e''
The output of the OR circuit (17) is 0 on average, so the output of the first counter (19) is "O", and the output of the second EOR circuit (18) is also "o" on average, so the output of the second counter (19) is "0". The output of 20) is °′O″. Therefore, the third EO
The output of the R circuit (22) is sent to the first and second counters (
19) and (20), it becomes "0", which is set in the variable frequency divider (23), and the frequency division ratio is set to 1/(N
As a result, the output phase of the DCO (400) is delayed, and the phase difference φ with the input signal (e″) is compressed and approaches 0.

Next, in FIG. 5, the phase of the input signal (τ) is D CO (40
0) is a diagram for explaining a synchronization state when the output signal differs by 180'' from the output signal (a) of FIG.

(A) When the phase difference φ is 180° (τ, Go, ;), the first
The output of the EoR circuit (17) is approximately 1°, and the output of the second EOR circuit (18) is half "do", half "0". Therefore, the output of the first counter (19) is approximately 1°. “1-
The output of the second counter circuit (20) is approximately 1°,
“°O゛.

The output of the third EOR circuit (22) is also '1-'0.
The DCO (400) output phase change is slight and the synchronized state is maintained.

(B) When the phase difference φ is larger than 180° (ε′, 1′τ
'), output signal (d') of the first EOR circuit (17)
is close to the average value "1", the output of the first counter (19) is "1", and the output signal (τ'
) is close to the average value "0", and the output of the second counter (20) becomes "o". Therefore, the third EoR circuit (22
) becomes 1/1, and the frequency division ratio of the variable frequency divider (23) becomes 1/(N-1), so the output phase of the DCO (400) advances and the phase difference φ approaches 180°.

(C) When the phase difference φ is smaller than 180° (ε″).

d'', e''), the output signal of the first EOR circuit (17) (
d") is close to the average value "1', the output of the first counter (19) is "1", and the output signal of the second EOR circuit (18) is "1".
i") is close to the average value "1", and the second counter (20)
The output of is "°1", therefore the output of the third EOR circuit (22) is "0", and the frequency division ratio of the variable frequency divider (23) is 1/(N+1), which is the output of the DCO (400). Delay the phase.

Bring the phase difference φ close to 180'.

As described above, it is clear that this digital PLL means (300) can synchronize both when the phase difference φ with the input signal is Oo and when it is 180°, so It is also possible to synchronize a signal with a 180° phase change and reproduce its carrier (this continuous wave without a 180° phase change). Furthermore, in this case,
While the output signal (a> of the frequency divider (24) is synchronized with the RDS signal carrier with a phase difference of Oo or 180°, the signal switching means (25) selectively outputs this signal (a>) and outputs the signal (a>) to the multiplier (14). ), demodulation of the RDS data signal is performed.

(2) When the RDS signal and ARI signal are input at the same time, this signal (e, 2) becomes as shown in equation (19), but this also applies.

e12″(E*2CO52ψ(1)÷eA2)1/2.
s i 0(ωat+θ.)...
(23) However, θo= j a n '(Etc o
It can be rewritten as s (t)/e A). This signal <e,
2) can also be expressed as a vector diagram as shown in FIG. 2(b).

The amplitude and phase relationships of the RDS and ARI signal components are as described above. However, in FIG. 1, amplitude modulation is omitted. The signal <e, 2> is the ARI signal with slight amplitude modulation due to the RDS signal component and θ. This is a phase modulated signal. Therefore, the output of the comparator (16) is θ
. This is a square wave corresponding to the phase modulated ARI signal carrier.

Its average phase is the same as that of the ARI signal carrier,
There is no phase reversal as would occur with the RDS signal alone.

Therefore, as is clear from the previous explanation, digital PL
The L means (300) is synchronized with the ARI signal carrier so that the phase difference φ is 0'' or 180''. Phase modulation θ. is almost zero if averaged over a suitable period due to the nature of the RDS data signal, so its influence is due to the cumulative judgment processing of the input signal by the first and second counters (19) and (20) and the D CO (4,000 ) is removed by its own integral effect.

In this way, the output signal (a) of the frequency divider (24) by 4 has the ARI signal. Since the signal carrier phases of the RDS signal and ARI signal are synthesized so that they differ from each other by 90'', in this case, the output signal (b) of the .4 frequency divider (24) is approximately 0° with respect to the carrier phase of the RDS signal. Alternatively, they will be synchronized with a phase difference of 180''.

Therefore, in this case, the signal switching means (25).

The RDS data signal is demodulated by selecting the output signal (b) of the 4-frequency divider (24) and applying it to the multiplier (14).

Next, the operation of the determining means (26) will be explained.

This determining means (26) determines whether the input signal is only the RDS signal or when the RDS signal and ARI signal are input simultaneously, and provides an input selection signal to the signal switching means (25). This operation is performed when the input signal is RD.
In case of S signal only (■), digital PLL means (30
The first EoR circuit (17) because the input signal phase of 0) is reversed by 18° at least once every 171187.5 seconds
The average value of the output. Therefore, the output of the first counter (19) takes a value of "On" and "1" every time this phase is reversed, and if the period is sufficiently longer than this reversal period, it becomes "0".
The probability of appearance of “1” is approximately 1/2, and RD
When S signal and ARI signal are input at the same time (■)
This can be done by taking advantage of the fact that the output of the first counter (19) appears largely biased towards either 0° or 1°' since such a phase inversion does not occur.

In FIG. 6, the second binary counter (35) is
It constantly counts the timing signal input to the input terminal (31), and if the count value exceeds (2'''-1) and an overflow occurs, the count value is returned to zero and a carry signal is issued. in.

This carry signal causes the first binary counter (32
) is cleared to zero. At the same time, DFF
The D input signal of the circuit (34), that is, the output signal of the EOR circuit (33) is read and outputted to the output terminal (36).
). The data read by the DFF circuit (34) here follows the output immediately before the first binary counter (32) is cleared. The first binary counter (32) is the same ((n+1) bit counter as the second binary counter (35) and has the same input terminal (3
In order to use the signal given to 1) as the counting input. It still counts from zero to (2'''-1>), but it does not overflow because it is periodically cleared by the output of the second binary counter (35). Also, the first binary counter (32) Counting is controlled by a signal given to the input terminal (30).If this input signal is "1", counting is enabled, and if it is "0", counting is prohibited.If the input signal is biased to "On", counting is disabled. At the reading timing of the DFF circuit (34), the first binary counter (32
) and its one least significant bit output (
Q. ,Q. -, ) is (0.0), and the input signal is about 172 of "0" and ° "1".

(Q,,Q.,) is (0.1) or (1, O)
The output is Furthermore, if the human input signal is biased toward "1", the output (Q,.

Q. , ) becomes (1.1). When only the RDS signal is input as described above, the input signal to this input terminal (30) is "1" and "On" are each approximately 1/2 If the RDS signal and ARI signal are input simultaneously (■), the probability will be biased toward either "°O" or "1°°." Therefore, the presence or absence of ARI signal is determined by EOR.
This can be determined by providing the circuit (33) with the output of the most significant bit of the first binary counter (32) and the bit below it, and the output is 1'' at the read timing of the DFF circuit (34).

It is determined that only the RDS signal is input, and if it is "0'°, it is determined that the RDS signal and the ARI signal are input simultaneously. The DFF circuit (34) is connected to the first binary counter (32). ) continues to output the previous judgment result even during counting for judgment, and the signal switching means (25) can be directly controlled.

In the above embodiment, the frequency divider of the DCO (400) is divided into a variable frequency divider (23) and a 4-frequency divider (24), but this is because the output frequency of the crystal oscillator (27) is Almost R
Divide into DS signal carrier frequency.

If the output phase can be controlled and the outputs have a phase difference of 90 degrees from each other, the same effect can be achieved6. For example, by replacing the 4 frequency divider (24) with a 90" phase shifter, It is also possible to quadruple the average frequency division ratio of the frequency generator (23).

Further, in the above embodiment, the output of the EOR circuit (22) is directly applied to the variable frequency divider (23), but a counter for performing cumulative determination may also be provided between the outputs of the EOR circuit (22). Furthermore, in the above embodiment, the control signal is given to the DCO (400) using two frequency division ratios, namely 1/(N-1) and 1/(N-1).
+1> is switched, but 9 For example, EOR circuit (22)
count the output of
(N+1), clear the counter at the same time, and if the counter output is less than a certain value, set it to 1/(N-1) and clear the counter at the same time, and under other conditions, set the division ratio to 1.
/N can also be configured.

In addition, the first binary counter (32) of the determination means (26) in the above embodiment is a simple up-counter that allows or prohibits counting depending on the input signal; Down counting may also be controlled. In this case, the most significant bit and the next bit of the output of the counter are "0" when only the RDS signal is input.

The judgment means (2
The output of 6) will be inverted from that of the above embodiment.

Since this is a simple inversion, it can easily be made to perform the same operation as the above embodiment.

Further, in the above embodiment, the input signal of the determining means (26) is obtained from the output of the first counter (19).

This can also be configured to directly input the output of the first EOR circuit (17) for determination.

[Effects of the Invention] As described above, the present invention includes a synchronous detection means for demodulating a radio data signal, a phase locked loop means for reproducing a carrier of the radio data signal, and a configuration of the radio data signal. The apparatus includes a determining means for determining, and a signal switching means for switching the phase of the output reproduction carrier of the phase-locked loop means by approximately 90 degrees in accordance with the output signal of the determining means.

Since the multiplier and low-pass filter for demodulating the RDS data signal are provided independently of the carrier regeneration circuit, there is an effect that the device can be made inexpensive.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a radio data demodulation circuit according to an embodiment of the present invention, and FIG. 2 is a vector diagram of input signals to the radio data demodulation circuit of FIG. 1. FIG. 3 is a waveform diagram of the RDS signal, and FIGS. 4 and 5 are operation timing diagrams of the digital PLL means. FIG. 6 is a detailed block diagram of the determination means (26) in FIG. 1;
FIG. 7 is a block diagram showing a conventional radio data demodulation circuit. In the figure, (14)... multiplier, (15)... low pass filter, (16)... comparator, (17)...
...First EOR circuit, (18)...Second FOR circuit, (19)...First counter, (20)...Second counter. (21)...timing generator, (22>...third
EOR circuit, (23>...variable frequency divider, (24)
...4 frequency divider, (25) ... signal switching means, (2
6)...determination means, (27)...crystal oscillator, (3
00)...Digital phase-locked loop means, (400
)...DCO. Note that the same reference numerals in each figure indicate the same or corresponding parts. Death 20 Child 3 Diagram (b) RDS Imo No. 15 ± Power" υ Sugio 4 Diagram b e" 兇 5 Diagram 5 Procedural Amendments September 4, 1986

Claims (4)

[Claims] (1) A synchronous detection means for demodulating a radio data signal, a phase-locked loop means for regenerating the carrier of the radio data signal, a determining means for determining the configuration of the radio data signal, and a determining means for determining the configuration of the radio data signal. The phase of the output regenerated carrier of the phase-locked loop means is adjusted to approximately 9 in accordance with the output signal.
1. A radio data demodulation circuit comprising: signal switching means for switching 0 degrees, and using an output signal of the signal switching means as a reference signal to be supplied to the synchronous detection means. (2) The radio data demodulation circuit according to claim 1, wherein the synchronous detection means is comprised of a multiplier and a low-pass filter. (3) The first claim characterized in that the phase-locked loop means and the determination means are constituted by digital circuits.
The radio data demodulation circuit described in Section 1. (4) The determination means includes a counting circuit, an exclusive OR circuit,
4. The radio data demodulation circuit according to claim 1, wherein the radio data demodulation circuit comprises a D-type flip-flop circuit.