JPS63311699A - Sample-and-hold circuit - Google Patents

Abstract

PURPOSE:To reduce the settling time by selecting a value of a phase compensation capacitor in response to a hold capacitor so as to obtain an optimum transient response characteristic. CONSTITUTION:An input signal 6 is given to a noninverting input of an operational amplifier 1 and its output is given to a hold capacitor 4 and a buffer circuit 3 via a switch circuit 2 switched by a sample pulse 7 and the other terminal of the hold capacitor 6 is connected to ground and the output of the buffer circuit 3 is given to an inverting input of the operational amplifier 1 to constitute a feedback loop and the signal is fed back to an internal circuit of the operational amplifier 1 via the phase compensation capacitor 5. Through the constitution above, the switch 2 and the hold capacitor 4 form a low pass filter having a frequency characteristic different depending on the ON-resistance of the switch 2 and the value of the hold capacitor 4. Thus, in selecting the phase compensation capacitor 5 properly, the optimum transient response is obtained and the settling time is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a sample and hold circuit that samples an input signal using a sample pulse and holds that voltage until the arrival of the next sample pulse. For example, the present invention relates to a sample and hold circuit used in sampling servo and the like.

BACKGROUND ART FIG. 4 is a diagram showing the configuration of a conventionally known general sample-and-hold circuit.

In FIG. 4, an input signal 6 is supplied to the normal input of an operational amplifier 11, and the output of the operational amplifier 11 is connected to a hold capacitor 4 and an output buffer 7 circuit 3 via a switch circuit 2. The output of the buffer circuit 3 becomes the output of this sample and hold circuit, and is also connected to the inverting input of the operational amplifier 11. The operational amplifier 11 performs phase compensation to prevent oscillation due to feedback of the output of the buffer circuit 3:
] The phase is compensated by the capacitor 5. The operation of this circuit is that switch 2 is closed when a sample pulse arrives;
Feedback of the outputs of the operational amplifier 11 and the buffer circuit 3 constitutes a portage funnel, and the output of the buffer circuit 3 outputs the same voltage as the input signal. At this time, the hold capacitor 4 accumulates a charge corresponding to the voltage at that time, and when the switch 2 is opened, the capacitor 4 holds the accumulated charge, so the output of the buffer circuit 3 is the same as the previous voltage. is held as is.

Problems to be Solved by the Invention In the sample and hold circuit shown in FIG. The charge that should have been stored flows out over time, causing droop, which causes the output voltage to gradually change. Especially when the hold time is long, the amount of change becomes a large value. To reduce droop,
Measures are taken to increase the capacitance of the hold capacitor 4, but at this time, the on-resistance of the switch 2 and the hold capacitor 4 form a kind of low-pass filter, and the configuration of FIG. 2 with a feedback loop causes an unstable system. It becomes.

FIG. 5 shows an example of an output waveform when a square wave is applied to the input signal with switch 2 closed in the sample-and-hold circuit shown in FIG. 4 in an unstable state. Although the rise time is short, overshoot occurs and ringing occurs, resulting in a long settling time Ts.

Therefore, it goes without saying that the pulse width of the sample pulse needs to be Ts or more, but in a system where the pulse width is limited to Ts or less, the held value becomes uncertain.

Means for Solving the Problems The present invention solves the above problems by changing the value of the phase compensation capacitor that is fed back from the buffer output to the internal circuit of the operational amplifier according to the value of the hold capacitor. The phase characteristics of the loop can be varied to obtain optimal transient response characteristics.

Function: With this configuration, overshoot 1. A transient response characteristic with less ringing can be obtained, and the settling time can be set to the minimum value.

Embodiment FIG. 1 is a block diagram of a sample and hold circuit which is an embodiment of the present invention. In FIG. 1, an input signal 6 is supplied to the normal input of an operational amplifier 1, and its output is a sample pulse. The other terminal of the hold capacitor 6 is grounded, and the output of the buffer circuit 3 is connected to the inverting input of the operational amplifier 1. The signal is fed back to the internal circuit of the operational amplifier 1 via the phase compensation capacitor 5, forming a feedback loop. In this configuration, switch 2 and hold capacitor 4 are connected to the on-resistance of switch 2 and hold capacitor 4.
A low-pass filter with different frequency characteristics is formed according to the value of .

Figure 2 shows the transient response characteristics when the value of the phase compensation capacitor 5 is set appropriately for the value of the hold capacitor.
Neither overshoot nor ringing occurs, and the value converges to the final value in a short settling time Ts. In this way, by selecting an appropriate value for the phase compensation capacitor 5 in accordance with the value for the hold capacitor 4, an optimal transient response can be obtained, the settling time is short, and a system with a short sample pulse can be supported.

FIG. 3 is a circuit configuration diagram of a sample and hold circuit showing a more specific embodiment of the present invention. In FIG. 3, a section I surrounded by a dashed-dotted line indicates an operational amplifier circuit, 2 indicates a switch circuit, and m indicates a buffer circuit. Q1 to Q17 are transistors, R1 to R6 are resistors, and 11
~■6 indicates a constant current source, and SWl is a current switch that opens and closes the sample pulse. CH is a hold capacitor, CT is a phase compensation capacitor, and the buffer output is fed back to the base of the transistor Q7 in the operational amplifier circuit.

Furthermore, the circuit shown in FIG. 3 can be easily integrated into a monolithic circuit, and if Tl to T6 are taken out as terminals, the hold capacitor CH and the phase compensation capacitor CT can be freely selected and a wide range of specifications can be set. Of course, if the specifications are limited, it is also possible to integrate the Holby capacitor C8° phase compensation capacitor CT. Further, in FIG. 3, the operational amplifier, switch, and buffer are constructed with bipolar elements, but it goes without saying that they can be constructed with MO8 elements.

Effects of the Invention As described above, according to the present invention, by selecting the value of the phase compensation capacitor according to the value of the hold capacitor, an optimal transient response characteristic can be obtained, and a sample-and-hold circuit with the shortest settling time can be realized. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a sample-and-hold circuit according to an embodiment of the present invention, FIG. 2 is a transient response characteristic diagram of the sample-and-hold circuit according to the present invention, and FIG. 3 is a diagram showing a specific embodiment of the present invention. FIG. 4 is a block diagram showing a conventional sample-and-hold circuit, and FIG. 5 is a transient response characteristic diagram of the conventional sample-and-hold circuit. 1... operational amplifier, 2... switch circuit, 3... buffer circuit, 4... hold capacitor, 5... phase compensation capacitor,
6...Input signal, 7...Sample pulse. Name of agent: Patent attorney Toshio Nakao and one other person Figure 2 TIME βFQ Figure 14 Figure 5 11M5 . 5'EC

Claims (1)

[Claims] The operational amplifier and its output are coupled to a hold capacitor and an output buffer via a switch that opens and closes with the sample pulse, and the output of this buffer is feedback coupled to the inverting input of the operational amplifier and is connected via a phase compensation capacitor. A sample and hold circuit characterized in that the sample and hold circuit is feedback-coupled to an internal circuit of the operational amplifier.