JPS63311693A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To attain efficient bump test by providing a logic means setting at least one of word and data lines wired to select a storage cell into the full selection state. CONSTITUTION:X and Y decoders 4, 5 are provided, which select alternatively word and data lines 2, 3 based on address inputs Ax, Ay of word and data lines 2, 3 wired by plural wires respectively to select an optional storage cell among lots of storage cells 1. Moreover, a logic means 8 to set data line pairs 3, 3 to the full selection state in response to a test setting signal B given externally via a terminal pad 9, is provided, and the logic means 8 keeps the nonactive state in the normal operation and gives no effect on the operation of the Y decoder 5 and activated by setting the test setting signal B into the active state, thereby driving the Y switches in the on-state simultaneously. Thus, the bump test time is reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to semiconductor memory device technology, and furthermore, to 5-RAM
(Static type RAM), for example, bipolar-0MO3 type 5-R as described in Japanese Patent Application Laid-open No. 170090/1983.
It relates to technology that is effective for use in AM.

[Prior Art] In a semiconductor memory device, if the power supply voltage changes significantly during the selection of a memory cell, the information stored in the selected memory cell may be destroyed. The present inventors have clarified that this tendency is more likely to appear in the Tokuni bipolar CMO8 type S-RAM.

Therefore, the present inventors conducted a test to examine whether or not stored information is destroyed by intentionally changing the power supply voltage of a semiconductor memory device during memory cell selection, a so-called bump test. (BumpTest) was investigated.

[Problems to be Solved by the Invention] However, the inventors have found that the above-mentioned technique has the following problems.

That is, the present inventors have clarified that in the conventional semiconductor memory device, the following steps are required to perform the above-described bump test.

That is, as shown in FIG. 3, there is a step S1 of selecting a memory cell under test, a step S2 of writing test data to the memory cell under test, and a step S2 of writing test data into the memory cell under test. Step S3 in which is changed by a predetermined amount
, a step S4 of reading and evaluating the storage contents of the memory cell under test after passing through this step S3, and a step S5 of updating the address by one address in order to designate the next memory cell under test.
, and step S6. in which the series of steps 81 to S5 described above are repeated a number of times (MXN) corresponding to the total number of storage bits (or total number of storage words) of the semiconductor memory device.
S7 is required.

The problem here is that in order to change the power supply voltage in step S3, it takes a relatively long time, for example several ounces number of words memorized)
This must be done a number of times (MXN) corresponding to (MXN).

For example, 65,536 memory cells are selected one by one by 128 word lines and 512 pairs of data lines.
In the case of bit 5-RAM, the above number of times (MXN) is 65
That's 536 times. Therefore, if the time required to perform the above step S3 once is 100 m5ec, the required test time per sample is 65536 times x 100
m sec = 6553.6 seconds = 1 hour and 50 minutes.

As described above, the conventional semiconductor memory device cY of this type has a problem in that it is significantly lacking in testing suitability for performing the above-mentioned bump test and the like.

An object of the present invention is to improve the testing suitability of semiconductor memory devices. Specifically, it is an object of the present invention to efficiently perform a bump test to check whether or not stored information is destroyed due to changes in power supply voltage during selection operation on an individual memory cell basis. Our goal is to provide the technology that makes it possible.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows.

That is, it has logic means for setting at least one of a word line and a data line wired to select a memory cell to a fully selected state.

[Operation] According to the above-described means, it is possible to collectively set the memory cells row by row or column by column to the selected state at the same time.

As a result, when performing a bump test to check whether stored information is destroyed due to a change in power supply voltage during 1 selection operation, the process of changing the power supply voltage is performed not in bit units or word units, but at least in row or column units. be able to do it. As a result, the bump test time required per sample becomes significantly shorter.

In the manner described above, the objective of improving the testing suitability of semiconductor memory devices is achieved.

[Examples] Hereinafter, preferred embodiments of the present invention will be described based on the drawings.

In each figure, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an embodiment of a main part of a conductive memory device to which the technology according to the present invention is applied.

First, the semiconductor memory device shown in the figure is bipolar-0MO.
It is configured as a 3-type 5-RAM, and has a large number of memory cells 1 arranged in a matrix in the row and column direction.A plurality of memory cells 1 are each wired to select an arbitrary memory cell from among the large number of memory cells 1. word line 2 and data line 3,
An X decoder 4 that selectively selects the word line 2 and the data line 3 based on address inputs Ax and Ay.
and a Y decoder 5.

In this case, two data lines 3 are arranged in pairs, and a plurality of pairs are wired. Each data line pair 3, 3 is connected to a common data line 7 via a Y selection switch 6, respectively. The Y selection switch 6 is selectively selected by the Y decoder 5 and turned on.

In normal operation, the word line 2 and the data line pair 3,
3 are alternatively selected, so that the memory cell 1 located at the intersection of the selected word line 2 and data line pair 3.3 is selected and subjected to memory writing/reading. It has become.

Furthermore, in the illustrated embodiment, in addition to the above-described configuration, logic means 8 sets the data line pair 3 to the fully selected state in response to a test setting signal B applied from the outside via the terminal pad 9. is provided. This logical means 8 is
Multi-input logic gate 61 provided in the Y decoder 5
It is constructed by adding logical hexagonal terminals. This logic means 8 maintains an inactive state during normal operation and does not participate in the operation of the Y decoder 5, but is activated by setting the test setting signal B to an active state, and is activated by setting the test setting signal B to an active state. Turn on the switches all at once.

FIG. 2 shows how the above-described embodiment is applied to a semiconductor memory device.
The procedure for performing a bump test for checking each storage cell for the presence or absence of storage information destruction due to a change in power supply voltage during a selection operation will be described.

As shown in the figure, a bump test on the semiconductor memory device of the above-described embodiment can be performed as follows.

First, in step S1, a word line is selected, and predetermined test data is written bit by bit into the memory cells on the selected word line.Next, the test setting signal B is activated. Step S21 is then performed to set all the data lines to the selected state using cells 1 to 1. As a result, one row (N) of memory cells lined up on the selected word line are set to the selected state at the same time. In this state, step S3 of changing the power supply voltage by a predetermined amount is performed. After this, step S31 of resetting the test setting signal B is performed, and then the data stored in the memory cells arranged on the selected word line is changed. A step S4 is performed in which each bit is read out and evaluated. This evaluation is
This is performed by focusing on whether or not the test data written in step S2 has changed.

After step S4 is completed, step 8S5 is performed to update the row address by 1 in order to designate the first selected word line. Then, step S6. Through S7, the above-mentioned series of steps 81
-S5 are repeated a number of times (M) corresponding to the number of word lines.

As described above, in the semiconductor memory device of the embodiment shown in FIG. 1, the memory cells can be grouped in rows and set to the selected state at the same time. As a result, when performing a bump test to check for damage to stored information due to power supply voltage changes during selection operations, the step of changing the voltage sit voltage can be performed row by row instead of bit by bit or word by word. become able to. As a result, the bump test time required per sample can be significantly reduced.

For example, 65,536 memory cells are selected one by one by 128 word lines and 512 pairs of data lines.
In the case of a bit 5-RAM, the step S3 of changing the power supply voltage can be performed 128 times for one sample. Therefore, if the time required to perform the above step S3 once is 100 m sec, then 1 The required test time per sample may be 128 times x 100 m5ec = 12.8 seconds.

Note that the terminal pad 9 for applying the test setting signal B may be provided inside the semiconductor chip if only the bump test is performed, but if it is drawn out to an external terminal pin, the same memory content can be performed. It can also be used when writing in units at high speed.

As above, the invention made by the present invention has been specifically explained based on the examples, but it goes without saying that the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the logic means 8 may be such as to set the word line or both the word line and the data line to the full state.

The above explanation mainly describes the invention made by the present inventor, which is the field of application which is the background of the invention, which is bipolar-0MO.
Although the case where the present invention is applied to an 8-type 5-RAM has been described, the present invention is not limited thereto, and can also be applied to, for example, a pure CMO 8-type 5-RAM or an ECL-type RAM.

C Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly described below.

In other words, it is possible to improve the testing suitability of semiconductor memory devices, and for example, it is possible to efficiently conduct a bump test to check whether or not stored information is destroyed due to changes in power supply voltage during selection operation on an individual memory cell basis. Effects can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a main part of a semiconductor memory device according to the present invention, FIG. 2 is a flowchart showing a procedure for bump testing the semiconductor memory device shown in FIG. 1, and FIG. 2 is a flowchart showing the steps required to bump test a conventional semiconductor memory device. 1...Memory cell, 2...Word line, 3...
Data line, 4...X decoder, 5...X decoder, 6...Y selection switch, 7...Common data line, 8...Logic means, 9... Terminal pad for testing. Figure 2

Claims (1)

[Claims] 1. A large number of memory cells arranged in a matrix, and a plurality of word lines and data wired each to select an arbitrary memory cell from the large number of memory cells. and a decoder that selectively selects the word line and the data line based on address input, and at least one of the word line or the data line is fully selected according to external settings. 1. A semiconductor memory device comprising logic means for setting. 2. The semiconductor memory device according to claim 1, wherein the logic means is constituted by a multi-input logic gate provided in the decoder.