JPS6331089Y2 - - Google Patents

Description

[Detailed explanation of the idea]

The present invention relates to a level display circuit that determines and displays the signal level of a digital signal processing device using pulse code modulation directly from a pulse code modulation code. Conventionally, well-known VU meters and peak meters have been used as level display methods, and are also used in some digital devices. Recently, digital devices have become widespread, and various methods of level display have been used. The digital devices are broadly classified into two types. One is that the output signal can be extracted as an analog signal,
One has a built-in so-called D-A converter, and the other is composed only of completely digital elements. The former has many advantages, such as being able to take out an analog signal as an output, allowing the conventional VU meters and peak meters to be used as is, and requiring a relatively simple drive circuit. However, the latter is completely digital from input to output, and has the drawback that conventional VU meters and peak meters cannot be used as is. Therefore, recently, level display circuits have been adopted that convert binary digital codes into absolute values and then construct and display codes corresponding to arbitrary levels from each code using logic gates. According to this method, accurate level display is possible regardless of variations in characteristics caused by analog meters, mechanical factors, etc. Table 1 shows the relationship between each level and code when the full scale expressed in complementary offset binary is OdB. As is clear from this table, each bit can be separated into a sign and an absolute value by exclusive ORing.

【table】

【table】

[Table] For example, the code for -10dB level in positive polarity is as follows. Exclusive ORing each bit with the code above yields the following. This code corresponds to a -10dB code with negative polarity. Convert the code to an absolute value like this,
Figure 1 shows an example in which the level for each 2dB step is configured using logic gates. In Figure 1, 1 is the input terminal for the code, and 2 is the exclusive terminal for converting to an absolute value.
OR gate, 3 is a logic gate for extracting each level, 4 is an OR gate for displaying bar graphs as in the past, since simply displaying each level would be a spot display and difficult to see visually, 5 For example, when the display moves dynamically due to a music signal, etc., the brightness of the display element (for example, an LED) becomes low, and the brightness is modulated by the signal, making it difficult to see. To eliminate this problem, we use a monostable multivibrator that can be used for a fixed period of time. 6 is a display element.
In this example, there is no problem as long as the time width of continuous "1" of the input code of this monostable multivibrator is shorter than the output time width T of the monostable multivibrator of 5. When a "1" code is input, the display element should normally continue to light up, but if the monostable multivibrator 5 is an edge trigger type, only the rising edge of the first "1" is input. After a time T has elapsed after being triggered, the light may turn off and no longer light up. This case is shown in Figure 2a.
Shown in ~c. Fig. 2a shows a case where a single "1" is applied to the input of the monostable multivibrator 5, and Fig. 2b shows a case where an intermittent "1" is applied to the input of the monostable multivibrator 5.
Figure c shows the case where continuous "1"s are applied. The present invention eliminates the above-mentioned drawbacks of the conventional circuit, and eliminates the exclusive OR in the conventional circuit shown in Figure 1.
The circuit configuration before the gate 2 is shown in FIG. In FIG. 3, 7 is a complementary offset binary code input terminal, 8 is an AND gate, 9 is an output terminal of AND gate 8, 2 is an exclusive OR gate, and 10 is a clock pulse application terminal. In the present invention, a clock pulse that is bit-synchronized with the complementary offset binary code is ANDed with the complementary offset binary code, a sign and an absolute value code are created from the AND output, and this output is output for each bit. The desired level detection gate circuit input from the . Figures 4a, b, and c show the relationship among the code pulse (for example), clock pulse, AND gate output, and monostable multi-output of the level display circuit of the present invention; ”, b is intermittent “1”, c
is the case of continuous "1", and the display element 6 can continue to be lit even in the case of continuous "1". As is clear from the above explanation, according to the present invention, even if a pulse having a pulse width considerably longer than the preset time constant of the single multivibrator is input to the single multivibrator, the desired level can be displayed. , it is possible to control the level display with high precision from AC signals to DC signals.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional level display circuit.
Figures 2a, b, and c are explanatory diagrams of the operation of conventional level display circuits, Figure 3 is a block diagram of the main parts of a level display circuit according to an embodiment of the present invention, and Figures 4a, b, and c are diagrams showing the operation of conventional level display circuits. FIG. 3 is an explanatory diagram of the operation of the level display circuit of the present invention. 1... Input terminal, 2... OR gate, 3... Logic gate, 4... OR gate, 5... Monostable multivibrator, 6... Display element, 7... Input terminal, 8... AND gate, 9...Output terminal, 10
...Clock pulse application terminal.

Claims (1)

[Scope of utility model registration request] A clock pulse bit-synchronized with the complementary offset binary code and a clock pulse synchronized with the complementary offset binary code.
first logic circuit means which performs an AND with the MSB, and also performs an AND between the clock pulse and each of the other bit outputs; a second logic circuit means for obtaining a plurality of code bit outputs converted into absolute values by performing an exclusive AND with a logical product output; and a third logic circuit means to which the plurality of code bit outputs are input and obtain a plurality of display level outputs. A level display circuit comprising logic circuit means, a monostable multivibrator which receives the display level output of the third logic circuit means, and a light emitting element that emits light based on the output of the monostable multivibrator.