JPS63310027A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To detect an abnormal operation of a CPU writing data in excess of a stack memory area by providing a register setting a permissible maximum consecutive number of time data of a CALL instruction. CONSTITUTION:A data representing the permissible maximum consecutive number of times of a CALL instruction is set to a register 3. An up-down counter 2 is cleared by a clear decode signal of a signal line 8 when an instruction decode circuit 1 decodes a counter clear instruction, counted up by a CALL decode signal of a signal line 6 when the circuit 1 decodes the CALL instruction and counted down by a RET decode signal of a signal line 7 when the circuit 1 decodes a RET instruction. A comparator circuit 4 compares an output 9 of the register 3 with an output 10 of the counter 2 and outputs a detection signal to an interruption generating circuit 5 through a signal line 11 when the output 10 of the counter 2 exceeds an output 9 of the register 3. The circuit 5 generates interrupt when the detection signal is inputted.

Description

Detailed Description of the Invention (1) [Objective of the Invention] (Industrial Application Field) The present invention is directed to a central processing unit (cpu) such as a microprocessor or an l-chip microcomputer.
2) relates to a semiconductor integrated circuit having a function of 2), and a circuit for monitoring the quality of a storage area when data is stored in a stack memory area.

(Prior Art) In general, microcomputers (hereinafter abbreviated as microcomputers) have stack pointers as hardware and subroutine call instructions ( CALL) and a return instruction (RET).The stack pointer is usually set to an upper address in the memory area as an initial value.The subroutine is executed in the following steps.That is, the main program If there is a CALL instruction in the middle of the process, the address of the next instruction after this CALL instruction (the contents of the address counter) is saved in the memory area at the address indicated by the stack pointer, and the process moves to the start address of the subroutine and executes the subroutine. At this time, the stack pointer is decremented and points to the address of the memory area to be saved next.When the last 0RET instruction of the above subroutine is executed, the address stored in the memory ( read the return address), move to this address, and resume execution from the middle of the main program.At this time, 1!i, the stack pointer is incremented and returns to the value before the above subroutine was called.In addition, the above subroutine If there is a CALL instruction again in the middle of the process, the address of the instruction to be executed next after the CALL instruction is saved and stored in the memory area at the address indicated by the stack pointer, and another subroutine is executed. The stack pointer is decremented at the same time as moving to the first address of Then, when the execution of the above-mentioned subroutine is finished and the last RET instruction is executed, the return address is read out, and execution is resumed from the middle of the original subroutine, and the stack pointer is incremented, as described above. I'll keep it.

As mentioned above, when executing a subroutine, CALL
When instructions are executed successively, the addresses are stored back in the memory areas that are sequentially addressed as the stack pointer is decremented.

However, if the program runs out of control for some reason, or if the CALL instruction is repeated for more than a pre-allowed number of times, the storage of the return address in the memory area will also be repeated. This causes the above storage to be performed outside the memory area pre-allocated for storing the return address.As a result, if programs or data were previously stored in this area, these programs and data will be lost. There was a problem in that the microcomputer itself was destroyed and the microcomputer itself became uncontrollable.

Note that such problems occur not only in subroutine processing using the above-mentioned CALL and RET instructions, but also in other processing that uses the stack pointer and part of the stack memory area (register data processing using the PUSH and POP instructions). The same problem occurs during temporary save processing.

(Problems to be Solved by the Invention) As described above, the present invention solves the problem that when writing is performed in memory beyond the stack memory area due to a program error or runaway, the program or data in this part is This was developed to solve the problem of corruption, and it can detect abnormalities in CPU operation that attempt to write beyond the stack memory area, and prevents the destruction of programs and data outside the stack memory area. An object of the present invention is to provide a semiconductor integrated circuit that can prevent the above problems.

[Configuration of the Invention (Means for Solving Problems) A semiconductor integrated circuit of the present invention is a semiconductor integrated circuit having a CPU function, and includes an instruction decoding circuit.

an up/down counter that counts up or down in response to a predetermined decode output of the instruction decode circuit; a register that stores predetermined data;
The present invention is characterized by comprising a comparison circuit that compares the magnitude relationship between the output of this register and the output of the up-down counter and generates a running output according to this magnitude relationship. (Function) For example, when executing a subroutine, CALL Command, R
If the up/down counter is counted in the opposite direction with the execution of the ET instruction, and the maximum allowable consecutive number of CALL instructions corresponding to the stack memory area is set in register J1, the count value of the up/down counter will be stored in the register. It is now possible to detect an abnormality in the CPU operation using a comparison circuit when the value exceeds the value of It can be prevented. Furthermore, when the CALL instruction has never been executed or the CALL instruction and the RgT instruction have been executed the same number of times, the underflow output obtained from the counter when the RET instruction is executed is used to detect an abnormality in the CPU operation. It can be used as output.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a circuit formed on the same semiconductor chip as a microprocessor. Wholesale.

1 is an instruction decoding circuit, and CA of the instruction code
When the LL instruction is decoded, K outputs the CALL decode signal to the signal line 6, and when the RET instruction is decoded, the RET decode signal is output to the signal @7, and the counter clear instruction (a dedicated instruction code may be used, or another instruction When decoding the I
A clear decode signal is output to Ii times Hs. 2 is up/down data, it is cleared when the above clear decode signal is input, it counts up when the above CALL decode signal is input, and the above RET 5''2-do1
Countdown when the next number is entered. 3 is CALI
, is a register that stores data representing the maximum allowable number of consecutive instructions. 4 compares the output 9 of the register 3 and the output 10 of the up/down counter 2, and the former 9
When the latter value 10 exceeds the value , a detection signal is output to the signal line 11. Reference numeral 5 denotes an interrupt generation circuit, which generates an interrupt when the detection signal is input.

Next, the operation of the above configuration will be explained. First, as an initial setting, a clear decode signal is generated on the signal line 8 by manually inputting a counter clear command to the command decode circuit 1, and the up/down counter 2 is cleared. Also,
Register 3 is set with data representing the maximum allowable number of consecutive CALL instructions. The maximum allowed consecutive number of times is
This is the maximum number of consecutively executed 0ALL instructions when the program scheduled to be executed is operating normally.

However, here, continuous means CALL instruction and CAI
, L instruction, and there is no RET instruction between them. In this example, the maximum number of consecutive times is set to 4. Next, execute the main program. When the %CALL instruction is executed during execution of the main program, the up/down counter 2 counts up due to the CALL decode signal outputted to the signal line 6, and the count value becomes r l JK. Next, when the CALL instruction is executed again, the count is increased in the same way as above, and the count value becomes ``2''.Next, when the RET instruction is executed, the signal 1
1! ! The up/down counter 2 counts down according to the RET decode signal output to 7, and the count value becomes r.
Become lJ.

Next, when the uT instruction is executed again, the countdown is performed in the same manner as above, and the count value becomes "0".

The above is an example of normal normal operation.

On the other hand, for some reason, the CPU operation goes out of control and C
A case will be described in which the ALL instruction is executed five times in succession, which is greater than the set value 4. When the CALL instruction is executed four times in succession, the count increases as described above each time the CALL instruction is executed, and the count value becomes "4". In this state, SaraK CAL
When the L instruction is executed, the sicant value becomes "5" due to the count up. At this time, the value of register 3 is set to "4" in advance.
”, the comparator circuit 4 outputs a detection signal to the signal line 11. As a result, the interrupt generation circuit 5 operates to generate an interrupt, and a predetermined routine for runaway prevention processing is executed.

FIG. 2 shows another embodiment, which differs from the previous embodiment in that the underflow output of the up/down counter 2 is led to the interrupt generation circuit 5 by the signal 912 as another input. Since the parts are different and the others are the same, they are given the same reference numerals. In this embodiment, if the CALL instruction is executed consecutively exceeding the maximum allowable number of consecutive times,
An interrupt occurs in the same manner as in the previous embodiment. moreover,
In this embodiment, a case will be described in which the RET command is executed when the count value of the up/down counter 2 is rol. If the count value of up/down counter 2 is "0", it means that the CALL instruction has never been executed after up/down counter 2 has been cleared, or that the CALL instruction and the RET instruction have been executed the same number of times. It's one or the other. Therefore, in this way, the corresponding C
Executing the part T instruction while the ALL instruction is not being executed is not a normal situation, and for some reason the CPU
If the operation goes out of control, an underflow signal is output to the signal line 12 as the up/down counter 2 counts down. This underflow signal is an output that detects the runaway of the cpυ operation, and based on this signal, the interrupt generation circuit 5 generates an interrupt, and a processing routine for preventing runaway is executed.

Incidentally, in the description of each of the above embodiments, abnormalities due to fi and runaway of CPU operation were detected, but abnormalities due to other causes (for example, program errors) K can also be detected. For example, a subroutine may call itself. In this case, the above call is repeated until a certain condition is met. However,
As explained earlier, each time a CALL instruction is executed, the data is returned to the stack memory pointed to by the stack pointer.

Addresses are stored. If the return address is stored beyond the area allocated as the stack memory before a certain condition of the subroutine is met, the program and data previously stored in this area may be destroyed. Put it away. However, before the return address is stored beyond the area of the stack memory, the count value of the up/down counter 2 exceeds the set value of the register 3, so that an abnormality is detected. That is, for example, if the stack memory area is 100 addresses, register 1IcrloOJ is set. If you get the hang of it,
After executing the CALL instruction 100 times to fill the stack memory area and storing the seat address, if the CALL instruction is further executed, an abnormality is detected. Then, an interrupt can be generated based on this abnormality detection output, and a processing routine for preventing runaway can be activated.

Further, in each of the above embodiments, the case of subroutine processing using the CALL instruction and the RET instruction has been explained, but other processing using the stack pointer and stack memory (PUSI (combination of instruction and POP instruction, or C
The above implementation can also be implemented by changing the instruction decoding circuit to output a counter control signal by decoding the above-mentioned PUSH instruction etc. in a process that temporarily saves register data using other specific instructions that the PU has. You can get the behavior according to the example.

[Effects of the Invention] As described above, the semiconductor integrated circuit of the present invention has an up/down counter that counts up and down in response to the execution of each instruction in a specific combination of instructions. Since the value of the registered register and the value of the counter are compared in magnitude, it is possible to detect an abnormality in the CPU operation that attempts to write beyond the area of the stack memory. Therefore, by activating a predetermined processing routine based on this detection output, runaway CPU operation and destruction of programs and data outside the stack memory area can be prevented.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of a semiconductor integrated circuit according to the present invention, and FIG. 2 is a block diagram showing another embodiment. 1... Instruction decode circuit, 2... Up/down counter, 3... Register, 4... Comparison circuit, 5...
Interrupt generation circuit.

Claims (4)

[Claims] (1) In a semiconductor integrated circuit having a CPU function, an instruction decode circuit, an up-counter or an up-down counter that counts up or down according to a predetermined decode output of the instruction decode circuit, a register that stores predetermined data, and this register. 1. A semiconductor integrated circuit comprising: a comparison circuit that compares the magnitude relationship between the output of the up-down counter and the output of the up-down counter, and generates an output according to the magnitude relationship. (2) The instruction decode circuit controls counting of the up/down counter by a decode output corresponding to each instruction in a specific combination of instructions regarding the use of the stack memory area, and the register is configured to control the up/down counter according to a decode output corresponding to each instruction in a specific combination of instructions regarding the use of the stack memory area, 2. The semiconductor integrated circuit according to claim 1, wherein data representing a maximum allowable number of consecutive instructions is stored. (3) The semiconductor integrated circuit according to claim 1 or 2, wherein a predetermined processing routine of a CPU operation is activated by a predetermined output of the comparison circuit. (4) CP is determined by each of the predetermined output of the comparison circuit and the underflow output of the up/down counter.
The semiconductor integrated circuit according to claim 1 or 2, characterized in that a predetermined processing routine for U operation is activated.