JPS63309043A - Data transmission system - Google Patents

Abstract

PURPOSE:To evade the entrance of a system into a deadlock state owing to a noise, etc., appearing on a bus by allowing a terminal device to detect control information for obtaining control right being sent out on the bus during data transfer and release the bus automatically as a master station. CONSTITUTION:When the terminal device connected to a bus network operates as the master station, the terminal obtains the control right of an external bus by sending out control information S to the external bus, sends out serial clock data SCL to a serial clock SCL bus to start transfer operation, and confirms the end of transfer operation, thereby finishing the transfer operation and also deciding whether or not stop control information P on the external bus is detected during the transfer operation. When the stop control information P is generated on the external bus during the data transfer and the losing of the control right of the external bus is detected, the stop control information P is generated and the transfer is finished after the external bus is released. Consequently, the entrance of the system into the deadlock state owing to a noise appearing on the bus can be evaded.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Industrial field of application B1 Overview of the invention C1 Prior art 0 Problems to be solved by the invention E1 Means for solving the problems F0 Effects G. Example (G-1) Structure of the example ( Figures 1 to 3) (G-2)
Operation of the Embodiment (Figs. 4 and 5) H1 Effect of the Invention A, Industrial Field of Application The present invention acquires control over the bus by transmitting control information onto the bus and controls data. A plurality of terminal devices that can operate as a master station that transfers data and as a slave station that receives data transferred on the bus by detecting control information on the bus are connected via a bus network. The present invention relates to a data transmission system that performs data transmission using multi-master operation.

B1 Summary of the Invention The present invention operates as a master station that acquires control of the bus and transfers data by transmitting control information on the bus, and also operates as a master station that transfers data by acquiring control over the bus by transmitting control information on the bus. In a data transmission system in which multiple terminal devices capable of operating as slave stations that receive data transferred via a bus network are connected via a bus network and perform data transmission using multi-master operation, the master station By detecting that the system has lost control of the bus and automatically releasing the bus, the system is prevented from falling into a deadlock state due to noise mixed into the bus.

C1 Conventional technology Traditionally, a so-called microprocessor (CPU) is built in as a system controller, etc., and data is transmitted between the CPU for system control and external devices and various devices inside the device to control various functional blocks. Various electronic devices are provided that perform operation control, and data transmission is performed by connecting the system control CPU, external devices, and various devices inside the device via a bus network as shown in Figure 6, for example. In the system, data is transmitted between various devices using serial transmission.

The data transmission system shown in FIG.
．． Two bidirectional buses 63 pulled up via 62
．． 64, each CPU 6 of various devices such as system controller (roller 651 function block 66 and external device 67)
5A, 66A, and 67A are interfaces 65, respectively.
The bidirectional bus 63.64 via B, 66B, 67B
, and data transmission is performed by serial transmission between the various devices mentioned above using positive logic wired AND logic.

In this data transmission system, one bidirectional bus 63 is connected to a serial clock (SCL) sent from a master station.
The other bidirectional bus 64 is a transmission line for serial data (S04) sent from the master station or slave station, and as shown in FIG. 1” SD in state
Control information is given by changing the logical value of the A bus 64, and the S
Start transferring the change from DA logic “1” to logic “0” (
start) control n information (S), and from the logic "0" of the above SDA to the logic r1. A change in the data is defined as transfer end (stop) control information (P), and a change in the data transferred on the SDA bus 64 is allowed only when the SCL bus 63 is in the logic "1" state. Various devices such as the system controller 651 function Broncro and the external device 67 acquire control of the bus by sending start control information (S) onto the bidirectional bus 63, 64, and the serial clock (S).
CL) and serial data (SDA), transmits stop control information (P), and operates as a master station that relinquishes control of the bus. When the control information (S) is detected, each slave station has the function of receiving the data transferred from the master station and operating as an addressed slave station, and by multi-master operation via the above bus network, Data transmission is now possible.

D9 Problems to be Solved by the Invention By the way, as described above, a plurality of terminal devices connected via a bus network, that is, various devices such as the system controller 652 functional block 66 and external device 67, each have control over the bus. In a data transmission system that performs data transmission using multi-master operation, which acquires a terminal and operates as a master station, there is a risk of malfunction at each end due to noise mixed into the bus. During data transfer, noise enters the bus, and as shown in Figure 8, when the SCL bus is at logic "1", the SDA bus changes from logic "1" to logic "0" due to noise (N). and start control information (
When S゛) is generated on the bus, the terminal device operating as the master station switches to the slave station operating state by detecting the start information (S゛), and all terminal devices become slave stations. Stomb control ill by operating as a station
It continues to wait for information (P), and unless stop control information is generated due to noise, it will fall into an uncontrollable dendronk state.

Therefore, the present invention solves the above-mentioned problems by transmitting control information onto the bus to acquire control over the bus and operate as a master station to transfer data.
Multiple terminal devices that can operate as slave stations that receive data transferred on the bus by detecting control information on the bus are connected via a bus network and perform data transmission using multi-master operation. In a data transmission system, the present invention aims to provide a master station with a function to avoid the system from falling into a dendrochronic state due to noise mixed into the bus, thereby ensuring normal operation of the system.

Means for Solving Problem No. 1 The present invention solves the above-mentioned problems by providing a master station that acquires control of the bus by transmitting control information onto the bus and transfers data. Multiple terminal devices that can operate as a slave station and receive data transferred on the bus by detecting control information on the bus are connected via a bus network, resulting in multi-master operation. In a data transmission system that performs data transmission, each terminal device includes a detection means for detecting that control of the bus has been lost during data transfer, and a control means for releasing the bus in accordance with the detection output of the detection means. The bus is automatically released when a terminal device operating as a master station loses control of the bus.

F0 operation In the data transmission system according to the present invention, when the terminal device connected to the path network operates as a master station, the external bus is controlled by sending start control '1 information (S) onto the external bus. Obtain control, send serial clock data (SCL) to SCL Hass, and
Start the transfer operation as shown in the flowchart in the figure,
The end of the transfer operation is confirmed (step 1), and the transfer operation is terminated. At the same time, it is determined whether or not the stop-based tall information (P) was loaded on the external bus during the transfer operation (step 2), and the data transfer is completed. When stop control information (P) is generated on the external bus during the process and it is detected in step 2 that control of the external bus has been lost, stop control information (P) is generated in the next step 3. The transfer is completed after releasing the external bus.

G. Embodiment (C;-1) Structure of the Embodiment The embodiment described below with reference to the drawings is an example in which the present invention is applied to the data transmission system shown in FIG. 6 above. As shown in the data format, the first byte immediately after the start control information (S) is the system control n data, the 7-bint slave address data that specifies the slave station, and the transmission direction of the data from the second byte onward. 1-bit read/write (R
/W) Data is transmitted in units of 8 bits while handshaking is performed using a reception confirmation signal (ACK).

In the first block diagram showing a specific configuration of a terminal device constituting the data transmission system according to the present invention, the terminal device 1 includes a first input/output coupler 1-2 externally connected to an SCL bus and an SDA A CPU 6 connected via an internal bus to an interface (1/F) block 5 provided with a second human power port 3 externally connected to the bus and a human power port 4 to which an evening synchronization pulse (SEC) is supplied. Prepare,
This CPU 6 supplies the basic clock (CLOC), read signal (READ), and write signal (WRITE) to the 1/F block 5, and also communicates with various registers 7.8, 9.10 via the internal bus. It exchanges data, determines the state of the I/F block 5, and controls its operation.

Connected to the first input/output boat 2 is an SCL controller 11 that inputs and outputs serial clock data (SCL) to an external SCL bus and forms various operation timing pulses based on the serial clock data (SCL). has been done.

Further, an SDA controller 12 is connected to the second input/output boat 3, which inputs and outputs serial data (SDA) to and from an external SDA bus, and also forms a reception confirmation signal (ACK). Furthermore, an external synchronization circuit 13 for externally synchronizing the operation of the I/F block 5 is connected to the input port 4.

The SCL controller 11 forms serial clock data (SCL) based on clock pulses supplied from the clock generator 14 in the master mode, and outputs it from the first input/output port 2 to the SCL bus. Further, the SCL controller 11 is configured to
Serial clock data (SCL) on the bus is supplied to the bus busy detection unit 15 and the loss of control detection unit 16.

Further, the SCL controller 11 forms various timing pulses based on the serial clock data (SCL) on the SCL bus and supplies them to the status control register 7, data shift register 8, SDA controller 12, and comparator 17. There is.

The SDA controller 12 outputs the data transferred from the data shift register 8 in the transmission mode as serial data (SDA) from the second input/output port 3 to the SDA bus. In addition, the above SDA
In the reception mode, the controller 12 inputs the serial data (SDA) transferred from the SDA bus via the second input/output port 3 to the data shift register 8, and also inputs the serial data (SDA) transferred from the SDA bus to the data shift register 8.
) is completely received, a reception confirmation signal (ACK) is generated and outputted from the second input/output port 3 to the SDA bus. Further, the SDA controller 12 includes the SDA controller 12,
Serial data (SD^) on the DA bus is supplied to the bus busy detection section 15 and the loss of control detection section 16.

The bus busy detection unit 15 receives serial clock data (SCL) supplied from the SCL controller 11.
The start control information (S) is detected by detecting the start control information (S) and stop control information (P) on the external bus based on the serial data (SDA) supplied from the SDA controller 12. The bus busy state is detected from until the stop control information (P) is detected, and the detection output is supplied to the status control register 7.

The control loss detection unit 16 detects serial clock data (SCL) supplied from the SCL controller 11 and the SDA controller 12 in the master mode.
Loss of control of the bus is detected by detecting the start control information (S) generated externally on the bus using the serial data (SDA) supplied from・Supply to control register 7.

The comparator 17 is connected to the data shift register 8.
1 byte of data transferred from the master station via the SDA bus immediately after the start control TJ information (S) and its own slave address data set in advance in the slave address data 9 by the CPU 6. The comparison is made to detect a match, and it is also detected that the 1-byte data transferred immediately after the start control information (S) is all logic "0", and the detection output is sent to the status control. Supplied to register 7.

As shown in FIG. 3, the status/control register 7 includes upper 4 bits to which data can be written/read from the CPU 6 via an internal bus, and
It consists of a lower 4-bit register whose data content differs depending on whether it is written or read by U6.

The upper 4 bits of the status control register 7 indicate master mode with logic "1", slave mode with logic "0", MST and node, transmit mode with logic "1", and receive mode with logic "1". TRX indicated by “0”
A BB bit indicates a state in which the external bus is in use with a logic "1", a logic "0" indicates a non-use state of the external bus, and a PIN bit for issuing an interrupt to the CPU 6.

The MST bit is set by the CPU 6 when it is necessary to control the external bus, and is reset after creating stop control information (CP), and is transferred when control of the external bus is lost. It is reset when the internal bytes have been transferred. And the above status
The control register 7 causes the SCL controller 11 to form serial clock data (SCL) for data transmission in the master mode in which the MST bit is set, and causes the SCL controller 11 to form serial clock data (SCL) for data transmission to the first human output port 2.
Serial clock data (SCL) from external SCL
Performs control operations to output to the bus.

Further, the TRX bit is set by the CPU 6 when acquiring control of the external bus and operating in master mode, and is reset after creating stop control information (P). It is reset when the transfer of the byte being transferred is completed if the user loses the right to do so. Furthermore, the TRX pinpoint is reset by the R/W data following the slave address data in the 1-byte data immediately after the start control information (S), and in master mode, if R/W = "O". If there is no change and R/W=rl, it is reset, and in slave mode, if R/W=rO, there is no change, and if R/W-"i", it is set. When the status control register 7c is in the transmission mode in which the TRX bit is set, the data in the data shift register 8 is converted into serial data (SD^) and synchronized with the serial clock data (SCL). SDA controller 1
2, and performs a control operation to output serial data (SDA) from the second input/output boat 3 to the external SDA bus. The status control register 7 also stores a serial number transferred from the external SDA bus to the SDA controller 12 via the second input/output port 3 when the TRX focus is reset. When the data (SDA) is input to the data shift register 8 and the serial data (SDA) is completely received, a reception confirmation signal (ACK) is sent.
by causing the SDA controller 12 to form the second
A control operation is performed to output a reception confirmation signal (ACK) from the human output port 3 to the external SDA bus.

Furthermore, the BB focus is determined by the bus busy detection section 15.
is set when start control information (S) on the external bus is detected, and reset when stop control information (P) on the external bus is detected. Above CPU6
When it is necessary to acquire control of the external bus and operate in master mode, when the BB bit is reset and the external bus is not in use, the TRX bit is set and the start control information ( S) on the external bus to perform a control operation to acquire bus control.

Furthermore, the PIN bit is set each time the data shift register 8 is written/read, and the PIN bit is set every time the data shift register 8 is written/read.
It is reset by the CL controller 11 every time the transmission or reception of one byte of data ends. Then, when the PIN bit is reset, the status control register 7 supplies an interrupt control signal to the interrupt control unit 18 to control the CPU 6.
interrupt to notify the end of data transfer.

Furthermore, the lower 4 bits of the status control register 7, which are write-only for the software, are the ESO pin which specifies permission/inhibition of the data transmission operation to the external bus by the T/F block 5, and the 1/2 bits mentioned above.
BC indicating the number of bits of data transmitted and received by F bronc 5
,,BC,.

BC, bit. Furthermore, the lower 4 bits of the status control register 7, which are read-only for the software, are the A and L pinto indicating the state of loss of control over the external bus, and the AAS pinto and AD0 bits indicating the address designation state by the master station. This is an LRB bit indicating the data reception status.

The AL bit is set to the control loss detection unit 1 when control of the external bus is lost in the master transmission mode.
It is set by the detection output of the data shift register 8, and is reset every time the data shift register 8 is written/read. In addition, the AL bit is set to the status control register 7 while being addressed in slave mode.
It is set when data is written to the , indicating that the written data is invalid. When the AL bit is set in the mask mode, the status control register 7 resets the TRX bit and generates stop control information (P) when the transfer of the byte being transferred is completed. A control operation is performed to output to the bus and reset the MST bit.

The AAS bit is set at the output of the comparator 17 when addressed by the master station, and is reset each time the data shift register 8 is written/read. Further, the AD bit is sent at the output of the comparator 17 when the 1-byte data immediately after the start control information (S) transferred from the master station is all logic "0", and the bus busy detection is performed. The unit 15 is reset when it detects start control information (S) or stop control information (P) on the external bus. Furthermore, the LRB bit is the reception confirmation signal (to AC) generated on the receiver side during the above master mode.
maintain the state of That is, when the receiver returns a reception confirmation signal (ACK), LRB=rQj, indicating that data has been received normally.

Further, the control register 10 controls the speed of serial clock data (SCL) generated in the operation mode and master operation mode of this interface circuit, and uses a 4-pin register.

(G-2) Operation of Embodiment In this embodiment, when the terminal device l operates as a master station, the CPU 6 instructs the control register 10 to send start control information (S) via the internal bus. The above SCL controller 11 and SDA
The controller 12 sends start control information (
S), it acquires control of the external bus and transmits serial clock data (SCL) to the SCL bus.
) from the SCL controller 11 to start the transfer operation shown in the flowchart of FIG.
The data transfer operation is confirmed by the above PIN bit (step 1) and the transfer operation is terminated, and stop control information (P) is generated on the external bus during the data transfer, and control of the external bus is lost in the above step 2. The above support device 1! When the loss detection unit 16 detects (step 2),
The above status core) C1-/I/register 7 is the above SCL controller 11 and SDA controller 12
Then, stop control information (P) is generated on the external bus (step 3), the external bus is released, and the transfer ends. By automatically releasing the bus when the terminal device 1 operating as a master station loses control of the bus, it is possible to prevent the system from falling into a de-locked state due to noise entering the bus. avoid,
Normal operation of the system can be ensured.

Further, as shown in the flowchart of FIG. 5, the terminal device 1 in this embodiment detects the start control information (S) on the external bus in the bus busy detection section 15 (step 1), and then communicates with the slave station. First, the status control register 7 resets the abord timer (step 2), and then in step 3, it performs an operation to determine whether or not data has been transferred from the master station, and the determination result is rYEsJ, that is, if there is transfer data, the data is fetched from the data shift register 8 to the CPU 6 (step 4), and if the judgment result in step 3 is "NO", that is, there is no transfer data, the next step is executed. 5, it is determined whether or not the above-mentioned abord timer has overflowed, and if no data has been transferred within a predetermined period until the above-mentioned abord timer overflows, the bus busy flag is set to recent (step 5). 6) Generate stop control n information (P) on the external bus from the SCI, controller 11, and SDA controller 12 (step 7), and forcibly release the external bus. In this way, when data is not transferred through the external bus for a predetermined period of time or more, the terminal device f1 operating as a slave station without control over the external bus forcibly releases the bus. Accordingly, it is possible to recover the system from a deadlock state caused by noise mixed into the external bus, and to ensure normal operation of the system.

H. Effects of the Invention According to the present invention, the master station obtains control of the bus by transmitting control information onto the bus and operates as a master station to transfer data, and also by detecting the control information on the bus. Multiple terminal devices that can operate as slave stations that receive data transferred on the bus are connected to the bus.
In a data transmission system that is connected via a network and performs data transmission using multi-master operation, a detection means detects that a terminal device operating as a master station has lost control of the bus during data transfer. Since the bus is automatically released, the master station is provided with a function to prevent the system from falling into a deadlock state due to noise mixed into the bus, thereby ensuring normal operation of the system.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a specific example of a terminal device constituting a data transmission system according to the present invention, and FIG. 2 is a schematic diagram showing an example of a data format in the data transmission system. FIG. 4 is a schematic diagram showing the configuration of a status control register constituting the terminal device, FIG. 4 is a flowchart showing the operation of the terminal device as a master station, and FIG. 5 is a flowchart showing the operation of the terminal device as a slave station. 2 is a flowchart showing the operation of FIG. Fig. 6 is a schematic diagram showing the configuration of a data transmission system using a general HAS network, UA 7 is a schematic diagram without showing the bus system of the data transmission system, and Fig. 8 is a schematic diagram showing the configuration of a data transmission system using a general HAS network. FIG. 2 is a schematic diagram for explaining malfunctions caused by noise on a lotus in a data transmission system. l...Terminal device 2.3...I/O boat 5...Interface block 6...CPtJ 7...Status control register 8...Data shift register 9...Slave address register 10. ... Control register 11 ... SCL controller 12 ... SDA controller 14 ... Clock generator 15 ... Bus busy detection section 16 ... Loss of control detection section 17 ... Comparator patent expert Sony stock company

Claims (1)

[Claims] Operates as a master station that acquires control of the bus by transmitting control information onto the bus and transfers data, and also transfers data on the bus by detecting control information on the bus. In a data transmission system in which multiple terminal devices operating as slave stations that receive incoming data are connected via a bus network and data is transmitted using multi-master operation, control of the bus is lost during data transfer. Each terminal device is provided with a detection means for detecting this, and a control means for releasing the bus in accordance with the detection output of the detection means, and when the terminal device operating as a master station loses control of the bus. A data transmission system characterized in that the above-mentioned bus is automatically released.