JPS63309027A - Current source circuit - Google Patents

Abstract

PURPOSE:To easily constitute a high-accuracy constant current source group while making the width of grounding wiring narrower than before and, therefore, reducing chip area by applying a potential lower than the source potential of an N-channel MOS field effect transistor(FET) present in each well. CONSTITUTION:When the source potentials of N-channel transistors(TR) 101-107 for constant current generation need to be raised from the ground zero potential because their grounding wiring is narrow, the potentials of wells are controlled according to the raising quantity to control the threshold values of the respective TRs 101-107 for constant current generation. Consequently, the current quantities of the respective TRs for constant current generation can be adjusted with high accuracy and even if the wiring is narrow, the constant current source group is composed of the TRs for constant current generation having current values nearly proportional to the gate sizes of the TRs.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a current source circuit, and particularly to a current source circuit that generates a constant current using a MOS field effect transistor.

2. Description of the Related Art Constant current source circuits using MOS field effect transistors are used for various purposes. As a conventional example of these, an example of a constant current source group in a segment current type D/A converter is shown in FIG. 101゜102.103,104
, 105, 106, 107 are N-channel MO5 type field effect transistors of equal size for constant current generation, and the sources 11, 12, 13, 14, 15,
16°17 is wiring 201.202.203.204
.

It is connected to ground terminal 1 via 205.206.207. Terminal 4 is a gate bias potential supply terminal to the transistor. The transistor is connected to a first output terminal 401 and a second output terminal via a switching part 3o00.
is connected to the output terminal 402 of. The switching section 3000 is composed of 7 pairs, that is, 14 N-channel MO5 type field effect transistors for switching current paths.
By controlling the gate-source voltages of the transistors 3011 and 3012, the path of the current flowing through the transistor 101 is determined to one of the output terminals 401 and 402, and similarly, each transistor pair, 3021-3022
．． 3031-3032.

3041-3042.3051-3052.

3o61, 3062, 30γ1, 3o72 are respectively,
Transistor 102, 103, 104゜105.106
．． The path of the current flowing through the circuit 107 is switched.

In the segment current type D/MU converter using the conventional constant current source group configured as described above, the signal obtained by decoding the input digital signal is supplied to the switching section 3000, and the output terminal 401 ,402
Controls the amount of current flowing from the

Problems to be Solved by the Invention However, in the above configuration, each of the constant current generating transistors 101, 102, 103, 104, 106, .
106.1o source 11.

12. Wiring connecting 13, 14, 15, 16, 1a and ground terminal 1 201.202.203.204゜205.
Due to the potential drop at 206.207, the sources 11, 12, 13, 14, 1 of each constant current generating transistor
5, 16.17 potential v1. .

vl2 + v13+ v14+ vl5 * vl6
+vl7 becomes higher potential than the zero potential of ground terminal 1,
Since the voltage between the gate and source of each constant current generating transistor is different, the current value of each constant current generating transistor is different even though the gate size is the same, and the linearity of D/MU conversion is deteriorated. N-channel MO3 type field effect transistor of equal size for each constant current generation 1o1゜102.10
The current values flowing through 3, 104, 105, 106, and 107 are respectively Ij+
．． I7, the source potential of each constant current generation transistor v111v12! v15Iv14Iv15Iv1
6. It is connected to v17 by the following formula. That is, ・・・・・・・・・・・・・・・(1) Coco Ks r2o1. r2oz, r2as, r2
aa, 7"20517"2061r207 respectively, wiring 201, 202.203゜204.205.
The resistance value is 206.207.

Also, II + 12 + ``x Engineering 4.'' 5. “6+
``7'' satisfies the following formula when the MO3 field effect transistor operates in the saturation region. That is, where μ, rr is the effective mobility of electrons, and W.

L is the channel width and channel length of the constant current generating transistor, respectively, and ε. 8 is the dielectric constant of the gate oxide film, Tox is the gate oxide film thickness, vGsk is the gate-source voltage of each constant current generation transistor, and VTk is the threshold of each constant current generation transistor. Since the source of each constant current generating transistor has the same potential as the well in which each transistor exists, the threshold value vTk (k=1 to 7) of each constant current generating transistor is equal. Therefore, the engineering depends on vG Sk. Also, the gate bias potential of the constant current generation transistor is set to V. If set to 0, vGS
k - vco V,k, and from equation (1) it is clear that crab v, k < vl and +1 (k = 1 to 6), so (
2) Equation 3. Therefore, Ik>”k++ (k=1 to 6).

This is one of the causes of deterioration in the linearity of the output current of the segment current type D/mu converter. In a D/mu converter with a conventional configuration, the wiring is set at 202.203°2 to the extent that lV + knee v+1l (i to j) does not affect the linearity error of the D/mu conversion.
04.205.208.207 must be thickened to reduce wiring resistance. For example, the gate width of the constant current generation transistor is 12 μm, the gate length is 6 μm, the grounding wire length is 2000 μm, and the maximum output current is 3 mm. 6 bits) D/
In the case of a system converter, in order to maintain 6-bit accuracy, the width of the ground wiring must be set to about 50 μm to allow for a margin, and the problem was that the ground wiring significantly increased the chip area. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a current source circuit in which the width of the grounding wiring is much narrower than in the past, thereby reducing the chip area and making it easy to configure a group of high-precision constant current sources. .

Means for Solving the Problems The above purpose is to generate a
A group of channel (or P-channel) MO5 type field effect transistors is divided into a plurality of wells and produced, and a voltage lower than the source potential of the above N-channel (or P-channel) MO3 type field effect transistor existing in each well is placed in each well. (or by applying a potential higher than the source potential).

According to the present invention, with the above-described configuration, in the N-channel (or P-channel) constant current generating transistor, the grounding wiring (or the V+ potential supply wiring) is thin, so that the source potential is reduced from the grounding zero potential. Lifting (or V
When the potential drop from + potential is large, if the threshold of each constant current generation transistor is controlled by controlling the potential of the well according to the amount of rise (or amount of potential drop), each constant current generation transistor The current feed can be adjusted with high precision, and even when the wiring is thin, a constant current source group consisting of constant current generating transistors having a current value approximately proportional to the gate size of the transistor can be configured.

Embodiment FIG. 1 shows a segment current method D as an embodiment of the present invention.
FIG. 2 is a configuration diagram of a constant current source group in a /mu converter. In Fig. 1, branches 501, 502° 503.504, +5
05.1506.507, 508 are P-type buried layers connected in series between the negative potential bias terminal SOO and the ground terminal 10, and nodes 61.82.83, θ4.65.
66.67 is the voltage dividing point of the negative potential bias, and N-channel MO3 type field effect transistors 101.102, 103, 104.10!5°1o of equal size for each constant current generation.
θ and 107 are connected to the P-type wells, respectively. The rest of the structure is the same as that of the conventional example shown in FIG.

The operation of the constant current source group of this embodiment configured as described above will be described below.

Current k (k-1) flowing through each constant current generating transistor
~7) is expressed by equation (2), where vG! The term −vTk in 3 can be rewritten as follows. That is, vGsk
'rk' vco-v+k 'Tk'=vao
(+vrk to vl) (c-=1~7)...
・・・・・・・・・(3) Here, vQQ + v+ is the bias potential supplied from terminal 4 to the gates of N-channel MO8 type field effect transistors of equal size for each constant current generation and each transistor. is the source potential of

Tsureuni (2), (3) Equation j li, v, +vTk
By keeping (k-1 to 7) almost constant, Ik(k
= 1 to 7) can be kept almost constant. Therefore, in this embodiment, vl in equation (3) is +vd k
In order to keep (k-1~end) almost constant, vlk(k=
:=1 to 7), the threshold value vTk (k-1 to 7) of each transistor is controlled by the well potential.

The relationship between the potential of the well where the transistor exists and the threshold is:
It is expressed by the following formula. That is, Vrk=vrko + r(,5'';j; animals(V +k
'sub k )-J7 Here, v and ko are the threshold values when the potential of the well is equal to the source potential of the constant current generation transistor in each well, and φ is the Fermi potential of the well. Yes, v
subk is the potential of each well, and γ is a constant expressed by the following equation. That is, here, q is the amount of charge of electrons, ε8 is the dielectric constant of silicon, and N is the impurity density of the well. In the example shown in FIG. 2, the N-type impurity density in the drain region is 1.5X1019Q11',
This figure shows the substrate bias effect when the well P-type impurity density is I x 1015 -3 and the gate oxide film thickness is 20 nu, and the change in threshold value is about 1/30th of the change in well potential. Therefore, +vT for vl in equation (3)
Since the amount of change in the term k is smaller than the amount of change in the well potential vsub k , it can be seen that the value of equation (3) can be adjusted with high accuracy. The value of v+ is calculated using k (1)
Although it is calculated by the formula, since the amount of change ΔIk in the force k due to an increase in k is smaller than the force k, it is possible to substitute a value for v+ with a value calculated without taking into account the ΔIk as k increases. can. Mie in engineering. Tookir2ok3r. Then, vl is expressed by the following equation. That is, (n = 7, k = 1 to 7) -----・-
--・(4) Regarding the second term of equation (4), ro=o, s
Ω, Eng. Figure 3 shows the situation when = 50 μm. For this situation at v+, +VTk at V+ in equation (3)
The well potential is controlled so that the value of vT is approximately constant.
control k.

V is on the monotonically increasing part of the upwardly convex quadratic curve, and in order to compensate for this increase with the change in '/Tk, we calculate the rate of change in V in the minute section of the curve in Figure 2. Make use of it.

According to this method, +vrk is added to v+ for all (k-1~
7) Squid, how many times td, which cannot be constant for
If vTk is controlled by the potential of the well such that v, j+vTI=vl+vT7, then k (k-1 to end) can be kept almost constant. In this case v, +v
The state of Tk is shown in FIG. 4(C). FIG. 4(A) shows the state of the source potential v, and FIG. 4(B) shows the threshold value vTk.
This is what it looks like. According to Figure 4, the variation in vl +vTk when the well potential is not controlled is 626 μV.
On the other hand, when the well potential is controlled, the variation in v and +v is 112,5 according to Fig. 4(C).
μV, V, + vrk (D variation has been improved to about one-fourth. In order to linearly decrease vTk as k increases as shown in Fig. 4 (B), Since the minute section can be regarded as a straight line, it is sufficient to increase the potential of the well linearly as k increases.
Mold buried layer 6o2゜603.504.505.506
．． 507 should have the same resistance value. Further, by controlling the potential applied from the terminal SOO, the rate of change in the potential of the well can be set arbitrarily. In addition, the P-type buried layer 501
．． The resistance value of 608 is determined so that the potential difference between the voltage dividing points 61 and 67 can be set to a desired potential difference while ensuring that the absolute value of the potential difference between the potential applied from the terminal 600 and the zero potential does not become too small. do it.

As described above, according to this practical example, by fabricating multiple constant current generating transistors in different wells and applying a controlled potential to each well, the source potential of each constant current generating transistor is different. In this case, it is possible to improve the linearity of a segment current type D/MU converter using a constant current generating transistor group consisting of a transistor group of equal gate size.

In the above embodiment, a method of compensating for the rise of the source potential of a constant current generating transistor group consisting of a transistor group of equal gate size from the ground zero potential was described, but a weighted current type D/MU converter In a constant current generation transistor group consisting of a group of transistors with different gate sizes, or a group of transistors with equal gate sizes combined in parallel in proportion to the weight, each constant current is weighted due to process variations. If the ratio of current values between the generation transistors differs from the desired ratio, by controlling the potential of the well where each constant current generation transistor exists,
A constant current source group consisting of constant current generating transistors having current values weighted to a desired ratio can be constructed, and the linearity of the weighted current type D/MU converter can be improved.

As described in detail, according to the present invention, when the source potential of an N-channel (or P-channel) MO5 field effect transistor that generates a constant current rises above the ground zero potential (or drops below the V+ potential), In this case, the constant current value can be controlled by controlling the potential of the well where the constant current generating transistor is located. When the source potential of the constant current generating transistor group fluctuates, the current value of each constant current generating transistor can be controlled to approximately a desired value. The present invention provides an integrated circuit in which the current value of each constant current generating transistor constituting a constant current generating transistor group is maintained at a value defined by the gate size,
+Potential supply wiring) can be made thinner, so the area of the integrated circuit can be reduced, which has a great practical effect.

Further, according to the present invention, when the current of each constant current generation transistor varies due to process variations, by controlling the potential of the well where each constant current generation transistor exists, it is possible to obtain a desired current value ratio. It can be made to have In an integrated circuit, the present invention makes it possible to make the ratio of current values of weighted constant current generation transistors almost match the ratio defined by the gate size even when there are process variations. Process variations can be tolerated when the total is reduced, which has a great practical effect.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a constant current source group in a segment current type D/MU converter according to an embodiment of the present invention, FIG. 2 is a characteristic diagram showing the substrate bias effect, and FIG. A characteristic diagram showing the amount of rise in the source potential of the constant current generating transistor in the converter. Fig. 4 is an explanatory diagram of the compensation method for the amount of rise in the source potential. Fig. 6 is a characteristic diagram showing the amount of rise in the source potential of the constant current generating transistor in the converter. FIG. 3 is a configuration diagram of a constant current source group. 101.102,103,104,106°10S,
107...N-channel MO3 type field effect transistor, 501. 502.503.504゜SO5,6
06, E507.508・=-P type buried layer, 500
...Negative potential bias terminal, 4...Gate bias potential supply terminal, 1.10...Ground terminal,
61.82, 63, 64, 65, 66.6...Division point of negative potential bias. Name of agent: Patent attorney Toshio Nakao and 1 other person61
~≦7− Partial pressure point of bias bias 101・+07−N
+ Yarnel MO5 Next field effect transistor 50Q-jIt lamp bias chicken 5DIA5Q8-' P-type workpiece 1 Fig. 1
3000-Swie/+Nzu part 3011 to 3072-KRanginuta Figure 2 Relationship between substrate voltage Vsvb and threshold voltage Vsub (V) ro = o, 5n, Io = 50aA Figure 3 r, 2 3 4 5 6'/4th
Figure T23t567 Figure 5

Claims (3)

[Claims] (1) In the constant current source group, each constant current source including an N-channel (or P-channel) MOS field effect transistor that generates a constant current is divided into a plurality of wells and manufactured, respectively.
In the well, the N channel (
1. A current source circuit comprising means for applying a potential lower than (or higher than) a source potential of a P-channel MOS field effect transistor. (2) Below the source potential of the N-channel (or P-channel) MOS field effect transistor present in each well (
Alternatively, a bias potential of (or higher than the source potential) is externally applied, the potential difference between the bias potential and the ground potential (or V^+ potential) is divided by a resistor, and the potential of the dividing point that generates the above-mentioned voltage is set to the above-mentioned voltage. 2. A current source circuit according to claim 1, further comprising means for supplying a current to each well. (3) Below the source potential of the N-channel (or P-channel) MOS field effect transistor present in each well (
or higher than the source potential), and a second bias potential of
Applying a bias potential from the outside, dividing the potential difference between the first bias potential and the second bias potential using a resistor,
2. The current source circuit according to claim 1, further comprising means for applying a potential at a voltage dividing point that generates said partial voltage to each of said wells.