JPS63308388A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain the high storage keeping capacity from the irradiating ultraviolet rays by a method wherein an ultraviolet ray absorber is provided inside an ultraviolet ray shielding structure. CONSTITUTION:An ultraviolet ray absorber 8 comprising e.g., polysilicon is formed encircling a floating gate 5 on a field oxide films 12 formed between a drain region 1 and a source region 3 through the intermediary of insulating films 13. In other words, any permeating ultraviolet rays are going to reach the floating gate 5 of a floating gate type MOS(FAMOS) while repeating irregular reflections passing through the field oxide films 12 and the insulating films 13 as the permeating channels but considerable level of permeating ultraviolet rays is absorbed by the ultraviolet ray absorber 8 provided halfway on the channels. Through these procedures, the permeating ultraviolet rays originally in minor level are further reduced so that the ultraviolet rays reaching the floating gate 5 may be notably attenuated to prevent the storage contents from being erased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that prevents erasure of stored contents by irradiation with ultraviolet rays.

[Prior Art] FIG. 3 is a schematic plan view of a conventional UPROM device, and FIG. 4 is a sectional view taken along TV-IV in FIG. 3.

Here, UPROM is a 70-Tingate type j., 10S (
FAMOS) Memory Bfff and Unerasabl
-e progra+able ROM.

The configuration will be explained below with reference to both figures.

Semiconductor substrate 1 as the drain of the FAMOS transistor
A pair of drain regions 1 formed in the semiconductor substrate 1 are spirally introduced from the outside to the inside of the device, and a gate electrode 2 connected to a control gate is provided inside the drain region 1 for separating each region formed in the semiconductor substrate 11. It is formed above the field oxide film 12 with an insulating film 13 interposed therebetween. Drain territory TL! A source region 3 is formed in the semiconductor substrate 11 as a source of the transistor so as to face the lower part of the gate electrode 2 at the tip of the fII region. A FAMO is formed by sandwiching an insulating film under the gate electrode 2 at the part where the north region 3 and the drain region 1 face each other.
A floating gate 5 of S is formed. In addition, a drain region 1 centered around the floating gate 5. A diffusion region 6 surrounds the gate electrode 2 and the 1-north region 3.
is formed in the semiconductor substrate 11, but not in the introduction portion of the drain region 1 and the gate electrode 2. A metal Ji11o made of, for example, an aluminum thin film is formed on the top surface so as to cover the entire device configured as described above (in FIG. 3, the top of the device is omitted for convenience), but this metal layer 10 is a diffusion region 6 and a contact portion 7
electrically connected via.

Further, a protective film 14 made of, for example, a glass coat is formed on the entire upper surface of the metal 8110 to protect the device.

Next, the operation of the LJPROM device will be explained.

When performing a memory operation, that is, a write operation, first the FA
A high voltage is applied to a drain region 1 connected to the drain of the MOS and a gate electrode 2 connected to a control gate, and then a low voltage is applied to a source region 3 connected to the source via a contact portion 4. Then, electrons are injected and held in the floating gate 5 of the FAMOS by avalanche breakdown, that is, an avalanche phenomenon. When the injected electrons are held in the floating gate 5, the semiconductor substrate 1 surrounded by the source region 3 and drain region 1 below
Since fRwi of 1 is made conductive as the channel Ffil, an I current flows from the source to the drain, that is, memory is retained.

However, when the electrons thus held in the floating gate 5 are irradiated with ultraviolet rays or the like, the electrons are excited and return to the semiconductor substrate 11, thereby erasing the stored contents. Therefore, by covering the memory storage section with the metal layer 10 and the contact section 7 and blocking the ultraviolet rays, the memory contents will not be erased even if the ultraviolet rays are irradiated.
It is a ROM.

[Problems to be Solved by the Invention] The conventional semiconductor memory device as described above does not have a sufficient structure to block ultraviolet rays. That is, as shown in FIG. 3, the memory storage section is surrounded by the metal layer 10 and the contact section 7, but the area where the drain region 1 and the gate electrode 2 are introduced from the outside (indicated by C'') Since the area (range) cannot be completely closed off, ultraviolet rays penetrate into this part.
FAI￥I reaches the floating gate 5 of the OS while repeating this process, so there is a problem that even if the ultraviolet rays of the mulberry are infiltrated for a long time, the memory contents may be erased by irradiation with ultraviolet rays for a long time. Ta.

The present invention was made to solve this problem, and an object of the present invention is to provide a semiconductor memory device that has high memory retention ability even when exposed to ultraviolet light.

[Means for Solving the Problems] A semiconductor memory device according to the present invention has an ultraviolet absorber provided inside a conventional ultraviolet shielding structure.

[Function] In the present invention, the ultraviolet absorber absorbs the invading ultraviolet rays and further attenuates the ultraviolet rays that reach the memory storage section compared to the conventional method.

[Embodiment FIG. 1 is a schematic plan view showing an embodiment of the present invention.
FIG. 2 is a sectional view taken along line II'-ffl in FIG. 1.

The configuration will be described below with reference to both figures.

Semiconductor substrate 1 as the drain of the FAMOS transistor
A pair of train regions 1 formed in the semiconductor substrate 11 are spirally introduced from the outside to the inside of the device, and a gate electrode 2 connected to the control gate is formed on the semiconductor substrate 11. Field oxidation is performed to separate each region. It is formed above the film 12 with an insulator y413 interposed therebetween.

A source FF4 region 3 is formed in the semiconductor substrate 11 as a source of the transistor so as to face the lower part of the gate electrode 2 at the tip of the drain region 1, but electrical connection between this region and the outside is made via the contact portion 4. It will be done. A FAMOS floating gate 5 is formed under the gate electrode 2 with an insulating film interposed therebetween at a portion where the source region 3 and the drain l[1 face each other. In addition, the drain region 1.70 is centered around the 70-ring gate 5. A diffusion region 6 is formed in the semiconductor substrate 11 so as to surround the gate electrode 2 and the source region 3, but the drain region 1 and the gate 1! It is not formed at the introduction part of pole 2. The structure up to the above is the same as that of the conventional device, but in this invention, the field oxide film 12 formed between the drain region 1 and the source region 3 inside the device is
An ultraviolet absorber 8 made of polysilicon, for example, is formed above the floating gate 5 via an insulating film 13 to surround the floating gate 5. Furthermore, a metal layer 1i 110 made of aluminum 3J#, for example, is formed on the top surface so as to cover the entire device (the upper part of the device is omitted in FIG. 1 for convenience); They are electrically connected to the ultraviolet absorber 8 via contact portions 7.9, respectively. A protective film 14 made of, for example, a glass coat is formed on the entire upper surface of the metal SIO to protect the device.

Since the operation of the 11 F ROM device constructed as described above is the same as that of the conventional device, the explanation will be omitted here. First, the pieces of the ultraviolet absorber 8 will be described below.

When the LIPRs ◯ to 1 β in this invention are irradiated with ultraviolet rays, a portion of the ultraviolet rays enters from the range of the introduction portion indicated by C° in the figure, as in the conventional example. The invading ultraviolet rays use the field oxide film 12 and the insulating film 13 as an intrusion route and try to reach the floating gate 5 of the FAMOS while repeatedly being diffusely reflected. However, since an ultraviolet absorber 8 is installed in the middle of this path, the invading ultraviolet rays A considerable amount of this will be absorbed. Therefore, the ultraviolet rays that originally penetrated into the floating gate 5 are further reduced, and the ultraviolet rays that reach the floating gate 5 are significantly attenuated.

In Example F, the ultraviolet absorber and the metal layer are connected through the contact part, but it is not necessary to connect them, and the installation of the ultraviolet absorber alone can have a considerable effect of attenuating ultraviolet rays. .

In addition, in the above practical example, the shape, number of times, and installation position of the ultraviolet absorber are specified, but the settings are not limited to these and can be set to bring about a better ultraviolet absorption effect depending on the internal structure of the device. It goes without saying that it can be done.

Further, in the above embodiment, polysilicon is used as the ultraviolet absorber, but other materials can have the same effect as long as they have an ultraviolet absorbing effect.

[Effects of the Invention] As explained above, in this invention, since an ultraviolet absorber is provided inside the hole-shielding structure, the amount of light that enters the ultraviolet rays that reach the memory storage section is greatly attenuated, and the amount of ultraviolet rays that have entered the storage area is greatly attenuated. On the other hand, there is an effect that the semiconductor memory device has a high memory retention ability.

[Brief explanation of drawings]

FIG. 1 is a schematic plan view showing an embodiment of the present invention, FIG. 2 is a sectional view taken along IT-II in FIG. 1, and FIG. 3 is a conventional LIPR.
A schematic plan view of the OM, and FIG. 4 is a sectional view taken along the line rV-■ in FIG. 3. In the figure, 1 is a drain region, 2 is a gate electrode, 3 is a source region, 5 is a floating gate, 6 is a diffusion region, 7 is a contact portion, 8 is an ultraviolet absorber, 9 is a contact portion, and 10 is a metal layer. . Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (8)

[Claims] (1) a semiconductor substrate, a storage section formed on the semiconductor substrate, a conductive section connected to the storage section and electrically connected to the outside, and an ultraviolet ray shielding section that includes a part of the conductive section and covers the storage section. a diffusion region formed in the semiconductor substrate surrounding the storage section except for the conduction section or below the conduction region; and a shielding section that connects the shield layer and the diffusion region and blocks ultraviolet rays. . A semiconductor memory device, comprising: an ultraviolet absorber that absorbs ultraviolet light and is provided in a space formed by the shielding layer, the shielding section, and the semiconductor substrate. (2) the ultraviolet absorber is connected to the shielding layer;
A semiconductor memory device according to claim 1. (3) The semiconductor memory device according to claim 1 or 2, wherein the ultraviolet absorber is polysilicon. (4) The semiconductor memory device according to claim 1, 2, or 3, wherein the storage section is a FAMOS. (5) The semiconductor memory device according to claim 4, wherein the conduction section includes a wiring section connected to a gate electrode constituting the FAMOS. (6) The semiconductor memory device according to claim 4 or 5, wherein the conductive portion includes a region connected to a source or drain region constituting the FAMOS. (7) the shielding layer and the shielding part are metal films;
A semiconductor memory device according to any one of claims 1 to 6. (8) The semiconductor memory device according to claim 7, wherein the metal film is aluminum.