JPS63306422A - Production of active matrix liquid crystal panel - Google Patents
Production of active matrix liquid crystal panelInfo
- Publication number
- JPS63306422A JPS63306422A JP62142267A JP14226787A JPS63306422A JP S63306422 A JPS63306422 A JP S63306422A JP 62142267 A JP62142267 A JP 62142267A JP 14226787 A JP14226787 A JP 14226787A JP S63306422 A JPS63306422 A JP S63306422A
- Authority
- JP
- Japan
- Prior art keywords
- external connection
- electrode
- connection terminal
- film
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000011159 matrix material Substances 0.000 title claims description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 11
- 239000007772 electrode material Substances 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 4
- 239000010408 film Substances 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 25
- 239000010410 layer Substances 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 14
- 239000000565 sealant Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 239000010409 thin film Substances 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 239000003566 sealing material Substances 0.000 abstract 4
- 239000003086 colorant Substances 0.000 abstract 1
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 229910004205 SiNX Inorganic materials 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 4
- 229910001120 nichrome Inorganic materials 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000007872 degassing Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明はアクティブマトリックス液晶パネルの製造方
法に係り、特に下基板上の薄膜トランジスタアレイの製
造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method of manufacturing an active matrix liquid crystal panel, and more particularly to a method of manufacturing a thin film transistor array on a lower substrate.
（従来の技術）
非晶質Ｓｉ（ａ−８ｉ）を用いた薄膜トランジスタ（ａ
−８ｉＴＦＴ）アレイを内蔵した従来のアクティブマト
リックス液晶パネルの製造方法を第３図および第４図を
用いて説明する。(Prior art) Thin film transistor (a-8i) using amorphous Si (a-8i)
A method of manufacturing a conventional active matrix liquid crystal panel incorporating a 8i TFT array will be described with reference to FIGS. 3 and 4.
第３図に示すようＫＳｔずガラス基板１上にＩ Ｔｏ
（Ｉｎｎ’ｓ ＋ Ｓｎｏｗ ）よシなる透明電極２（
セル用電極）をスパッタと加工によシ所定の形状に形成
する。次に、ニクロム（ＮｉＣｒ ） 、タングステン
ｔＷｌなどよシなる第１の金属層を基板１上に２００〜
ｘｏｏｏＡ程度被着し、これを所定の形状に形成するこ
とによりａ−８ｉＴＦＴアレイのゲート電極３全形成す
る、。この時、ゲート電極３としては、電極部３ａ、配
線部３ｂおよび外部接続端子部３Ｃを形成する。次いで
、ＮＩ（３とＳｉ Ｈ４ｋ主成分ガスとして用いたグロ
ー放電法によシ、シリコン窒化膜（ＳｉＮｘ ） ｅｏ
、２〜０．４μｍ８度の膜厚として基板１全面に堆積さ
せる。さらに、その上にＳｉ＆ガスを用いたグロー放電
法によシロ−８ｉ膜を０．０２〜０．２ｋｎ程度堆積さ
せる。そして、それらの所定部分以外、詳しくはａ−８
ｉＴＦＴの素子部４と、ドレイン電極配線部下領域部分
５、さらにはドレイン電極外部接続端子部下領域部分６
以外をホトリソとドライエツチング（ｃＦ４ ＋ Ｏｘ
ガスを用いたプラズマエツチング）で除去することによ
り、ａ−８ｉＴＦＴアレイの活性層（ａ−８ｉ膜）およ
びゲート絶縁［［（Ｓｉ Ｎｘ）を選択的に形成する。As shown in FIG. 3, I To
(Inn's + Snow) different transparent electrode 2 (
A cell electrode) is formed into a predetermined shape by sputtering and processing. Next, a first metal layer such as nichrome (NiCr), tungsten tWl, etc.
The entire gate electrode 3 of the a-8i TFT array is formed by depositing about 1 x00A and forming it into a predetermined shape. At this time, as the gate electrode 3, an electrode portion 3a, a wiring portion 3b, and an external connection terminal portion 3C are formed. Next, a silicon nitride film (SiNx) was deposited by a glow discharge method using NI (3) and SiH4k as main component gas
, 2 to 0.4 μm and a film thickness of 8° C. is deposited on the entire surface of the substrate 1. Further, a Shiro-8i film of about 0.02 to 0.2 kn is deposited thereon by a glow discharge method using Si and gas. For details other than those specified parts, see a-8.
The element part 4 of the iTFT, the region 5 below the drain electrode wiring, and the region 6 below the drain electrode external connection terminal.
Other than photolithography and dry etching (cF4 + Ox
The active layer (a-8i film) and gate insulator of the a-8i TFT array are selectively formed by removing the active layer (a-8i film) and the gate insulator [[(SiNx)].
次に、アルミニウム（ＡＺ）からなる第２の金属層を真
空蒸着法により０．５〜１．０μｍ程度被着し、これを
所定の形状に加工することでａ−８ｉＴＦＴアレイのド
レイン電画７およびンース′ｄ極８を各々形成する。こ
の時、ドレイン電極７としては、電極部７ａ、配線部７
ｂおよび外部接続端子部７Ｃを形成する。最後に、グロ
ー放電法によシ、シリコン窒化膜（Ｓｉ Ｎｘ ）また
はシリコン酸化膜（Ｓｉ Ｏｘ ）を所定の領域に堆積
させることで表面保護膜（図示せず）を形成する。以上
のプロセスによシセル用電極（透明’＠極２）とａ−８
ｉＴＦＴアレイが完成する。Next, a second metal layer made of aluminum (AZ) is deposited to a thickness of about 0.5 to 1.0 μm by vacuum evaporation, and is processed into a predetermined shape to form the drain electrode 7 of the a-8i TFT array. and 2'd poles 8 are formed, respectively. At this time, as the drain electrode 7, the electrode part 7a, the wiring part 7
b and an external connection terminal portion 7C are formed. Finally, a surface protective film (not shown) is formed by depositing a silicon nitride film (SiNx) or a silicon oxide film (SiOx) in a predetermined region by a glow discharge method. Through the above process, the electrode for the cell (transparent'@pole 2) and a-8
The iTFT array is completed.
このａ−８ｉＴＦＴアレイと透明電極２上にポリイミド
よシなる有機膜を形成し、ラビング処理することで図示
しない配向処理＠を形成する。その後、前記ゲート電極
３とドレイン電極７の外部接続端子部３ｃ、７ｃ上に配
置されてａ −Ｓｉ ＴＦＴアレイと透明電極２を囲む
ようにシール剤９を厚膜のスクリーン印刷法によ多形成
し、最後にセル間隔を均一に保持するための図示しない
スペーサ（球状のプラスチック）金配同処理膜上に散布
することで下基板が完成する。An organic film such as polyimide is formed on the a-8i TFT array and the transparent electrode 2, and a rubbing treatment is performed to form an alignment treatment (not shown). Thereafter, a sealant 9 is formed by a thick film screen printing method so as to be placed on the external connection terminal portions 3c and 7c of the gate electrode 3 and drain electrode 7 and surround the a-Si TFT array and the transparent electrode 2. Finally, a lower substrate is completed by scattering spacers (spherical plastics, not shown) on the gold distribution treatment film to maintain uniform cell spacing.
一方、上基板（対向電極側）は以下に示す如く形成され
る。すなわち、ガラス基板上に、ＩＴＯよりなる透明電
極をスパッタと加工によシ所定の形状に形成する。そし
て、透明電極上に、ポリイミドよシなる有機膜を形成し
、ラビング処理し、配向処理＠全形成することで上基板
が完成する。On the other hand, the upper substrate (counter electrode side) is formed as shown below. That is, a transparent electrode made of ITO is formed into a predetermined shape on a glass substrate by sputtering and processing. Then, an organic film such as polyimide is formed on the transparent electrode, subjected to a rubbing treatment, and then subjected to an alignment treatment @complete formation to complete the upper substrate.
そして、このようにして上基板と下基板が完成したら、
第４図に示すようにシール剤９を挾んで該シール剤９に
よυ上基板１０と下基板１１を貼シ合せ、シール剤９を
加熱硬化させ、さらにｙ −ル剤９の内側を真空脱気し
た後、該部分に液晶を注入し、注入口を封止することで
ａ −Ｓｉ ＴＦＴアレイを用いた液晶パネルが完成す
る。なお、第４図は、第３図のＡ−Ａ線断面図である。Once the upper and lower boards are completed in this way,
As shown in FIG. 4, the upper substrate 10 and the lower substrate 11 are bonded together with the sealant 9 between them, the sealant 9 is heated and cured, and the inside of the Y-ru agent 9 is vacuumed. After degassing, liquid crystal is injected into the area and the injection port is sealed to complete a liquid crystal panel using an a-Si TFT array. Note that FIG. 4 is a cross-sectional view taken along line A-A in FIG. 3.
（発明が解決しようとする問題点）
しかしながら、上記のような従来の製造方法では、下基
板１１において、ゲート電極の外部接続端子部３０部分
の膜厚と、ドレイン電極の外部接続端子部７０部分の１
模厚が、単層のみと３層の積層構造の違いによシ異なる
ため、シール剤９形成後の厚みが第４図にＢｌ、Ｂ２で
示すように異なシ、このため、ゲート電極の外部接続端
子部３ｃ付近とドレイン電極の外部接続端子部７Ｃ付近
でセル間隔（透明電極２と対向電極間隔）が異なり均一
なセルギャップを得にくいため、パネル駆動時色ムラが
発生するという問題点があった。(Problems to be Solved by the Invention) However, in the conventional manufacturing method as described above, in the lower substrate 11, the film thickness of the external connection terminal portion 30 of the gate electrode and the thickness of the external connection terminal portion 70 of the drain electrode are different. 1
Since the thickness differs depending on the difference between a single-layer structure and a three-layer multilayer structure, the thickness after forming the sealant 9 differs as shown by Bl and B2 in FIG. Since the cell spacing (the spacing between the transparent electrode 2 and the opposing electrode) is different near the connection terminal portion 3c and the drain electrode external connection terminal portion 7C, and it is difficult to obtain a uniform cell gap, there is a problem that color unevenness occurs when the panel is driven. there were.
この発明は、以上述べた下基板のゲート電磁外部接続端
子部部分とドレイン電極の外部接続端子部部分とで膜厚
が異なることでセル間隔が不均一になシ、色ムラが発生
するという問題点を解決し、表示品質の優れた液晶パネ
ルを得ることができるアクティブマトリックス液晶パネ
ルの製造方法を提供することを目的とする。This invention solves the above-mentioned problem of the difference in film thickness between the gate electromagnetic external connection terminal portion of the lower substrate and the drain electrode external connection terminal portion, resulting in uneven cell spacing and color unevenness. It is an object of the present invention to provide a method for manufacturing an active matrix liquid crystal panel that can solve the problems and obtain a liquid crystal panel with excellent display quality.
（問題点を解決するための手段）
この発明は、アクティブマトリックス液晶パネルの製造
方法において、シール剤が配置されるゲート電極外部接
続端子部部分およびドレイン逼砥外部接続端子部部分全
同−嗅構成で形成するようにしたものである。(Means for Solving the Problems) The present invention provides a method for manufacturing an active matrix liquid crystal panel in which a gate electrode external connection terminal portion where a sealing agent is placed and a drain and drain external connection terminal portion all have the same structure. It was designed to be formed by
（作 用）
上記のような方法によれば、ゲート電極外部接続端子部
部分およびドレイン電極外部接続端子部部分の膜厚が等
しくなプ、シール剤形成後の厚みも等しくなシ、セル間
隔が全体で均一になる。(Function) According to the method described above, the film thicknesses of the gate electrode external connection terminal portion and the drain electrode external connection terminal portion are equal, the thickness after forming the sealant is also equal, and the cell spacing is uniform throughout.
（実施例）
以下この発明の一実施例を図面を参照して説明する。第
１図はこの発明の一実施例によ）製造された液晶パネル
の断面図、第２図はその液晶パネルのうち下基板を取出
して示す平面図である。(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a liquid crystal panel manufactured according to an embodiment of the present invention, and FIG. 2 is a plan view showing a lower substrate of the liquid crystal panel.
その第２図に示すように、まずガラス基板２１上にＩ
Ｔ Ｏ（Ｉｎ５ｅ３＋ Ｓｎ Ｃｈ ）よシなる透明電
極２２（セル用電極）をスパッタと加工により所定の形
状に形成する。次に、ニクロム（ＮｉＣｒ） 、タング
ステン（ロ）などよりなる第１の金属層を基板２１上゛
に２００〜１０００λ程度被層し、これを所定の
形状に形成することによ、９ａ−８ｉＴＦＴアレイのゲ
ート電極２３を形成する。この時、ゲート電極２３とし
ては、電極部２３ａ、配線部２３ｂおよび外部接続端子
部２３０ｔ−形成する。また、この時、第１の金属層は
、ゲート電極領域以外の、ドレイン電極外部接続端子部
形成領域にも下地層２４として残すようにする。次いで
、ＮＨｓとＳｉ＆ｔ−主成分ガスとして用いたグロー放
電法によシ、シリコン窒化＠（ＳｉＮｘ ） ｔ Ｏ，
２〜０．４μｍ程度の・膜厚として基板２１全面に堆積
させる゛。さらに、その上ＫＳｉＨ４ガスを用いたグロ
ー放電法によｐａ−８ｉ膜を０．０２〜０．２μｍ程度
堆積させる。そして、それらの所定部分以外、詳しくは
ａ −Ｓｉ ＴＦＴの素子部２５と、ドレイン電極配線
部下領域部分２６、さらにはドレイン電極外部接続端子
部下領域部分２７以外をホトリソとドライエツチング″
（ｃＦ４ ＋ （ｈガスを用いたプラズマエツチング）
で除去することによ）、ａ −Ｓｉ ＴＦＴアレイの活
性層（ａ−８ｉ膜）およびゲート絶縁＠ （ＳｉＮｘ
）を選択的に形成するが、この時、この一実施例では、
シリコン窒化膜とａ−８ｉ膜を前記ゲート電極２３の外
部接続端子部２３ｃ上にも２層膜２８として残すようＫ
する。次に、アルミニウム（μ）からなる第２の金属層
を真空蒸着法によシ０．５〜１．０μｍ程度蒸着し、・
これを所定の形成に加工することでａ −Ｓｉ ＴＦＴ
アレイのドレイン電極２９およびソース電極３０を各々
形成する。この時、ドレイン電極２９としては、電極部
２９ａ、配線部２９ｂおよび外部接続端子部２９Ｃを形
成する。また、この時、第２の金属層を利用して、ゲー
ト電極２３の外部接続端子部２３ｃ上には上層金属層３
１に一形成する。この上層金属層３１は、ゲート電極２
３の外部接続端子部２３Ｃ上や配線部２３ｃ上で該ゲー
ト電極２３に電気的に接続されるようにする。最後に、
グロー放電法によシ、シリコン窒化膜（Ｓｉ Ｎｘ ）
または′シリコン酸化膜（Ｓｉ Ｏｘ ）を所定の領域
に堆積させることで表面保睡＠（図示せず）を形成する
。以上のプルセスによシセル用電極（透明電極２２）と
ａ −ＳｉＴＦＴアレイが完成する。As shown in FIG. 2, first, an I
A transparent electrode 22 (cell electrode) made of T O (In5e3+ Sn Ch ) is formed into a predetermined shape by sputtering and processing. Next, a first metal layer made of nichrome (NiCr), tungsten (b), etc. is coated on the substrate 21 with a thickness of about 200 to 1000λ, and this is formed into a predetermined shape to form a 9a-8i TFT array. A gate electrode 23 is formed. At this time, as the gate electrode 23, an electrode portion 23a, a wiring portion 23b, and an external connection terminal portion 230t are formed. Further, at this time, the first metal layer is left as the base layer 24 in the drain electrode external connection terminal forming region other than the gate electrode region. Next, silicon nitride@(SiNx) tO,
It is deposited over the entire surface of the substrate 21 to a film thickness of about 2 to 0.4 μm. Furthermore, a PA-8i film is deposited to a thickness of about 0.02 to 0.2 .mu.m by a glow discharge method using KSiH4 gas. Then, other than those predetermined portions, specifically, the element portion 25 of the a-Si TFT, the lower region 26 of the drain electrode wiring, and the lower region 27 of the drain electrode external connection terminal are photolithographically and dry etched.
(plasma etching using cF4 + (h gas)
), the active layer (a-8i film) of the a-Si TFT array and the gate insulation @ (SiNx
), but then, in this embodiment,
The silicon nitride film and the A-8I film are also left on the external connection terminal portion 23c of the gate electrode 23 as a two-layer film 28.
do. Next, a second metal layer made of aluminum (μ) is deposited to a thickness of about 0.5 to 1.0 μm using a vacuum evaporation method.
By processing this into a predetermined shape, a-Si TFT
A drain electrode 29 and a source electrode 30 of the array are formed, respectively. At this time, as the drain electrode 29, an electrode portion 29a, a wiring portion 29b, and an external connection terminal portion 29C are formed. Also, at this time, using the second metal layer, an upper metal layer 3 is formed on the external connection terminal portion 23c of the gate electrode 23.
1 to 1 form. This upper metal layer 31 is connected to the gate electrode 2
The gate electrode 23 is electrically connected to the gate electrode 23 on the external connection terminal portion 23C or the wiring portion 23c of No. 3. lastly,
By glow discharge method, silicon nitride film (SiNx)
Alternatively, a silicon oxide film (SiOx) is deposited in a predetermined area to form a surface retention layer (not shown). The above process completes the cell electrode (transparent electrode 22) and the a-Si TFT array.
このａ −Ｓｉ ＴＦＴアレイと透明電極２２上にポリ
イミドよシなる有機ＵＸｔ″形成し、ラビング処理する
ことで図示しない配向処理膜を形成する。その後、前記
ゲート電極２３とドレイン電極２９の外部接続端子部２
３ｃ、２９ｃ上に配置されてａ−８ｉＴＦＴアレイと透
明電極２２を囲むようにシール剤３２を厚膜のスクリー
ン印刷法によシ形成し、最後にセル間隔を均一に保持す
るための図示しないスペーサを配向処理膜上に散布する
ことで下基板が完、成する。An organic UXt'' such as polyimide is formed on the a-Si TFT array and the transparent electrode 22, and a rubbing treatment is performed to form an alignment film (not shown).After that, an external connection terminal between the gate electrode 23 and the drain electrode 29 is formed. Part 2
A sealant 32 is formed by a thick film screen printing method so as to surround the a-8i TFT array and the transparent electrode 22, and finally a spacer (not shown) is placed on the a-8i TFT array and the transparent electrode 29c. The lower substrate is completed by scattering it on the alignment treatment film.
一方、上基板（対向電極側）瓜ガラス基板上に透明電極
を所定の形状に形成した後、その透明電極上にポリイミ
ドよシな゛る有機膜を形成し、ラビング処理し、配向処
理＠を形成することで完成する。On the other hand, after forming a transparent electrode in a predetermined shape on the upper substrate (counter electrode side) glass substrate, an organic film such as polyimide is formed on the transparent electrode, rubbed, and aligned. It is completed by forming.
そして、このようＫして得られた上基板３３と前記下基
板３４を第１図に示すようにシール剤３２を挾んで該シ
ール剤３２で貼シ合せ、シール剤３２加熱硬化させ、さ
らにシール剤３２の内側を真空脱気した後、該部分に液
晶を注入し、注入口を封止することでこの発明の一実施
例のａ −Ｓｉ ＴＦＴアレイを用いた液晶パネルが完
成する。なお、第１図は第２図のＣ−Ｃ線断面図である
。Then, as shown in FIG. 1, the upper substrate 33 and the lower substrate 34 thus obtained are laminated together with a sealant 32 sandwiched therebetween, the sealant 32 is heated and cured, and further sealed. After the inside of the agent 32 is vacuum degassed, liquid crystal is injected into the area and the injection port is sealed, thereby completing a liquid crystal panel using an a-Si TFT array according to an embodiment of the present invention. Note that FIG. 1 is a sectional view taken along the line CC in FIG. 2.
（発明の効果）
以上詳細に説明したように、この発明の製造方法によれ
ば、シール剤が配置されるゲート電極外部接続端子部部
分およびドレイン電極外部接続端子部部分の膜構成を、
ゲート電極材料、ゲート絶縁膜、ａ−８ｉ半導体層およ
びソース・ドレイン電極材料によシ同−膜構成としたか
ら、両電極の外部接続端子部部分の膜厚が等しくなシ、
シール剤形成後の厚みも例えば第１図にＤｌ、Ｄ２で示
すように等しくなる。したがって、完成した液晶パネル
においてセル間隔が全体で均一となり、駆動時の色ムラ
を低減させ、表示品質の向上を図ることができる。(Effects of the Invention) As described in detail above, according to the manufacturing method of the present invention, the film structure of the gate electrode external connection terminal portion and the drain electrode external connection terminal portion where the sealant is arranged is
Since the gate electrode material, gate insulating film, A-8I semiconductor layer, and source/drain electrode materials have the same film structure, the film thickness of the external connection terminal portion of both electrodes is equal.
The thicknesses after the sealant is formed are also equal, as shown by Dl and D2 in FIG. 1, for example. Therefore, in the completed liquid crystal panel, the cell spacing becomes uniform throughout, reducing color unevenness during driving, and improving display quality.
第１図および第２図はこの発明のアクティブマトリック
ス液晶パネルの製造方法の一実施例を説明するための図
で、第１図は完成した液晶パネルの断面図、第２図は下
基板を取り出して示す平面図、第３図および第４図は従
来の製造方法を説明するための図で、第３図は下基板の
平面図、第４図は液晶パネルの断面図である。
２１・・・ガラス基板、２３・・・ゲート電極、２３ａ
・・・電極部、２３ｂ・・・配線部、２３ｃ・・・外部
接続端子部、２４・・・下地層、２５・・・素子部、２
６・・・ドレイン電極配線部下領域部分、２７・・・ド
レイン電極外部接続端子部下領域部分、２８・・・２層
膜、２９・・・ドレイン電極、２９ａ・・・電極部、２
９ｂ・・・配線部、２９ｃ・・・外部接続端子部、３０
・・・ソース電極、３１・・・上層金属層、３２・・・
シール剤、３４・・・下基板。
りづニニ・Figures 1 and 2 are diagrams for explaining one embodiment of the method for manufacturing an active matrix liquid crystal panel of the present invention. Figure 1 is a cross-sectional view of the completed liquid crystal panel, and Figure 2 is a cross-sectional view of the completed liquid crystal panel, and Figure 2 is a diagram with the lower substrate removed. FIGS. 3 and 4 are diagrams for explaining the conventional manufacturing method. FIG. 3 is a plan view of the lower substrate, and FIG. 4 is a sectional view of the liquid crystal panel. 21...Glass substrate, 23...Gate electrode, 23a
... Electrode part, 23b... Wiring part, 23c... External connection terminal part, 24... Base layer, 25... Element part, 2
6... Drain electrode wiring lower region portion, 27... Drain electrode external connection terminal lower region portion, 28... Two-layer film, 29... Drain electrode, 29a... Electrode portion, 2
9b... Wiring section, 29c... External connection terminal section, 30
... Source electrode, 31 ... Upper metal layer, 32 ...
Sealing agent, 34...lower substrate. Rizunini・
Claims (1)
た後、該トランジスタアレイとセル用電極を囲むシール
剤を前記トランジスタのドレイン電極およびゲート電極
の外部接続端子部上に配置して設けた下基板を有するア
クティブマトリックス液晶パネルの製造方法において、
前記薄膜トランジスタアレイの製造方法として、 （ａ）前記基板上に電極部、配線部および外部接続端子
部からなるゲート電極を形成し、同時に該ゲート電極材
料からなる下地層をドレイン電極の外部接続端子部形成
領域に形成する工程と、 （ｂ）その後、ゲート絶縁膜とａ−Ｓｉ半導体層を薄膜
トランジスタの素子部、ドレイン電極の配線部形成領域
および同電極の外部接続端子部形成領域に形成し、同時
に上記絶縁膜と半導体層からなる２層膜を前記ゲート電
極の外部接続端子部上に形成する工程と、 （ｃ）その後、電極部と配線部ならびに外部接続端子部
からなるドレイン電極と、ソース電極とを形成し、同時
にこれら電極材料からなる上層金属層を電気的に接続し
て前記ゲート電極の外部接続端子部上に形成する工程と
を有することを特徴とするアクティブマトリックス液晶
パネルの製造方法。[Claims] After forming a cell electrode and a thin film transistor array on a substrate, a sealant surrounding the transistor array and cell electrode is placed on external connection terminal portions of the drain electrode and gate electrode of the transistor. In a method of manufacturing an active matrix liquid crystal panel having a lower substrate provided with
The method for manufacturing the thin film transistor array includes: (a) forming a gate electrode consisting of an electrode part, a wiring part, and an external connection terminal part on the substrate, and at the same time applying a base layer made of the gate electrode material to the external connection terminal part of the drain electrode; (b) After that, a gate insulating film and an a-Si semiconductor layer are formed in the element part of the thin film transistor, the wiring part forming area of the drain electrode, and the external connection terminal part forming area of the same electrode, and at the same time, (c) forming a two-layer film consisting of the insulating film and the semiconductor layer on the external connection terminal portion of the gate electrode; and at the same time electrically connecting an upper metal layer made of these electrode materials and forming it on an external connection terminal portion of the gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62142267A JPH0766131B2 (en) | 1987-06-09 | 1987-06-09 | Active matrix liquid crystal panel manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62142267A JPH0766131B2 (en) | 1987-06-09 | 1987-06-09 | Active matrix liquid crystal panel manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63306422A true JPS63306422A (en) | 1988-12-14 |
| JPH0766131B2 JPH0766131B2 (en) | 1995-07-19 |
Family
ID=15311374
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62142267A Expired - Lifetime JPH0766131B2 (en) | 1987-06-09 | 1987-06-09 | Active matrix liquid crystal panel manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0766131B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0618920A (en) * | 1991-11-19 | 1994-01-28 | Matsushita Electric Ind Co Ltd | Liquid crystal display device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9246036B2 (en) * | 2012-08-20 | 2016-01-26 | Universal Display Corporation | Thin film deposition |
-
1987
- 1987-06-09 JP JP62142267A patent/JPH0766131B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0618920A (en) * | 1991-11-19 | 1994-01-28 | Matsushita Electric Ind Co Ltd | Liquid crystal display device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0766131B2 (en) | 1995-07-19 |
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