JPS63305633A - Monitor system for frame aligner - Google Patents

Abstract

PURPOSE:To monitor all cells in use in an clastic memory by inserting a test pattern to a signal written in the elastic memory while being shifted for each frame. CONSTITUTION:A pattern generator 3-1 generates a test pattern TP of (n+1)-bit period. The test pattern TP, a reception signal DIN and a signal DD1 shifting the received signal by one bit are selected by a (3-1) selector 4 and a test pattern taking a carry CRY 1 of the (n+1)-bit counter 2 as the time slot is inserted. An AND gate A1 takes the coincidence between the carry CRY 1 of the (n+1)-bit counter 2 at the write side and a write reset WR1 and applies a reset to the (n+1)-bit counter 9 at the readout side to send the content of the test pattern inserted at the write side and the position information to the readout side and a comparator 8 detects the presence or absence of the coincidence of the test pattern.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a monitoring method for a 7-frame aligner when converting a digital signal arriving at an arbitrary phase into a reference frame phase within a device in the field of digital communication. .

[Conventional technology]

Conventionally, a typical method for monitoring an elastic memory all-around fc7 frame aligner is a method in which a tolerance bit is added to a signal written to the elastic memory and a 74-retit check is performed on the read signal.

[Problem that the invention seeks to solve]

In the conventional method described above, if the write signal to the elastic memory is fixed, even if a failure occurs in any cell in the memory, a mismatch between the write signal and the read signal may not be detected.

[Means to solve the problem]

The present invention aims to solve the above-mentioned problems.
In a frame aligner that converts the phase of a dinotal signal into a phase within a dinotal signal device having surplus bits in a frame transmitted at an arbitrary frame phase, a test pattern is inserted into the surplus bits of the dinotal signal, and the dinotal signal is stored in an elastic memory. When writing all the data, shift the position of the surplus bits by n bits every frame and write.

The readout IJIII is characterized by shifting the focus by n in order to synchronize it with the test no.7 turn insertion position and checking the test pattern of the read signal.

[Effect]

In the present invention, all used cells in the eraser memory are checked by setting a monitoring bit in an arbitrary time slot of the write signal and sequentially setting the monitoring bit.

〔Example〕

The non-invention will be explained with reference to all the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The frame synchronization circuit 1 receives all the digital signals DIN having empty time slots in the frame transmitted from the opposite device at an arbitrary frame phase, and fully establishes frame synchronization of the received signals. When one frame consists of n pinto points, the (n+1) pinto counter 2 constitutes an (n-1-1) bit free-running counter synchronized with the reception clock, and the pattern generator 3-1 forms an (n+1) bit free-run counter synchronized with the reception clock.
) A test pattern TP i of bit period is generated. The test program TP, the received signal DIN, the signal DDI obtained by shifting this received signal by 1 bit, and 't(3-1)
Selector 4 selects time chart 5ELOU in Fig. 2.
Select like T, then (n+1) bit counter 2
Carry CRY l'? Insert all tests and turns into time slots. As a result, (3-1) when writing the output of the selector 4 to the elastic memory 7, the position of the test pattern time slot is shifted by 1 bit every frame and written to the elastic memory 7.

On the reading side, as well as on the writing side described above, (n+1)
Bit counter j! 9'fr: Configure and generate a test pattern similar to that on the writing side from the turn generator 3-2. The write side (n +
1) Match the carry CRY 1 of bit counter 2 with the write reset WRI.

By applying a reset to the (n+1) bit counter 9 on the reading side, the entire contents and position information of the test pattern inserted on the writing side are displayed. To detect. The comparator 8 outputs a second turn check signal PTN CHK indicating the presence or absence of a match. Finally, (2-1
) The signal Do1 read from the elastic memory 7 by the selector 1o and the 1-bit shift register 5-
Select the signal DDO1 shifted by 1 bit in Step 2 as shown in the time chart SEL OUT shown in Figure 3, extract all the inserted test patterns, and restore the original frame configuration.

〔Effect of the invention〕

As explained above, in the present invention, by shifting and inserting a test pattern for each frame into the signal to be written into the elastic memory, it is possible to monitor all the used cells in the elastic memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the present invention, and FIGS. 2 and 3 are time charts of each part of FIG. 1. 1: Frame synchronization circuit, 2.9: (n+1) focus counter, 3-1.3-2: Pattern generator, 4
: (3-1) Selector, 5-1.5-2: 1-bit shift V register, 6-1.6-2: RS flip front f, 7: x rustic memory, 8: Comparator, 10: (2- 1) Selector.゛・mi・″・・・′ ＼−２１− Engineering Figure 2 1st frame 2nd frame

Claims (1)

[Claims] 1. In a frame aligner that converts a digital signal having surplus bits in a frame transmitted at an arbitrary frame phase to a phase within the device, a test pattern is inserted into the surplus bits of the digital signal, and the When writing a digital signal, the position of the surplus bit is shifted by n bits every frame and written, and on the read side, the position of the surplus bit is shifted by n bits in order to synchronize with the test pattern insertion position, and the test pattern of the read signal is checked. A frame aligner monitoring method featuring: