JPS63305474A - Filter circuit - Google Patents

Abstract

PURPOSE:To optionally change the size of a filter by adding a function for changing the flow of data to a circuit system for executing filter processing based on a data flow system. CONSTITUTION:A filter circuit obtained by combining line filters corresponding to the number of filters with maximum size in series and the line filters are provided with multipliers 11-15, delay units 16-20 and address 31-35. In case of using the filter circuit for the filter with the maximum size, all the line circuits are connected in series. In case of using the filter circuit for a filter with a smaller size, only the line filter circuits corresponding to the filter size and used and combination of multipliers, delay units and adders corresponding to the filter size out of the filter circuits are used. Thus, the filter size can be switched.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a circuit configuration for realizing "real-time filter processing" in the field of digital image processing.

A digital image is a single screen, for example,
It is an image that is divided into ×n pixels and is a set of data that corresponds to each pixel. The pixel data may be a 1-bit black and white image, or it may be a color image with a larger number of bits.

FIG. 4 is a diagram illustrating the definition of pixels of an (nXn) image.

Numbers are given in the horizontal direction, 1.2,...,ql...n.

This is sometimes called the column number.

Numbers are given in the vertical direction, 1.2, . . . , pl...n.

This is sometimes called a line number.

The coordinates of the pixel in the pth row and qth column are written as (p%q).

There is also a notation that reverses the front and back, but here we use the line number,
Sort by column number.

The value of the digitized data of this pixel is d(p%q)
Write.

A filter is used to extract features of an image at any location on the screen, and is made by associating constant coefficients with small square areas.

As shown in FIG. 4, the filter consists of, for example, a small square area of m×m. What should be called a pixel can also be defined in this small area. Row numbers 1.2, ..., j, ...m in the horizontal direction
Row numbers 1.2, . . . , i, . . . m are given in the vertical direction.

The pixel position in the filter is denoted by (i,j).

Indicated by

The pixels of the filter do not have data, but rather constant coefficients αij. Therefore, although it is not an original pixel, it can be associated with a pixel on the image.

Depending on how the constant coefficients (αij) are selected, it is possible to know the presence or absence of local image features.

Filters can be placed anywhere on the screen.

To express the position of the filter on the screen, do the following:

When the filter is placed on the screen, the pixel number on the screen corresponding to the lower right corner of the filter is (p%Q).

In this case, the position of the filter is set to (1)%Q).

There are other ways to represent the filter position.

It can also be expressed by the number of the pixel at the center of the filter.

It can also be expressed by the number of the pixel at the top left of the filter.

Here, the position of the filter is expressed by the number (pxq) of the lower right pixel.

Now, applying the filter at the position (plq) on the screen means calculating the next value A(pxq).

That is, the filter is placed on the screen so that the lower right side matches the pixel (psq), the value d of each pixel is multiplied by the coefficient of the filter above that pixel, and the sum is calculated.

The bottom right of the filter is m rows and m columns. filter i row j
The column number coefficient αij. Since (pxq) corresponds to m rows and m columns, (p −m+ i , q −m+ j
) corresponds to the i-th row and j-th column of the filter. i row j
From column to m rows and m columns, in the row direction (m-i), in the column direction (
This is because it is only necessary to advance by m−j).

The i-th row and j-th column of the filter has a numerical coefficient of αij, and the pixels that overlap this are (p-m+i, q-m+j),
Although the data is d (p-m+i, q-m+j), it can be expressed as in equation (1).

A(psq) is called the filter calculation value for (p, q). Obtaining the filter calculation value is called filter processing.

0) Prior Art Conventionally, in order to perform filter processing, data d(plq) of all pixels is stored in an image memory, and this data is sequentially read out and multiplied by a numerical coefficient ■ij to obtain a filter calculation value A.
I was looking for (p, q).

In order to do this, it is necessary to write data for all pixels into the image memory.

However, the screen is updated one after another.

For example, it is updated at a high speed of 30 screens per second. This is called the video rate. For example, if n=512, then n x n=262144 pixels.

In this way, a large amount of pixel data is updated every 1×30 seconds. Writing data to image memory,
It changes every 1/3o second. After writing data (1)
It is necessary to perform calculations on the expressions, but such high-speed calculations are difficult. Data writing and filter processing cannot be performed in parallel each time the screen changes.

However, in the field of image processing, there is a strong demand to perform filter calculations in real time.

In order to perform real-time filter calculations, pixel data is first written into memory, then read out and calculated.
It is not possible to adopt such a time-consuming method.

The applicant has already developed a circuit that performs a 3×3 size filter operation.

The size of the filter may be 3×3 or 5×5, but the size is fixed and cannot be easily changed.

The real-time filter calculation circuit will be explained with reference to FIG.

The order in which pixels on the screen are scanned is as follows.

The first row is first scanned from left to right. Then, the second line is scanned from left to right. Furthermore, the third row is scanned from left to right. In this way, we reach the bottom row.

If the column numbers are the same but the row numbers are different, there is a difference of n in scanning order.

If the filter is an m×m filter, (n−m) pixels are scanned from the rightmost pixel of a certain row to the leftmost pixel of the next row included in the filter.

If m=3, then (n-3) pixels in the area without a filter are scanned from one row to the next row. Then, if the data is passed through a delay circuit that delays the data by the time required to scan for (n-3) pixels, the pixel data corresponding to the i-th row of the filter will be followed by (i+1
) This means that the pixel data corresponding to the row is obtained.

The circuit shown in FIG. 3 is a real-time filter processing circuit based on this idea.

This is processing for a 3×3 filter as shown in FIG. A numerical coefficient with two suffixes, such as α1, is complicated, so the numerical coefficients from the top left of the filter are F, F2, etc.
..., F9.

The circuit in Figure 3 includes a first line filter circuit that processes the first line F0 to F3 of the filter, and a second line F
It consists of a second row filter circuit that processes filters 4 to F6, and a third row filter circuit that processes filters 3rd row F7 to F9.

Input data is transmitted from the third row filter circuit. This passes through (n-3) clock delay circuits 102,
It is transmitted to the row filter circuit. This further becomes (n-3)
The signal is transmitted to the first row filter circuit via the clock delay circuit 101.

Multiplier of first row filter circuit, 103.104.10
5 is the input data and the numerical coefficients F0 and F in the first row of the filter.
2. Perform multiplication by F3. The same applies to the second and third row filter circuits.

The flow of output data is opposite to that of input data, from the first row filter circuit to the third row filter circuit.

During this time, adders 121 to 129 and 1 clock delay unit 1
12 to 120 are provided alternately.

For simplicity, the pixel data to be multiplied by the numerical coefficient at the top left of the first row of the filter is designated as Dl, and hereinafter as D2 and D3. Let the pixel data of the second row be D4, D5, and D6. The third line is D7 to D9. Corresponding to the previous equation (1), Dg=d(ps q) DI=d(p-2%
(1-2).

Input data D0 to D3 are given consecutively, (n 3)
After the clock, D4 to D6 are applied consecutively. Furthermore, after (n-3) clocks, D7 to D9 are applied successively.

Dl passes through the delay devices 102 and 101 and reaches the input line 131 of the first row filter circuit. The multiplier 103 calculates D×F1. This value is added to "0" by the adder 121. Become a DIF engineer.

At the next clock, DIF passes through the delay device 112 and is input to the adder 122. At the same time, D2 reaches the first row filter circuit input line 131. By the multiplier 104, D 2
X F 2 is calculated. This value and the DIF from earlier
and are added by an adder 122.

At the third clock, this sum passes through the delay device 113 and is input to the adder 123. At the same time, D3 appears on input line 131. Multiplier 105 calculates D3XF3. Adder 123 adds these three products.

At the fourth clock, the output of the adder 123 is sent to the delay device 11.
4 and is input to the adder 124. At the same time, the second row data D5 reaches the input line 132 of the second row filter circuit. Since there are (n-3) pixels between D4 and D5, this number is temporarily held by the (n-3) clock delay circuit 101. Multiplier 106 is D4
Calculate ×F4. This value and the previous addition results are added.

Thereafter, in the same manner, at the ninth clock, the sum DIF of all these +...+D9F9 is obtained.

Such circuits are useful circuits that enable real-time filtering.

However, this circuit has a problem in that the filter size is fixed. This example can only be used for a 3×3 filter. It is an inflexible circuit.

(1) Purpose: To provide a real-time filter calculation circuit that can accommodate changes in filter size, such as being able to use either a 3x3 filter or a 5x5 filter. This is the object of the present invention.

B) Structure The filter circuit of the present invention is a combination of row filter circuits in series, the number of which is equal to the maximum dimension of the filter. The row filter circuit has as many sets of multipliers, delays, and adders as there are filter maximum dimensions.

When used for filters of maximum size, all of these circuits are connected in series. The circuit becomes similar to the circuit shown in FIG.

When used with smaller size filters, only a number of row filter circuits equal to the filter size are used. Among the row filter circuits, only sets of multipliers, delays, and adders whose number is equal to the filter size are used.

In this way, the filter size can be changed.

FIG. 1 is a circuit diagram of one row filter circuit.

Connect these row filter circuits in series. FIG. 2 shows an example in which five row filter circuits f to f5 are connected in series.

An example in which the maximum filter size is 5×5 will be described below. This is an example of a filter calculation circuit that can be used in either 5×5 or 3×3.

The configuration of the row filter circuit will be explained with reference to FIG.

The input data string obtained by scanning the screen pixel by pixel is obtained by branching from the main input data line 2.

This row filter circuit gets its input data from input line 4.

The data on the main input data line 2 is transmitted via the delay shift register 1 to the main input data line 3 of the next row filter circuit.

The delay number l of the delay shift register is changed depending on the dimensions of the filter. For this reason, a shift stage number command is given to the delay shift register 1 from the computer.

The following circuit is substantially similar to the circuit of FIG.

Although there are many overlaps, I will explain them in detail.

Five multiplier, delay, and adder sets are provided in this row filter circuit so that it can also be applied to a 5×5 filter.

For input line 4, five multipliers 11.12,...,15
is provided. As will be explained later, this does not actually perform multiplication, but here it is called a multiplier, and is used here to mean a circuit that multiplies the input data and the filter value t.

The multiplier calculates the product of the data (D) and the filter coefficient (α). The filter coefficients have ilj as a suffix. The row filter circuit fi has i=i
A filter operation is performed on the data of j=1 to 5.

FIG. 6 shows a 5×5 size filter. row filter f
i has a numerical coefficient α1j (i=1 to 5) in the horizontal direction.

The row filter fi uses these and the data d(p-m+H.

The product of q-m+H is calculated and the results are added together.

That is, the entire i-th filter circuit fi is shown in FIG. 1, and the operation performed here is a row operation Bi== Σ
-m+j) (2) Only j=1. These are added as described later, and A=
ΣBi is obtained.

Therefore, to simplify the explanation, α1j=Gj1d (p
−5+i, q−5+j ) =Dj. In other words,
The calculation performed by this filter is B = DB Gt +H2G2 +D3G3 + D
Suppose that a G4 +Ds Gs (3).

The filter number i is simply omitted.

The outputs of multipliers 11-15 are sent to 1-bit delayers 16-2.
0 and enters adders 31-35.

A 1-bit delay device is an element that has the function of holding data for one clock. Specifically, it is a register. Therefore, instead of calling it a delay device, I will refer to it more specifically as a register.

Registers 21-26 are connected in series between adders 31-35.

The input data flow is from right to left. The output data flow is from left to right. It's in the opposite direction.

From register 21, via an adder and alternating columns of registers, to register 26 is main output data line 6.

Used when using a 5x5 filter.

In addition, a bypass data line 7 and a 0 data line 8 are provided. This is used when using a 3x3 filter.

The bypass data line 7 bypasses the output data line immediately before the register 21 and the output data line immediately after the register 23. There is a register 27 on the way.

0 data line 8 has a ground end. On the way, register 28
is connected to the output data line immediately after the register 23.

Registers 23.27.28 serve important functions. For convenience of explanation, they will be referred to as registers ASB and C.

Enable signal lines 41, 42, and 43 of the filter size switching circuit 5 are connected to these registers A, B, and C. Enable signals a%b, c are appropriately applied to the respective registers A, B, and C.

If enable a, b, c, these registers output data. If disabled i%■, τ, no data is output.

The filter size switching circuit 5 provides a register A%B1C hay enable or disable signal according to a command from the computer.

(4) Effect (5×5) The effect when used as a 5×5 size filter processing circuit will be explained. In this case, all five row filter circuits f-f5 connected in series are used. The result is as shown in FIG. 2(a).

The row filter circuit in FIG. 1 is one of f-f5. The input data is D as mentioned earlier.
1 to D5, and the filter value (α) is G to G5.

Assume that the output of the preceding row filter circuit is Y.

For the row filter f0 at the frontmost stage, it is sufficient to set it as Y-0.

The input data is a series of pixel data obtained by scanning the screen in rask order.

(1) Data D1 is applied to the input line 4 at the first clock. As already mentioned, Dl is d (p5+
i, q-5+1).

Multiplier 11 calculates the product of Dl and coefficient G, and provides register 16 with . Go means α11.

The output Y of the pre-stage filter is held in the register 21, and the adder 31 adds these to obtain (Y+DIG,).

(2) Data D2 is applied to the input line 4 at the second clock. This is d (p-5+ i, q-5+2
).

Multiplier 12 calculates the product of D2 and 02. This is held in register 17.

At the same time, the value (Y+D, G1) of the adder 31 is given to the register 22.

Adder 32 calculates the sum (Y+
01°1+D2°2) (3) Data D3 is given at the third clock.

The multiplier 13 calculates the product of D3 and 03, and the result is held in the register 18.

At the same time, the output of the adder 32 enters the register 23. The adder 33 calculates the sum of the outputs of the registers 18 and 23 to obtain Y10IG+D2G2+D3G3).

(4) The same applies to the fourth clock.

The output of the adder 34 is (Y1DIG+D2G2+D
3G3+D4G4).

(5) At the fifth clock, the output of the adder 35 is:
A value of B-(Y-1-DIGl+...+D5G5) is obtained.

(6) At the next clock, the value of B is held in the register 26.

(7) From now on, the problem is the (i+1)th row filter circuit. That is, it is input to the register 21 as the pre-stage value Y in FIG. 1 (at 7 clocks).

The same process is repeated for the next row filter.

However, the number of shift stages l of the delay shift register 1 must be set appropriately.

From the first pixel in the i-th row of pixels included in the filter,
There are n pixels up to the first one on the (i+1)th row.

In the row filter circuit of Figure 1, the output data line is
Registers 21, 22, to 26 are lined up.

Therefore, six clocks are required for the output data to pass through the row filter circuit.

At this time, the number of delay stages of the delay shift register is l = n
-6(4).

This depends on the number of registers. If there were no register 26, the number of serial registers would be 5, so l = n −
5 (5). Conversely, if one register is added next to register 26, 1=n-7.

Just to be sure, we will explain the beginning of the operation in the next stage row filter circuit. Since l = n -6, the first data D1 of the next row will appear on the input line 4 at the seventh clock. It is processed by the multiplier 11 and entered into the register 16.

As already explained, the value of the previous stage is entered into the register 21 at the seventh clock. In other words, data input to registers 16 and 21 is simultaneous.

Conversely, in order to synchronize the data input of register 16.21, the number of delay shift register stages l is set to l = n.
-k. k, where k is the number of registers (21 to 26 in this example) connected in series to one row filter among the output data lines.

Thus, the calculation power of the row filter is completed in k clocks. Since there are m row filters, all operations are performed in mk clocks. Although k may be m, it may also be (m+1) or more. In the conventional example shown in FIG. 3, m=3.

In reality, the multipliers 11 to 15 cannot perform the GXD operation within one clock. Currently, 80n
This is because there is no element that can perform multiplication processing in a cycle of sec to 160 nSec.

Therefore, the product data of CD is written into the memory element using GID as an address. Then, GXD is given to the memory as an address input to read out the product CD. This is called the table lookup method.

Static RAM, 1391sec to 150
Devices are available that can be read with cycle times of nscc.

Although G and D may be used as addresses, the value of G is determined for each multiplier. Therefore, G may be determined in advance, and the product CD may be written using only D as an address.

In this case, if the number coefficient G of the filter changes, the contents of the memory element must be rewritten.

Regarding the determination of the number of stages l of the delay shift register, the multiplication in the auxiliary multipliers 11 to 15 may not be able to be performed in one clock. With the method using the memory element described above, it can be done in one clock, but if other methods are used, it may become slower.

For this reason, the speed of data transmission from input to output may be slower than what was explained earlier.

However, this is not a problem.

Data conversion from input to output is performed for all operations GD. Therefore, the delay in data conversion from input to output is canceled. This does not affect the determination of the number of stages l of the delay shift register.

In other words, l can be determined without depending on the delay in the flow of data from input to output. This makes the circuit of the invention possible.

(b) For work (3X3) Next, a 3×3 filter calculation will be explained.

Row filter circuits f□, f2 as shown in FIG. 2(b)
Don't use. Row filter circuits f3, f4, f5 are used. Moreover, of the five multipliers f3, f4, and f5, only the latter three are used.

Then, 3×3 filter processing can be performed.

In the case of the filter shown in FIG. 6, a 3×3 portion from α to α55 is used.

Therefore, for row filter circuit f3, register A,
B is disabled and C is enabled. Then,
Data 0 is applied from the 0 data line 8 to the adder 33. This means that a=0, b=o, and c=1.

For row filter circuits f4 and f5, register A1C
is disabled and B is enabled.

a=0, b=1, c=0. The previous value Y is applied to the adder 33 through the bypass data line 7.

Row filter circuits f3-f5 will include three multipliers.

The number of registers on the output data line included in one row filter circuit is four. The number of delay stages of the delay shift register is 4 (j = n - 4 (6)).

(g) Effects The present invention adds a function to change the flow of data to a circuit system that performs filter processing using a data flow method. This allows the size of the filter to be changed freely. It becomes a highly versatile circuit.

The explanation so far has been about switching between 5×5 and 3×3 filter sizes. However, by increasing or decreasing the number of circuits, it is also possible to switch between 7×7 and 9×9.

The present invention can be applied to image processing devices in all fields.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a row filter circuit forming a part of the filter circuit of the present invention. FIG. 2 is a schematic diagram showing connections between row filter circuits and input/output data flows. If (a) is a 5×5 filter, (b)
is the case of a 3×3 filter. FIG. 3 is a filter circuit diagram for a 3×3 filter according to a conventional example. FIG. 4 is an explanatory diagram of the correspondence between the digital screen and the filter. FIG. 5 is a number coefficient correspondence diagram of the 3×3 filter used in the circuit of FIG. 3. FIG. 6 is an explanatory matrix diagram of a 5×5 filter or 3×3 filter used in the present invention.

Claims (2)

[Claims] (1) At any location of an image divided into n×n pixels, a filter consisting of m×m numerical coefficients is made to correspond, and the sum of the products of the filter’s numerical coefficients and the pixel data at the corresponding position is calculated. Row filter circuits f_1, f_2, which are circuits that perform the desired filter processing and whose number is equal to the maximum size of the filter.
... are connected in series, and these are connected by an input data line and an output data line that transmit data in opposite directions, and a delay shift register 1 is provided on the input data line, and the input data of each row filter circuit is inputted with l clock pulses. A delay is given and the data is sent to the next row filter circuit, and each row filter circuit f
i is a number equal to the maximum size of the filter and includes the input data D_1, D_2, ... and the coefficient G_ of the filter in that row.
1, G_2,...; a number of adders equal to the maximum size of the filters installed on the output data line to sequentially add the outputs of the multipliers; a register provided between the adders and outside the adder, and one or more adders on the output data line;
a bypass data line 7 for bypassing the register;
A 0 data line 8 that gives data 0 to the same position as the bypass data line 7, a register B provided on the bypass data line 7, a register C provided on the 0 data line 8, and the last register among the bypassed registers. A and register B,
1. A filter circuit comprising a filter size switching circuit that selectively applies an enable signal to C and C. (2) A patent characterized in that the multiplier is configured by a circuit using a table lookup method using static RAM, and the number coefficients of the filter can be changed by rewriting the contents of the RAM under control from a computer. A filter circuit according to claim (1).