JPH03148780A - Picture processor - Google Patents

Abstract

PURPOSE:To make the scale of a circuit smaller and to reduce cost by making each number of memory stages of a FIFO to be the stages number subtracting the number of rows of a space filter from the number of horizontal picture elements, and specifying the connection of the FIFO memory and a filter calcula tion part. CONSTITUTION:A filter calculation part is equipped with nine coefficient registers 6-14, nine multipliers 15, eight D flip-flops (D-FF) 17, a D-FF 18 for setting initial value, and nine adders 16. And, FIFO memories 3,4,5, when the number of horizontal picture elements of an increment data is H, consists of (H-M)=(H-3) steps which is less than H for the number of rows M=3 of the space filter. In such a case, the output of the FIFO memory 3 is inputted to three of the multipliers 15 of the row closest to an output terminal 2, the output of the FIFO memory 4 is inputted to the three multipliers 15 of the next row, and the output of the final step FIFO 5 is inputted to three of the multipliers 15 of the row which is furthest away from an output terminal 2. Thus, the circuit constitution can be simplified, and the cost can be reduced at the same time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device that performs spatial filter calculation processing on image data.

[Prior Art 1] Conventionally, as a spatial filter used for contour enhancement of image data captured by a CCD camera or the like, for example, the filter shown in FIG. 4 is known.

Figure 4 shows an image processing device that configures a spatial filter with 3 rows and 3 columns (generally M rows and M columns), and image data input from input terminal 1 has a horizontal pixel count of H. Then, first, the number of vertically connected memory stages (H+3) is FIFO.
Memory (Fitst InFirst O++t Me
mory)3. 4. 5 is input to the first FIFO memory. Following the FIFO memories 3, 4, and 5, a filter calculation section 100 is provided.

As shown in FIG.
0°, Cot, . . . nine coefficient setters 6 to 14 that set eC2□, and nine multipliers 15 that calculate the product of the input image data and the coefficients of the coefficient setters 6 to 14. provided. Furthermore, each output of the multiplier 15 is connected to nine DFF1
7 and an adder 16, and finally the sum of products of nine image data and coefficients is obtained from the output terminal 2 as a filter calculation value.

Specifically, the distribution of image data with respect to the coefficient position of the spatial filter shown in FIG. 5 at the time of inputting arbitrary image data results in a state as shown in FIG. 6. - That is, the image data (reference data) located in the hatched area in the center of the spatial filter is the target of filter calculation, and the eight images that exist adjacent to the image data located in the center are The data is used in a filter operation, and a filter operation value for the central image data is determined as the sum of products of each image data and the corresponding coefficient.

As shown in FIG. 7, such a spatial filter calculation is performed by applying a spatial filter of 3 rows and 3 columns with the coefficients shown in FIG. This is equivalent to sequentially shifting each data and finding the filter calculation value of the image data located at the center of the filter.

[Problems to be Solved by the Invention] However, in a conventional image processing device that configures such a spatial filter, the number of horizontal pixels H of image data as a FIFO memory is equal to the number M of rows of the spatial filter in M rows and M columns.
For example, M = 3 memory stages are required, and F
There was a problem that the circuit configuration of the IFO memory became complicated.

In other words, the horizontal and vertical size of image data handled in image processing is 2.
For example, in the vertical direction 2
The image has 048 pixels and 2048 pixels in the horizontal direction. On the other hand, FIFOs with a variable number of memory stages, such as 2048 stages, are commercially available, but since the FIFO memory must have 2051 stages, which is 3 stages added to the horizontal pixel number H, it is necessary to use a 2048 stage FIFO memory. It's also -3 steps short. Therefore, three stages of D-flip-flops are
Since it is necessary to add a separate circuit after the O memory, there is a problem in that the circuit scale increases accordingly.

The present invention has been made in view of such conventional problems, and an object of the present invention is to provide an image processing device that can configure a spatial filter for image processing using a FIFO memory with a number of stages shorter than the number of pixels in the horizontal direction. shall be.

[Means for Solving the Problems] First, the present invention sequentially reads out image data of H horizontal pixels stored in a memory and inputs it to FIFO memories vertically connected in M stages. The parallel outputs of each stage are output row by row to a filter calculation section that constitutes a spatial filter of M rows and M columns, and the filter calculation section outputs the coefficients set at each filter position of M rows and M columns and the coefficient position. The present invention is directed to an image processing apparatus that sequentially calculates a filter calculation value of image data located at the center of the filter as the sum of products with input image data.

In the present invention, for such an image processing device, the FI
The number of memory stages of the FO memory is defined as the number of stages (HM - M) obtained by subtracting the number of rows of the spatial filter from the number of horizontal pixels H, and the output of the first stage FI FO memory is connected to the output terminal of the filter calculation section. The output of the M-stage FIFO memory is connected to the calculation unit in the filter calculation unit in the filter calculation unit so that the output of the final M-th FIFO memory is connected to the calculation unit in the nearest row, and the output terminal of the final M-th FIFO memory is connected to the calculation unit furthest from the output terminal of the filter calculation unit. The input is connected to the section.

[Function] According to the image processing device of the present invention having such a configuration, conventionally, an F I FO memory of (l(+M) stages), which is the number of horizontal pixels H plus the number of rows of the spatial filter M, is required. However, in the present invention, it is possible to create a FIFO memory with (HM-M) stages, which is the number of horizontal pixels H minus the number of spatial filter rows M. Therefore, compared to the conventional method, the number of memory stages is one FIFO A commercially available FIFO memory that can reduce the number of stages by (2
In the present invention, even if the FIFO memory is 0.048, the number of horizontal pixels H = 2048, M = 3 stages may be reduced, for example, so a commercially available FIFO memory can be used as is, and the circuit configuration can be simplified. At the same time, costs can be reduced.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of the present invention, taking as an example a case where a spatial filter is arranged in three rows and three columns.

In FIG. 1, 3.4.5 is a FIFO memory vertically connected to input terminal 1, and FIFO memory 3.4.
5 is composed of (HM-M)=(H-3) stages, where the number of horizontal pixels of the additional data is H, the number of rows of the spatial filter is M=3.

Following the FIFO memory 3.4.5 is the filter calculation unit 1.
00 is provided and the coefficient C. Nine coefficient registers 6 to 14 that set O=C22, nine multipliers 15 that calculate the product of image data and the coefficient, and eight D flip-flops that calculate the nine sums of the products of the multipliers 15 ( (hereinafter referred to as rD-FFJ) 17, a D-FF 18 for initial value setting, and nine adders 16.

Image data input from input terminal 1 is sent to FIFO memories 3, 4 and 5 in this order.

The difference from the conventional configuration shown in FIG. 4 is that the output of the FIFO memory 3 is input to the three multipliers 13 in the row closest to the output terminal 2, and the output of the FIFO memory 4 is input to the three multipliers 13 in the next row.
5, and the output of the final stage FIFO 5 is input to the three multipliers 15 in the row farthest from the output terminal 2.

Therefore, from the output terminal 2 of the filter calculation unit 100, the number of coefficients C of the coefficient register 6.7.8 is output. ae C. 1w
The product of CO2 and the output of the FIFO memory 5 and the coefficient register 9. Coefficients Cto, C1t, C of io, ii
, 2 and the output of the FIFO memory 14 and the coefficient C2°, C2°, C2 of the coefficient register 12.13.14
The sum of the product of ° and the output of the FIFO memory 3 is output.

Similarly, in the case of a general spatial filter with M rows and M columns,
FIFO memories having a number of memory stages (HM-M) smaller by the number of filter rows M than the number of horizontal pixels H are vertically connected in M stages, and input signals are passed through the FIFOs in the order of FIFO-1 to M-1. and,
The output of the first FIFO-o is input to the multiplier on the row closest to output terminal 2, the output of the second FIFO-l is input to the multiplier on the next row, and the output of the second FIFO-1 is input to the multiplier on the next row. The connection structure is such that the output of No. 2 is further sequentially input to the multiplier on the next row.

And the coefficient Co, o ~ C0, 61-1 is the last FI
Multiply by the output of FO-(M-l) and get the coefficient Ct-o”C+
.

The coefficient CM-l of the last row is multiplied by the output of the second-to-last FIFO-(N-2), and in the same manner, the coefficient CM-l of the last row is
0- CM-l, M-l is the first FIFO=
is multiplied by the output of 0, and finally M as the result of all additions
The sum of products of XM terms can be calculated.

With this configuration of the present invention, the number of FIFO memory stages required for the spatial filter is (HM-M), which is compared to the conventional (H-M).
+M) by 2M stages.

The following describes the function of the spatial filter realized by the present invention.

At a certain clock time (N), the output terminal 2 in FIG.
The signal OUT (N) output to the input signal IN (N
) and nine coefficients Call to C22. first,
FIFO memory 3. 4. Output FO at time N of 5
(N), Fl (N), F2 (N), since the length of FIFO memory 3.4.5 is (H-3), FO(N) = IN (N-H+3) River (1)
Fl (N)=IN (N-2xH+6) −・−
(2) F2 (N)=IN (N-3XH+9)
-...(3). Also, from output terminal 2 to D-FF1
Every time you go back 7, you go back one clock, so the output signal OUT (N) is OUT (N) ・F2 (N-lf) x COO+F2 (N-7)
x c Old 10F2 (Toro) xCO2+H (N-5
) x Clo ten Fl (N-4) XC11+FI (
N-3) XC12+FO (N-2)XC20+FO
(N-1) XC21+FO(N) XC22・
... (4) becomes.

Substituting the above equations (1), (2), and (3) into this equation (4), oUT (N) = IN (N-3x N+1) x
COO+IN (To3 x N+2) x cllll+
IN (N-3X N+3) X C12+IN (N
-2X 111) X CIO ten IN (N-2XH+2
)XC11+IN (N-2X old 4)XCO2+Summer N (
N-1+1) x e? o+IN (N-11+2)
x C21+IN (NH+3) X C22...
(5) becomes.

Therefore, OUT (N) is the sum of products of nine values of 3 x 3 with the input image at time (N-2XH+2) as the filter center and the coefficient Call-C22, and a spatial filter is constructed. It is proven that

That is, the coefficient C of the spatial filter by the filter calculation unit 100 in FIG. The distribution of o-czz is as shown in Figure 2,
The distribution of image data for each filter position at a certain input time point (N) is as shown in FIG. 3 based on the above equation (5), and the image data (2H-2) located at the center of the filter is shown by the diagonal line. This means that the filter calculation value of is obtained from the above equation (5). Note that the input time point (N) is omitted in FIG.

On the other hand, regarding the conventional device shown in FIG. 4, the FIFO memory 3. 4. If the same calculation is performed with the number of memory stages of 5 as (N+3) stages, the output OUT-(N) will be 0υT (N) = lN (N-3X H-ll) C
OD+IN (N-3x 10) COI+IN (3xH-9) CO2+IN (N-2x 11) CIO
+IN(N-lt xH-lll) CII+IN(N-
j! xH-9) C12+IN(N-F11) C20
+IN (N-F111) C21+IN (N-H-
9) C22...-(6) This is a sum of products with the input image at time (N-2XH-10) as the center of the filter.

Of course, the same proof can be applied to the generally expressed spatial filter with M rows and M columns.

To explain the operation shown in FIG. 1, image data input from the input terminal 1 is input to the FIFO memory 3.

The number of stages of the FIFO memory 3 is (N-3) stages, which is three stages less than the number of horizontal pixels H, so the FIFO memory 3 is processed after (N-3) clocks.
Image data is output from FO memory 3.

The output of FIFO memory 3 is input to FIFO memory 4. FIFO memory 4 also has (N-3) stages, so
N-3) Image data is output from the FIFO memory 4 after a clock. The output of FIFO memory 4 is input to FIFO memory 5. The FIFO memory 5 also has (N-3) stages, so after another (N-3) clock, the FIFO memory 5
Image data is output from.

Therefore, FO (N), Fl (N), and F2 (N) shown in equations (1), (2), and (3) are
FO memory 3. 4. The output will be 5.

The D-FF 18 is a register into which an initial value is input, and normally O is input therein. Therefore, the output F of FIFO memory 5
The product of 2(N) and the coefficient Coo of coefficient register 6 is D-FF.
Enter 17.

'In the next clock, F 2 (N) X Coo and F2
The sum of (N+1)XCOI enters the next D-FF 17, and the sum of F2 (N+2)XCO2 is added at the next clock. At this stage, F2(N) XCllO+F2(N+1) XCO
l+F2(N+2) XCO2 is 3 from the left on the first row
It is included in the second D-FF17. Furthermore, three clocks after the next clock, the product of the output F1 of the FIFO memory 4, the coefficient ctn, and the c ratio C12 is calculated, and Fl(N+3) XCIO+F1(N+4) XC11
+Fl(N+5)

After 3 more clocks, FO(N+6) XC208FO(N+7) XC2
1+FO(N+8) XC22 is added. Therefore, the output OUT (N) is expressed by the above-mentioned equations (4) and (5) by replacing (N+8) with N in the above equations.

Therefore, a 3×3 spatial filter can be realized with this configuration. Of course, the same applies to the case where M FIFO memories of (HM) stages are connected in series and an M×M spatial filter is configured by M×M multipliers, coefficient registers, adders, and D-flip-flops.

[Effects of the Invention] As described above, according to the present invention, a spatial filter can be configured using FIFO memories with fewer stages than the number of horizontal pixels, so the circuit scale can be reduced compared to the conventional one.

In particular, when the size of the spatial filter is M rows and M columns, it can be configured with M stages less FIFO memory than the number of horizontal pixels, so the larger the size of the spatial filter, the more effective it is in terms of size and cost by reducing the circuit scale. growing.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention; Fig. 2 is an explanatory diagram of the coefficient distribution of the spatial filter of the present invention; Fig. 3 is an explanatory diagram of the distribution of image data of the spatial filter of the present invention: Figure 4 is a block diagram of the conventional device; Figure 5 is an explanatory diagram of the spatial filter coefficients of the conventional device; Figure 6
The figure is an explanatory diagram of the distribution of image data by a spatial filter in a conventional device. FIG. 7 is an explanatory diagram schematically showing arithmetic processing of memory image data by a spatial filter. 1 Two-power terminal 2: Output terminal 3.4.5: FIFO memory 6-14: Coefficient register

Claims (1)

[Claims] The image data with H horizontal pixels stored in the memory is sequentially read out and input into M stages of vertically connected FIFO memories, and the parallel outputs of each stage of the M stages of FIFO memories are passed through a spatial filter with M rows and M columns. An image located at the center of the filter as the sum of the products of the coefficients input row by row to the constituent filter calculation section and set at each filter position in M rows and M columns in the filter calculation section and the pixel data input to the coefficient position. In an image processing device that sequentially calculates filter calculation values of data, the FI
The number of memory stages of each FO is set as the number of stages (HM - M) obtained by subtracting the number of rows M of the spatial filter from the number H of horizontal pixels, and the output of the first stage FIFO memory is set to the row closest to the output terminal of the filter calculation section. M such that the output of the final M-th FIFO memory is input connected to the calculation unit in the row furthest from the output terminal of the filter calculation unit.
An image processing apparatus characterized in that each output of each stage of FIFO memory is connected as an input to the filter calculation section.