JPS63304470A - Digital recorder - Google Patents

Digital recorder

Info

Publication number
JPS63304470A
JPS63304470A JP14029487A JP14029487A JPS63304470A JP S63304470 A JPS63304470 A JP S63304470A JP 14029487 A JP14029487 A JP 14029487A JP 14029487 A JP14029487 A JP 14029487A JP S63304470 A JPS63304470 A JP S63304470A
Authority
JP
Japan
Prior art keywords
signal
converter
switch
converted
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14029487A
Other languages
Japanese (ja)
Inventor
Tatsuro Shigesato
達郎 重里
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP14029487A priority Critical patent/JPS63304470A/en
Publication of JPS63304470A publication Critical patent/JPS63304470A/en
Pending legal-status Critical Current

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  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE:To reduce the number of A/D converters and to decrease a circuit scale by sharing the A/D converter for inputting and converting a signal and the A/D converter for the time of a signal reproduction. CONSTITUTION:At the time of recording, a signal to be inputted from an input signal 1 is inputted to the A/D converter 3 through a switch 2 and the converted input signal is converted into the signal suitable for being recorded by a signal processing part 5 through the switch 4. Then, after it is error-corrected and coded by an error correcting coding part 6, it is outputted to a recording signal 7. Next, at the time of reproduction, the reproducing signal 8 obtained from a recording medium is inputted to the A/D converter 3 through the switch 2 and the converted reproducing signal is inputted to a signal detecting part 10 through the switch 4. The detecting part 10 detects the signal by using digital multilevel information obtained by the A/D converter 3. The detected signal is error-corrected by an error correcting part 11 and converted into the former state of the signal by a signal processing part 12 and outputted to the output signal 13.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、画像や音声をディジタル化して記録するディ
ジタル記録装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital recording device that digitizes and records images and sounds.

従来の技術 画像信号をディジタル化して記録するディジタルVTR
や音声信号をディジタル化して記録するDAT等におい
て、記録されたディジタル信号を再生するときにその再
生信号をディジタル化して信号検出する方式が提案され
ている。これは従来のように再生信号を1サンプル毎に
1つのスレッシュホルドで1か0かを決定するよりも、
複数のサンプルをディジタル化してそれら複数のサンプ
ルの多値情報を用いて検出する方が誤り率が良いからで
ある。この様な方式としてビタビ復号が知られている。
Conventional technology Digital VTR that digitizes and records image signals
2. Description of the Related Art A method has been proposed in which, when reproducing a recorded digital signal, the reproduced signal is digitized and the signal is detected in a DAT that digitizes and records an audio signal. This is better than deciding whether the reproduced signal is 1 or 0 using one threshold for each sample as in the past.
This is because the error rate is better if a plurality of samples are digitized and detection is performed using multi-level information of the plurality of samples. Viterbi decoding is known as such a method.

また信号検出後の誤り訂正や誤り検出においてもこの様
な方式を用いることによって誤り訂正能力や誤り検出能
力を大幅に改善することが可能である。
Further, by using such a method in error correction and error detection after signal detection, it is possible to significantly improve error correction ability and error detection ability.

発明が解決しようとする問題点 しかしながら上記のような構成では、入力信号用のアナ
ログ・ディジタル(以下A/D )変換器と再生信号用
のA/D変換器の2つの変換器が必要になり、回路規模
の増大を招いてしまうという欠点を有していた。
Problems to be Solved by the Invention However, the above configuration requires two converters: an analog-to-digital (hereinafter referred to as A/D) converter for the input signal and an A/D converter for the reproduced signal. However, this method has the drawback of increasing the circuit scale.

本発明は上記のような欠点を改善するディジタル記録装
置を提供することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a digital recording device that improves the above-mentioned drawbacks.

問題点を解決するための手段 本発明は、画像信号や音声信号をディジタル化して記録
するディジタル記録装置において、入力信号を標本化し
てディジタル化するアナログ・ディジタル変換器と、記
録された信号を再生時に標本化してディジタル化して信
号検出または誤9訂正や誤9検出するときに用いるアナ
ログ拳ディジタル変換器とを共用することを特徴とする
ディジタル記録装置である。
Means for Solving the Problems The present invention provides a digital recording device that digitizes and records image signals and audio signals. This digital recording device is characterized in that it also shares an analog-to-digital converter used when sampling and digitizing signal detection, false 9 correction, and false 9 detection.

作  用 本発明は上記した構成によp1信号入力変換器用のA/
D変換器と信号再生時の’AD変換器とを共有すること
により、AD変換器の数を減らすことができ、回路規模
を小さくできる。
Operation The present invention has the above-described configuration to provide an A/
By sharing the D converter and the AD converter during signal reproduction, the number of AD converters can be reduced and the circuit scale can be reduced.

実施例 図は本発明の実施例のブロック図である。図の1は入力
信号、2はスイッチ、3はA/D変換器、4はスイッチ
、6は信号処理部、6は誤り訂正符号化部、7は記録信
号、8は再生信号、9は記録・再生制御部、1oは信号
検出部、11は誤り訂正部、12は信号処理部、13は
出力信号である。
The embodiment diagram is a block diagram of an embodiment of the present invention. In the figure, 1 is an input signal, 2 is a switch, 3 is an A/D converter, 4 is a switch, 6 is a signal processing section, 6 is an error correction encoding section, 7 is a recording signal, 8 is a reproduction signal, 9 is a recording - Reproduction control section, 1o is a signal detection section, 11 is an error correction section, 12 is a signal processing section, and 13 is an output signal.

ここで本実施例の動作について説明する。まず記録時に
は入力信号1から入力される信号は、スイッチ2を介し
てA/D変換器3へ入力される。
Here, the operation of this embodiment will be explained. First, during recording, a signal inputted from input signal 1 is inputted to A/D converter 3 via switch 2 .

ここでA/D変換された入力信号はスイッチ4を介して
信号処理部5で記録に適した信号に変換される。そして
誤り訂正符号化部6で誤り訂正符号化されて記録信号7
へ出力される。次に再生時には記録媒体から得られた再
生信号は、再生信号8よシ入力されてスイッチ2を介し
てA/D変換器3へ出力される。A/D変換器3でディ
ジタル情報に変換された再生信号はスイッチ4を介して
信号検出部1oへ入力される。信号検出部1oではA/
D変換器3で得られたディジタルの多値情報を用いて信
号検出する。ここで検出された情報は、誤り訂正部11
で誤り訂正され、信号処理部12で元の信号の状態に変
換されて出力信号13へ出力される。またスイッチ2お
よびスイッチ4の切り替えは記録・再生制御部9によっ
て制御される。
Here, the A/D converted input signal is converted into a signal suitable for recording by a signal processing section 5 via a switch 4. The error correction coding unit 6 then encodes the recording signal 7.
Output to. Next, during reproduction, the reproduced signal obtained from the recording medium is input as the reproduced signal 8 and outputted to the A/D converter 3 via the switch 2. The reproduced signal converted into digital information by the A/D converter 3 is input to the signal detection section 1o via the switch 4. In the signal detection section 1o, A/
Signal detection is performed using digital multilevel information obtained by the D converter 3. The information detected here is stored in the error correction unit 11
The error is corrected in the signal processing section 12, and the signal is converted into the original signal state and outputted as an output signal 13. Further, switching of the switch 2 and the switch 4 is controlled by a recording/reproduction control section 9.

一般に記録時には再生信号を検出する回路は必要でなく
、逆に再生時には入力信号をA/D変換する必要がない
。このため上記のように記録時か再生時かで切9替えて
1つのA/D変換器を共用することにより、回路規模を
小さくすることができる。
Generally, a circuit for detecting a reproduced signal is not required during recording, and conversely, there is no need to A/D convert the input signal during reproduction. Therefore, the circuit scale can be reduced by switching between recording and reproduction and sharing one A/D converter as described above.

また再生時に上記のA/D変換器から得られる再生信号
の多値情報を利用することによって誤り検出能力や誤り
訂正能力を大幅に改善することも可能である。
Further, by using the multi-level information of the reproduced signal obtained from the above-mentioned A/D converter during reproduction, it is also possible to significantly improve the error detection ability and error correction ability.

発明の効果 本発明は上記のように記録時のA/D変換部と再生時の
A/D変換器とを共用することにより、A/D変換器の
数を減らすことが可能になυ回路規模を小さくできる。
Effects of the Invention As described above, the present invention provides a υ circuit in which the number of A/D converters can be reduced by sharing the A/D converter during recording and the A/D converter during playback. The scale can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明の実施例のブロック図である。 2.4・・・・・・スイッチ、3・・・・・A/D変換
器、9・・・・・・記録・再生制御部、1o・・・・・
・信号検出部、11・・・・・・誤り訂正部。
The figure is a block diagram of an embodiment of the invention. 2.4...Switch, 3...A/D converter, 9...Record/playback control unit, 1o...
- Signal detection section, 11...Error correction section.

Claims (1)

【特許請求の範囲】[Claims] 画像信号や音声信号をディジタル化して記録するディジ
タル記録装置において、入力信号を標本化してディジタ
ル化するアナログ・ディジタル変換器と、記録された信
号を再生時に標本化してディジタル化して信号検出また
は誤り訂正や誤り検出するときに用いるアナログ・ディ
ジタル変換器とを共用することを特徴とするディジタル
記録装置。
In a digital recording device that digitizes and records image and audio signals, there is an analog-to-digital converter that samples and digitizes the input signal, and a signal detection or error correction that samples and digitizes the recorded signal during playback. A digital recording device characterized in that it shares an analog-to-digital converter used for error detection.
JP14029487A 1987-06-04 1987-06-04 Digital recorder Pending JPS63304470A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14029487A JPS63304470A (en) 1987-06-04 1987-06-04 Digital recorder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14029487A JPS63304470A (en) 1987-06-04 1987-06-04 Digital recorder

Publications (1)

Publication Number Publication Date
JPS63304470A true JPS63304470A (en) 1988-12-12

Family

ID=15265443

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14029487A Pending JPS63304470A (en) 1987-06-04 1987-06-04 Digital recorder

Country Status (1)

Country Link
JP (1) JPS63304470A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007243994A (en) * 2007-06-11 2007-09-20 Toshiba Corp Offset compensation circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007243994A (en) * 2007-06-11 2007-09-20 Toshiba Corp Offset compensation circuit

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