JPS63304318A - Multi-input comparator - Google Patents

Abstract

PURPOSE:To acquire the output data of each sequence at a high speed by using a memory circuit and a level deciding circuit which produces sequentially the selection signals for each shift pulse and in the order of levels. CONSTITUTION:The input data E-H are supplied to a latch circuit 3 and stored there. The latch data 9 undergoes the comparison of levels through a 2-input comparator 4 in terms of the combination to select two out of four pieces of data. Then a level deciding circuit 5 produces successively the selection signals 17 by the outputs of the circuits 4 and in the order of higher levels of data. A coder 14 converts four signals 17 into the 2-bit signals and sends them to a selection circuit 6. The circuit 6 selects a pieces of data corresponding to the selection signal out of the input data 9. Then a shift register 15 stores the selected data synchronously with a shift pulse 12. Thus the output data 7 are arranged in the order of higher levels after inputting the 4th pulse 12.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a multi-input comparator circuit, particularly a multi-input comparator circuit that rearranges data represented by a plurality of binary numbers into one song of the maximum value (or minimum value) of the data and outputs the same. Related to multi-input comparison circuits.

[Conventional technology]

Conventionally, this multi-input comparison circuit has a latch circuit for each input data, a plurality of two-input comparison circuits, a maximum input determination circuit, and a reset circuit, as shown in the case of the 4-input comparison circuit shown in FIG. , a pulse generation circuit, an encoder, a selection circuit, and a 7-foot register. Furthermore, the fifth
The figure is a circuit diagram of the most dog input publication circuit.

Next, its operation will be explained. Four input data 1 (E, F
,G,H)G! , the latch circuit 10 IC is input and stored in synchronization with the latch pulse 2. Next, in the plurality of two-input comparison circuits 4, magnitude comparisons are performed for all combinations in which two of the four are selected. In this case, the number of combinations is (
1) It becomes 6 as determined by formula.

nCr=4 C2=-”knee=62! (4-
2)! °------(1) Since the circuit as a whole outputs the input data in order of thickness, in this comparison circuit, if two pieces of manual data are the same, the data on the A side will be output. It is treated as if it were large.

Next, the outputs 8 of the six two-input comparison circuits 4 are input to the maximum input determination circuit 114C, and one of the four is selected by the logic circuit. In other words, when the input data E is the maximum value, the comparison result of (E≧F)ρ(E≧G)('N(E≧H) is obtained, and the AND circuit 11m
Only the output of AND circuit 11m of -1ip is 1H"
level. Similarly, when the maximum value is input data F, G, or H, AND circuits 11n and llo'!
Ta I! Only the output of lip becomes 1H# level. This 4
The maximum value selection signal 16 consisting of two output lines is transmitted to the encoder 14.
The selection circuit 6 extracts the data corresponding to the maximum value selection signal 16 from the data stored in the latch circuit 10, and extracts the data corresponding to the maximum value selection signal 16. The maximum value selection signal is sent to the reset pulse generation circuit 13.

Missing 1' (77 When pulse 12 is input to shift register 15, register 15 of the first stage of shift register 15
The maximum value data extracted by the selection circuit 6 is stored in a, and a reset pulse is generated l! In the 121 path 13, the respective ANDs of the four output lines of the previous maximum value selection signal 16 and the shift pulse are taken. Of these four logical products 13a to 13d, only one which had previously shown the maximum value outputs the W"H" level, and the data stored in the latch circuit lOK is used as a reset signal. Only the maximum value data is reset and set to 10'. As a result of this operation, the input signal to the two-input comparison circuit 4 updates the comparison data 8 with the second largest data becoming the new maximum value data. Similarly, the comparison data 84 is updated every time the shift pulse 12 is input. In this way, the shift register 15 is prevented from inputting four shift pulses 12.
registers 15d, 15c, 1 in the order of major kina data.
Output data 7 is obtained from 5b and 15a.

[Problem that the invention seeks to solve]

The conventional multi-input comparator circuit described above allows the shift register to hold thick g [C data] by applying shift pulses to the number of input data while selecting only the maximum value. There is a drawback that at least time is required to compare the number of data (b) by two people before the data is output as data for each rank.

An object of the present invention is to use a size determination circuit including a memory circuit.
To provide a multi-input comparator circuit that can quickly obtain output data without repeating the comparison of the two-input comparator circuit multiple times by arranging data from the results of a single two-input comparator circuit in order of size. [Means for solving the problem] The multi-input comparator circuit of the present invention includes a latch circuit that stores data represented by a plurality of binary numbers using tepulses;
m number of 2-input circuits that compare the magnitude relationship for each of all combinations of selecting two pieces of data from a plurality of pieces of data stored in this latch circuit; The data of the maximum value (or minimum value) is determined from the output of the 2-input comparator circuit, and a selection signal is output, and each time a shift pulse is input, the selection signal is held, and the held selection signal and the 2 inputs are a magnitude determination circuit that outputs selection signals in ascending order (or descending order) by repeatedly determining data that is consistently large (or small) by logical product with the output of the comparison circuit; a selection circuit that selects the plurality of pieces of data according to a selection signal output from the size determination circuit;
It is configured to include a shift register that sequentially transfers the output selected by the selection circuit using a shift pulse.

[Example] Next, an example of the present invention will be described with reference to one drawing.

FIG. 1 is a circuit diagram of an embodiment of the present invention, and shows the case of 4 input data. In FIG. 1, the same reference numerals as in FIG. 4 indicate the same components.

In the figure, the four input data l and te pulse 2 are as follows:
It is input to the 7-touch circuit 3. The output of the latch circuit 3 is input to a two-input comparison circuit 4 and a selection circuit 6. The outputs 8 of the six two-input comparison circuits 4, the offset pulse 12, and the reset pulse 18 are input to the magnitude determination circuit 5.

The selection circuit 6 contains the latch circuit 3, ``Yes'', ``Checked'', data 9, and a size determination image lol! A signal obtained by encoding the rank selection signal 17 obtained from r5 by the encoder 14 is input.

The output of the selection circuit 6 and the shift pulse 12 are input to the shift register 15, and its output becomes the output data 7.

To explain the operation of FIG. 1 according to the arrows, first, the four input data 1 (E, F, G, and H)
and is stored in synchronization with latch pulse 2. Next, the latch data 9 is sent to six two-input comparison circuits 4,
A size comparison is performed for all combinations in which two out of four are selected. In addition, since the circuit as a whole outputs the input data in descending order, this comparison circuit
If the two data have the same value, it is assumed that the data of A@ is larger. Next, these six 2
Based on the output of the input comparison circuit 4, the magnitude determination circuit 5 sequentially generates a selection signal 17 for each order of data.

FIG. 2 is a circuit diagram showing an example of the size determination circuit 5. This size determination circuit 5 includes inverter circuits 5al to 5a6.
．． 5cl ~ 5c6, 5g1 ~ 5g6, and AND circuit 5
bl~5b6.5dl~5d6゜5el~5e6.5
hl ~5h4.5 i1~5i4 and OR circuit 5fl
~5f6 and flip-flo.

5j1 to 5j4. First, the flip-flops 511 to 5j4 are all reset by the reset pulse 18.

Next, when six pieces of comparison data 8 are input, respective inverted signals are obtained from inverter circuits 5al to 5a6. These inverted signals have the meanings of E≧F, E≧G, E≧H9F≧G, F≧H, and G≧H for comparison data 8, respectively. AND circuits 5dl to 5d6 include respective comparison data 8 and AND circuits 5bl to 5 of the Q outputs of the signals 5jl to 5j4 related to the two compared signals.
Inverted signals 5cl to 5C6 of b6 are input.

Further, the inverted signals of the comparison data of the respective I words and the output signals of the AND circuits 5bl to 5b6 are input to the AND circuits 5el to 5e6. These two AND circuits 5dl ~5
The logical sum of d6 and 5 e 1 to 5 e 6 is OR circuit 5
In the case of fl, it is expressed by equation (2).

(E<F)・QK−QF+(E≧F)・QE−QF・
...(2) Here, QE and QF are Nori and Gua 0. Indicates the Q output of the group 5J1゜5j2, and these 7
When Tsugu is set, it is ``''L#L# level. Accordingly, when Furi, Gflo, G5jll or 5J2 is set, the OR circuit 5fl changes from O to 1 when E is F, and when E≧F, it changes from l to QK. In other words, the state before being set is reversed. FIG. 2 shows a circuit that generates a signal for selecting input data 1 in order of magnitude from the outputs of these six OR circuits 45fL to 5f6, and this magnitude determination circuit 5 selects input data in order of magnitude. , and the maximum value is initially selected as follows. That is, the reset pulse 18 causes the Qttl of the flip-flops 5j1 to 5j4 to
Since the force is 1 unit and all 1 unit is Hs, OR circuit 5fl to 5f
The output 1 of 6 remains the inverted signal of comparison data 8 as it is. Next, AND circuits 5hl to 5h41j, OR circuit 5
Outputs of fl~5f6 and their inverter circuits 5g1~5
Select the maximum value from the output of g6 and set the output to “l■
“Level it up.

In other words, if the maximum of input data E, F, G, and H is E, the conditions of E≧F, E≧G, and E≧H are satisfied, and only the AND circuit 5hl becomes 1H” level.'! Also, if the maximum is F, then E(F, F≧G.

If the condition of F≧H holds true, only the AND circuit 5h2, if the maximum is G, E(G, H,F
(H, G (H conditions hold, and only the AND circuit 5h4 becomes 1H" level. These AND circuits 5hl
The four signals 5114 to 5114 are sent to the encoder 14 as the rank selection signal 17. Also, it is synchronous with shift pulse 12.

Furi, Gua 0. set only. The Q output of this set Furi and Gufrog is:
Outputs of three of the six AND circuits 5bl to 5b6 are inverted, and three of the outputs of the OR circuits 5fl to 5f6 related thereto are inverted. Therefore, the second largest input data is similarly selected from the remaining three signals of the OR circuit outputs, and is stored in FRI, GFURO, and G5j1 to G5j4 by the second shift pulse 12. At this time, input of the shift pulse 12 is inhibited by the Q output of the flip-flop, which was previously selected to the maximum value, so that the shift pulse is maintained. In this way, by repeating the same operation several times for data, the rank selection signal 17 is generated in an orderly manner.

Next, the encoder 14 converts these four rank selection signals 17 into 2
It is converted into a bit signal and sent to the selection circuit 6.

The selection circuit 6 selects one piece of data corresponding to the selection signal from among the input data 9, and the next shift register 15 stores it in synchronization with the 77th pulse 12. After the fourth shift pulse 12 is input in this manner, data arranged in descending order of magnitude is obtained as output data 7.

In this embodiment, the selection signal from the magnitude determination circuit 5 is encoded by the encoder 14, but depending on the circuit configuration of the selection circuit 6, it may be input as is without being encoded. In this case, the encoder 14 becomes a fumo trap.

FIG. 3 is a circuit diagram of another embodiment of the present invention, showing the case of three input data. Although the circuit configuration and operation are the same as the embodiment shown in FIG. 1, in FIG. 3, there are three 2-input comparison circuits 4 because the comparison is performed by three people. In addition, the size determination circuit 5
A is the AND circuit 5kl to 5 and 3.5n1 to 5n3.
5o1~5゜3 and exclusive 7b0 circuit 511~
513, inverter circuits 5m1 to 5m3, and Furi, Gflo, and G5pl to 5p3, and the two inverter circuits, two AND circuits, and one OR circuit shown in Fig. General circuit 1) Replacement with K Note that in the embodiments shown in FIGS. 1 and 3, the size judgment circuit was supposed to select from the maximum value of the input data, but conversely, it selected from the maximum value of the input data. It is clear that it does not matter what you choose.

〔Effect of the invention〕

As explained above, the present invention provides a trap for each rank of each size having a memory circuit, and a size judgment circuit that sequentially generates a selection signal for each shift pulse. Since the output data can be obtained by comparing two people twice, the output data of each rank can be obtained faster than the conventional circuit.

In addition, in the present invention, the number of times of data is processed within the size judgment circuit of the memory circuit and logic circuit, but the processing time is sufficiently small compared to the two-man comparison, so the overall processing time is shorter than that of the conventional multi-input method. Compared to the comparison circuit, it is approximately 1/the number of data.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is a circuit diagram of the size determination circuit of FIG. 1, and FIG. 3 is a circuit diagram of another embodiment.
Figure 4 is a circuit diagram of a conventional multi-input comparison circuit, and Figure 5 is a circuit diagram of a conventional multi-input comparison circuit.
FIG. 3 is a circuit diagram of a maximum input determination circuit in the figure. 1...Manpower data, 2.12...Shift pulse, 3.3A, 10...Latch circuit, 4
...2-input comparison circuit, 5.5A...size judgment circuit, 6.6A...selection circuit, 7...
...Output data, 8...Comparison data, 9.-
... Latch data, 11 ... Most input determination circuit, 13 ... Reset pulse generation circuit, 14
゜14A... Encoder, 15,15A...
・Shift register, 17... Rank selection signal. ) r'Jl 宭 2 fig. 3 fig.'! J 4 Figure No. 5

Claims (1)

[Claims] A latch circuit that stores data represented by a plurality of binary numbers using latch pulses, and a plurality of latch circuits that compare the magnitude relationships for all combinations of selecting two pieces of data from the plurality of pieces of data stored in this latch circuit. A two-input comparator circuit and, after being initialized by a reset pulse, determines the maximum value (or minimum value) data from the outputs of the plurality of two-input comparator circuits, outputs a selection signal, and inputs a shift pulse. By holding the selection signal for each time, and repeating the judgment of the next largest (or smallest) data by ANDing the held selection signal and the output of the two-input comparator circuit, a magnitude determination circuit that outputs a selection signal; a selection circuit that selects a plurality of pieces of data stored in the latch circuit according to a selection signal output from the magnitude determination circuit; and a shift pulse that outputs the output selected by the selection circuit. 1. A multi-input comparison circuit comprising: a shift register that sequentially transfers data.