JPH0397038A - Multiplier - Google Patents

Abstract

PURPOSE:To make a test for discriminating the quality of an LSI easily dividing a multiplier into plural blocks by utilizing the regularity and symmetricality of the multiplier, impressing the same pattern, comparing outputs, and executing the test. CONSTITUTION:A test means is provided to be composed of means 7 and 8 to divide the multiplier into the plural blocks, where mutual signals are interrupted, equipped with the same function, means 5-8 to impress the common pattern for test to the respective blocks, and comparator 15 to compare the outputs from respective blocks when this pattern is impressed. Thus, by supplying the common test pattern to the same plural blocks 9-11, where the multiplier is divided, and investigating coincidence among the outputs of the respective blocks, the multiplier can be realized to easily execute the quality test while extremely suppressing the degradation of operating speed and the increase of a circuit area.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a multiplier that can be easily tested to determine whether it is a good product when testing the multiplier using an integrated circuit.

(Prior Art) A multiplier with an input bit count of nXn has a total number of combinations of inputs of 2 to the power of 2n, and as n increases,
It becomes difficult to test all human power combinations (confirm the consistency of input and output).

In order to solve these problems, the multiplier testing method is called "Test", which makes the macrocells that make up the multiplier capable of testing themselves, and allows testing at the cell level with a small number of clicks. Possible VLSI array multiplier design J (
The Design of Easy Testab
leVLSI Array Multipliers)
IEEE Trans. on Comp.
p. 554-560. It has been reported in 1984 etc.

In addition, in order to suppress speed deterioration, a bang generator is placed at the input section of the multiplier, and a bang compressor is placed at the output section, and after applying a large number of patterns, the data in the batan compressor is calculated in advance by logic simulation. One possible method is to compare it with the previously set value.

(To be solved by the invention) In the former of the above-mentioned two conventional methods, the multiplier is complex [[
Since the multiplier is constructed of macro cells, not only does the speed of the multiplier as a whole deteriorate, but when it is implemented into an LSI, the circuit area inevitably increases significantly.

In the latter case, although there is little deterioration in terms of speed, this tendency becomes particularly noticeable when the number of design steps required for simulation increases and the bit length becomes longer. Furthermore, it is also necessary to perform a simulation in advance to determine how many slams should be applied to obtain a desired failure coverage rate.

That is, the conventional multiplier testing method has drawbacks such as a decrease in speed, an increase in circuit construction area, and an increase in the number of design steps.

An object of the present invention is to provide a multiplier that can perform tests without obtaining data compression results while minimizing overhead in speed and circuit area.

(Means for Solving the Problems) The present invention includes means for dividing a multiplier into a plurality of blocks having the same function and having mutual signals cut off, and means for applying a common test pattern to each block. , and a comparator for comparing outputs from each block when this pattern is applied.

(Function) By supplying a common test pattern to multiple identical blocks into which the multiplier is divided and checking whether the outputs (or their compressed results) of each block match, deterioration in operating speed and increase in circuit area can be reduced. It is possible to realize a multiplier that can be easily tested for non-defective products with significantly reduced performance. Furthermore, since it is only necessary to confirm that the output of each block or the result of compressing the output is the same, the test results can be confirmed with a simple comparator.

Therefore, complicated simulation is not necessary.

(Example) Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a structural diagram showing an embodiment of the present invention.

This multiplier performs the multiplication operation and test operation described below.

(During multiplication operation) Figure 1 shows a 2n x 2n bit multiplier, and when the upper register of the multiplicand, the lower register of the multiplicand, the lower register of the multiplier, and the upper register of the multiplier are given to the n-bit length registers 1 to 4, respectively. , are supplied to first to fourth multipliers 9 to 12, respectively. The dotted line in the figure indicates that the data passes through as is and is supplied to the next multiplier. In the second multiplier 10, the lower part of the multiplicand is multiplied by the lower part of the multiplier, and the carry signal is
The signal is supplied to the first multiplier 9 and the third multiplier 11 through the switch 7 , and to the fourth multiplier 12 through the second buffer 6 . When the first multiplier 9 receives the carry signal from the second multiplier that has passed through the first switch 7, it multiplies the upper part of the multiplicand and the lower part of the multiplier by using this as a carry signal. Further, the fourth multiplier 12 receives the output of the second multiplier that has passed through the second buffer 6 as a carry, and multiplies the lower part of the multiplicand and the upper part of the multiplier using this as a carry. The third multiplier 11 includes the first switch 7
The output of the second multiplier 10 that has passed through the filter, the output of the first multiplier 9 that has passed the first buffer 5, and the output of the fourth multiplier 12 that has passed the second switch 8 are used as carry signals to calculate the multiplicand. Multiply the upper order and the upper order of the multiplier. 3rd and 4th buffer 13
, 14 have the role of holding the multiplication results.

(During test operation) During test operation, the first and second switchers 7 and 8 and the first and second
Buffers 5 and 6 always output O. Due to this,
The human power of the 1st to 4th multipliers 9 to 13 is the 1st to 4th registers 1 to 13.
4 is the only output, and the signals between the multipliers are cut off. Here, the first and second registers and the third and fourth registers are set to LF.
SR (Lenear Feedback Shift)
If the same random number pattern is generated by using a button generator such as a register (Register), the input patterns of the first to fourth multipliers 9 to 12 will be the same,
It is expected that the output button of each multiplier will be the same.

The output of each multiplier is the lth to fourth buffers 5, 6, 13, 14.
The outputs of the first to fourth buffers are input to the comparator 15 during test operation. In this way, the outputs of the buffers (or the compressed results) are compared by the comparator 15, and
Output whether all match. In other words, when a certain pattern is applied, if all four outputs match, it is a good product, and if even one is different, then the
4 multipliers 9 to 13, or 1st to 4th buffers 5, 6,
It can be seen that there are defects in the transistors, wiring, etc. in 13 and 14.

In a few batons, all the transistors inside the multiplier,
Since it is impossible to judge whether the wiring is good or bad, the multiplier is tested by sequentially generating a large number of patterns in the first to fourth registers 1 to 4 and monitoring the output of the comparator 15. .

(Effects of the Invention) As described above, the conventional multiplier testing method has drawbacks such as a decrease in speed and an increase in area, and requires a lot of man-hours for simulation. In the present invention, a multiplier realized using an integrated circuit is divided into a plurality of parts by taking advantage of its regularity and symmetry, and the test is performed by applying the same pattern and comparing the outputs. In the present invention, a conventional circuit can be used for the multiplier main body, and the deterioration in speed is about one gate for switching the test multiplication operation. Furthermore, since many of the peripheral circuits are circuits associated with conventional multipliers with additional functions, there is no increase in area. Moreover, since only a comparison operation is performed, there is no need to calculate an expected value by simulation. According to the present invention, it has become possible to easily perform LSI quality discrimination tests.

[Brief explanation of drawings]

FIG. 1 is a logic circuit block diagram showing an embodiment of the present invention. 1, 2... n-bit long multiplicand register, 3, 4...
. . . n-bit length multiplier register, 5, 6 . . . buffer, 7, 8 . . . switching circuit, 9 to 12. nXn bit multiplier, 13.14...output buffer, 15
...Comparator.

Claims (1)

[Claims] A means for dividing a multiplier into a plurality of blocks having the same function and having mutual signals cut off, a means for applying a common test pattern to each block, and an output from each block when this pattern is applied. A multiplier characterized in that it is equipped with a test means consisting of a comparator for comparing the .