CN103853524B - Multiplier device and multiplying method - Google Patents
Multiplier device and multiplying method Download PDFInfo
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- CN103853524B CN103853524B CN201210509001.XA CN201210509001A CN103853524B CN 103853524 B CN103853524 B CN 103853524B CN 201210509001 A CN201210509001 A CN 201210509001A CN 103853524 B CN103853524 B CN 103853524B
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Abstract
The invention provides a multiplier device which comprises a comparator, a first selector, a second selector and a multiplication unit. The comparator is used for comparing a high-k bit of a first multiplier with 0, and if the high-k bit is unequal to 0, the multiplication unit outputs data of low-(c-a+k-1) bit of the first multiplier and a second multiplier after multiplication; if the high-k bit is equal to 0, the multiplication unit outputs data of low-(a-k) bit of the first multiplier and the second multiplier after multiplication; the bit width of the first multiplier is a while the bit width of the second multiplier is b, and the maximum value of the bit width of multiplication of the first multiplier and the second multiplier is c; when c＞a+b and 2b＞/=c are met, an optional natural number k can be selected within an open interval of (a-b, a+b-c+1) to form an aXs multiplier, and s can be guaranteed to be smaller than b. Therefore, the multiplier device is more modified in structure and small in occupation. The invention further provides a method for implementing multiplication.
Description
Technical field
The present invention relates to hardware designs field, especially relate to a kind of multiplier device and the method realizing multiplying.
Background technology
Multiplier is a kind of conventional logical device, realizes the multiplying to two numbers by hardware circuit.With hard
The high speed development of part circuit and the continuous improvement to various terminals operational capability demand, the requirement to multiplier is also constantly carrying
High.According to different application scenarios, designer proposes different requirements to the speed of multiplier, area, power consumption etc., however,
Under many circumstances it may be necessary to sacrifice performance in a certain respect to obtain more excellent another aspect performance, such as needs to reach
During higher arithmetic speed, the bigger multiplier of space required just enables.In the prior art, according to different application demands
Such as Wallace Tree multiplier, multiple multiplier such as booth multiplier are derived.Wherein, Synopsys company utilizes it
In the advantage of logic synthesis (logic synthesis) aspect accumulation, in netlist level to general in its Designware product
Multiplier has carried out good optimization, all obtains larger advantage on the area of multiplier and performance of both speed.
In these prior arts, design and the target optimizing are all general purpose multipliers.So-called " general ", the meaning is multiplier
Two multipliers completely irrelevant, once it is determined that the bit wide of two multipliers, then the span of multiplier is exactly appointing in the range of bit wide
Meaning may value.For example, bit wide is respectively to two multipliers of a and b, the structure of the general purpose multipliers of employing is a × b.Real
On border, in real world applications, a lot of situations are the relations between two multipliers with negative correlation, and that is, a multiplier is another when increasing
Multiplier necessarily reduces, and when a multiplier reduces, another multiplier inevitably enlarges, and the bit wide of the product of two multipliers is less than two
The bit wide sum of individual multiplier.At present, even if multiplier meets negative correlativing relation, remain on and adopt general purpose multipliers.However, it is general
Often area occupied is larger for multiplier, and complex structure.
Content of the invention
Present invention solves the technical problem that being to provide one kind can reduce multiplier when multiplier meets negative correlativing relation
Area, the multiplier device optimizing multiplier architecture and the method realizing multiplying.
For this reason, the technical scheme that the present invention solves technical problem is：
The invention provides a kind of multiplier device, described device includes：Comparator, first selector, second selector
And multiplication unit；
Described comparator is used for comparing the high k position of the first multiplier with 0, if unequal, sends the first control signal
To first selector and second selector, if equal, send the second control signal to first selector and second selector；
The input data of the first input end of described first selector is the first multiplier, the second input of first selector
Input data be the second multiplier, described first selector selects first input end conduct after being used for receiving the first control signal
Input, selects the second input as input, by the input number of the input after selecting after receiving the second control signal
According to the 5th input being exported by outfan to described multiplication unit；Wherein, the bit wide of described first multiplier is a, and second takes advantage of
The bit wide of number is b, and the maximum of the bit wide of the product of the first multiplier and the second multiplier is c, and (a+b) is more than c, and a is not less than b,
2b is not less than c；
The input data of the 3rd input of described second selector is the low m-bit data of the second multiplier, second selector
The 4th input input data be the first multiplier low n-bit data, described second selector is used for receiving the first control
Select the 3rd input after signal as input, select the 4th input after receiving the second control signal as input,
The input data of the input after selecting is exported by outfan to the 6th input of described multiplication unit；Wherein, m=c-
A+k-1 and n=a-k, k be more than a-b and less than a+b-c+1 arbitrary natural number；
Described multiplication unit is used for for the data of the 5th input and the 6th input carrying out output after multiplying, described
The bit wide of the 5th input is a, and the bit wide of the 6th input is maximum number in m and n.
Preferably, wherein,
When described c is odd number, k=(2a-c+1)/2, then the bit wide of described 6th input is (c-1)/2.
Preferably, wherein,
When described c is even number, k=(2a-c)/2+1 or (2a-c)/2, then the bit wide of described 6th input is c/2-1.
Preferably, described device also includes：First depositor, the second depositor and the 3rd depositor；
Described first depositor after being used for the first multiplier is deposited sends the first multiplier to the of first selector
One input, the low n-bit data of the first multiplier is sent to the 4th input of second selector and the height by the first multiplier
K position data is activation is to described comparator；
Described second depositor after being used for the second multiplier is deposited sends described second multiplier to the described first choosing
Select the second input of device and the low m-bit data of the second multiplier is sent to the 3rd input of second selector；
Described comparator be used for by the high k position of the first multiplier compare with 0 including：Described comparator is used for the first depositor
The high k position of the first multiplier sending is compared with 0；
Described multiplication unit is used for for the data of the 5th input and the 6th input carrying out output inclusion after multiplying：
Described multiplication unit is used for carrying out exporting after multiplying by the data of the 5th input and the 6th input posting to the described 3rd
Storage；
Described 3rd depositor exports after being used for the data after described multiplication unit multiplying is deposited.
Preferably, described device also includes：4th depositor, the 5th depositor, the 6th depositor and the 3rd depositor；
Described 4th depositor after being used for the first multiplier is deposited sends the first multiplier to the of first selector
The one input and low n-bit data of the first multiplier being sent to the 4th input of second selector；
Described 5th depositor after being used for the second multiplier is deposited sends described second multiplier to the described first choosing
Select the second input of device and the low m-bit data of the second multiplier is sent to the 3rd input of second selector；
Described comparator sends the first control signal and includes to first selector and second selector：
Described comparator sends the first control signal to the 6th depositor；
Described comparator sends the second control signal and includes to first selector and second selector：
Described comparator sends the second control signal to the 6th depositor；
The signal that described 6th depositor is used for that comparator is sent is deposited and is sent the signal after depositing respectively
To first selector and second selector；
Described multiplication unit is used for for the data of the 5th input and the 6th input carrying out output inclusion after multiplying：
Described multiplication unit is used for carrying out exporting after multiplying by the data of the 5th input and the 6th input posting to the described 3rd
Storage；
Described 3rd depositor exports after being used for the data after described multiplication unit multiplying is deposited.
Preferably, described device also includes：7th depositor, the 8th depositor and the 3rd depositor；
Described first selector is used for exporting to described multiplication the input data of the input after selecting by outfan
5th input of unit includes：Described first selector is used for will be defeated by outfan for the input data of the input after selecting
Go out to the 7th depositor；
The data that 7th depositor is used for first selector is sent is deposited and by the data is activation after depositing to institute
State the 5th input of multiplication unit；
Described second selector is used for exporting to described multiplication the input data of the input after selecting by outfan
6th input of unit includes：Described second selector is used for will be defeated by outfan for the input data of the input after selecting
Go out to the 8th depositor；
The data that 8th depositor is used for second selector is sent is deposited and by the data is activation after depositing to institute
State the 6th input of multiplication unit；
Described multiplication unit is used for for the data of the 5th input and the 6th input carrying out output inclusion after multiplying：
Described multiplication unit is used for carrying out exporting after multiplying by the data of the 5th input and the 6th input posting to the described 3rd
Storage；
Described 3rd depositor exports after being used for the data after described multiplication unit multiplying is deposited.
Present invention also offers a kind of method realizing multiplying, the bit wide of the first multiplier is a, the bit wide of the second multiplier
For b, the maximum of the bit wide of the product of the first multiplier and the second multiplier is c, and a+b is more than c, and a is not less than b, and 2b is not less than c,
Methods described includes：
The high k position of the first multiplier is compared with 0, if unequal, by multiplication unit by the low m of described second multiplier
Position with described first multiplier make multiplying, if equal, by described multiplication unit by the low n position of described first multiplier with
Described second multiplier makees multiplying；
Wherein, m=c-a+k-1 and n=a-k, k be more than a-b and less than a+b-c+1 arbitrary natural number.
Preferably, wherein,
When described c is odd number, k=(2a-c+1)/2.
Preferably, wherein,
When described c is even number, k=(2a-c)/2+1 or k=(2a-c)/2.
Preferably, described by the high k position of the first multiplier compare with 0 including：By comparator by the high k position of the first multiplier with
0 compares.
As seen through the above technical solutions, the bit wide of the first multiplier is a, and the bit wide of the second multiplier is b, and a is not less than b, the
The bit wide maximum of the product of one multiplier and the second multiplier is c, is less than (a+b) when meeting c, and when 2b is not less than c, then can be
An optional natural number k in open interval (a-b, a+b-c+1), composition one a × s multiplier, wherein s be a-k and c-a+k-1 in
Big number, because k is located in open interval (a-b, a+b-c+1), therefore can ensure that s is less than b.Thus the multiplier dress of the present invention
The logical structure of the critical piece multiplication unit put is reduced to a × s by a × b of general purpose multipliers, and one increased is compared
Device and two MUX are all that area is little, and the short basic device of logical path, therefore present invention achieves structure is more excellent
The less multiplier device of change, area occupied.
Brief description
The specific embodiment structural representation of the multiplier device that Fig. 1 provides for the present invention；
The another specific embodiment structural representation of the multiplier device that Fig. 2 provides for the present invention；
The another specific embodiment structural representation of the multiplier device that Fig. 3 provides for the present invention；
The another specific embodiment structural representation of the multiplier device that Fig. 4 provides for the present invention；
The another specific embodiment structural representation of the multiplier device that Fig. 5 provides for the present invention；
The schematic flow sheet realizing multiplying method that Fig. 6 provides for the present invention.
Specific embodiment
In real world applications, a lot of situations are the relations between two multipliers with negative correlation, when that is, a multiplier increases
Another multiplier necessarily reduces, and when a multiplier reduces, another multiplier inevitably enlarges, and the bit wide of the product of two multipliers is little
In the bit wide sum of two multipliers, this relation often can make the structure of multiplier and area have some specific optimization skies
Between.When the present invention is namely based on two multipliers and has negative correlativing relation, provide that one kind is capable of structure and area occupied obtains
The multiplier device optimizing.
Refer to Fig. 1, the invention provides a kind of multiplier device, described device includes：Comparator 101, first choice
Device 102, second selector 103 and multiplication unit 104.
Described comparator 101 is used for comparing the high k position of the first multiplier with 0, if unequal, send first and controls letter
Number to first selector 102 and send the first control signal to second selector 103, if equal, send second control
Signal to first selector 102 and sends the second control signal to second selector 103.
The input data of the first input end of described first selector 102 is the first multiplier, the second of first selector 102
The input data of input is the second multiplier, and described first selector selects the first input after being used for receiving the first control signal
End, as input, selects the second input as input, by the input after selecting after receiving the second control signal
Input data is exported by outfan to the 5th input of described multiplication unit 104；Wherein, the bit wide of described first multiplier is
A, the bit wide of the second multiplier is b, and the maximum of the bit wide of the product of the first multiplier and the second multiplier is c, and that is, this product is all
Possible bit wide is more than c no more than c, i.e. a+b, and a is not less than b, and 2b is not less than c.
The input data of the 3rd input of described second selector 103 is the low m-bit data of the second multiplier, the second selection
The input data of the 4th input of device 103 is the low n-bit data of the first multiplier, and described second selector 103 is used for receiving
Select the 3rd input as input after first control signal, after receiving the second control signal, select the 4th input conduct
Input, the input data of the input after selecting is exported by outfan to the 6th input of described multiplication unit 104；
Wherein, m=c-a+k-1 and n=a-k, k be more than a-b and less than a+b-c+1 arbitrary natural number.
Described multiplication unit 104 is used for for the data of the 5th input and the 6th input carrying out output after multiplying,
The bit wide of described 5th input is a, and the bit wide of the 6th input is maximum several s in m and n.
As seen through the above technical solutions, in this embodiment, the bit wide of the first multiplier is a, and the bit wide of the second multiplier is b, a
Not less than b, the bit wide maximum of the product of the first multiplier and the second multiplier is c, is less than (a+b) when meeting c, and 2b is not less than
During c, then can in open interval (a-b, a+b-c+1) an optional natural number k, composition one a × s multiplier, wherein s be a-k and
Maximum number in c-a+k-1, because k is located in open interval (a-b, a+b-c+1), therefore can ensure that s is less than b.Thus this is real
The logical structure applying the critical piece multiplication unit of the multiplier device in example is reduced to a × s by a × b of general purpose multipliers,
And an increased comparator and two MUX are all that area is little, the short basic device of logical path, the therefore present invention
Achieve the multiplier device that structure more optimizes, area occupied is less.
When introducing c separately below for even number and odd number, when the structure of multiplication unit 104 is optimum, area occupied is minimum, k's takes
Value.
When described c is even number, the structure optimum of multiplication unit 104, occupancy during k=(2a-c)/2 or k=(2a-c)/2+1
Area is minimum, and, to meet the bit wide of described 6th input during k=(2a-c)/2 be c/2-1, during k=(2a-c)/2+1 with
The bit wide that sample meets described 6th input is c/2-1.Now the result of multiplication unit 104 is a × (c/2-1).
When described c is odd number, during k=(2a-c+1)/2, the structure optimum of multiplication unit 104, area occupied are minimum, and
Now meet：The bit wide of described 6th input is (c-1)/2.Now the structure of multiplication unit 104 is a × [(c-1)/2].
When two multipliers of multiplier are described below having negative correlativing relation, the structure of the multiplier being adopted is realized optimizing
Derivation.Because the input of multiplier, output are integer, the number being therefore related in the present invention is integer.
There is between two multiplier X and Y the relation of negative correlation, when that is, a multiplier increases, another multiplier necessarily reduces, one
When individual multiplier reduces, another multiplier inevitably enlarges, and the bit wide of the product of two multipliers be less than two multipliers bit wide it
With.
The bit wide of the first multiplier X is a, and the bit wide of the second multiplier Y is b, might as well assume a >=b.First multiplier X and second takes advantage of
The maximum of the product of number Y is c, and c needs to meet c<A+b, otherwise needs to use general purpose multipliers.
If X [a1] represents the numerical value of the binary number of a1 bit of number X；X[a1：A2] represent number X from a1 bit to
The numerical value of the binary number of a2 bit composition.
It is first whether 0 alternatively condition with the highest bit of the first multiplier X.As X [a-1]=0, multiplier becomes X
[a-2：0]×Y[b-1：0], it is designated as the multiplier 1 that b position is taken advantage of in (a-1) position；As X [a-1]=1, represent that a bit of X has been
Effect position, then the significance bit of Y up to c-a position, i.e. Y [c-a-1：0] it is significance bit, higher digit is invalid, and now multiplier becomes
Become X [a-1] × Y [c-a-1：0], it is designated as the multiplier 2 that (c-a) position is taken advantage of in a position.Continue to derive with same method, it is known that
If with the highest 2 bit alternatively condition of a, multiplier 1 takes advantage of b position for (a-2) position, and multiplier 2 takes advantage of (c-a+1) position for a position.
Conclusion is derived to the highest k bit alternatively condition with X, then multiplier 1 takes advantage of b position, multiplier for (a-k) position
2 take advantage of (c-a+k-1) position for a position.As shown in table 1.
Table 1
Bit wide A of two factors of note multiplier 1 and B are respectively A=a-k, B=b.
Bit wide C of two factors of note multiplier 2 and D are respectively C=a, D=c-a+k-1.
Two bit wides of final multiplier are designated as M and N respectively, might as well assume M >=N, then have
M=MAX (MAX (A, B), MAX (C, D))=MAX (A, B, C, D)
N=MAX (MIN (A, B), MIN (C, D))
Wherein, MAX (a1, a2) is maximum number in a1 and a2, and MIN (a1, a2) is minimum number in a1 and a2.By
In the bit wide of four factors, a is always maximum, therefore always has M=a, needs to obtain N so that N<B, so that the present invention is real
Existing multiplier is than the more optimized structure of general purpose multipliers.
N=MAX (MIN (A, B), MIN (C, D))=MAX (MIN (A, B), D), as A >=B, N=MAX (B, D), therefore N
>=B, i.e. N >=b, but because M=a, now multiplier M × N does not have and realizes more optimizing than general purpose multipliers a × b.
Therefore need to meet A<B, now N=MAX (A, D).In order to ensure to realize more optimizing than general purpose multipliers, then N<B, because
This A<B and D<B, i.e. (a-b)<K and k<(a+b-c+1).In order to ensure the presence of k, there is (a-b)<(a+b-c+1), that is, (c-1)/2
<B, due to b, c is integer, therefore only need to meet 2b >=c.
To sum up, when meeting c<A+b and 2b >=c, wherein a >=b, choose whether equal with the 0 alternatively bar in high k position of a
Part can achieve the more excellent multiplier of structure, wherein, (a-b)<K and k<(a+b-c+1).
The derivation of the k value of structure optimum that can make multiplier is described below.
In order that the more optimized structure of multiplier need to meet A<B is so that N=MAX (A, D) is it can be seen that A+D=c-
1 is constant value, will obtain the N value of minimum, A and D only need to be made as far as possible close.In positive integer domain, when c is odd number, need
Meet A=D, when c is even number, A=D+1 or A=D-1 need to be met, solution k value out is integer.
Due to A=a-k, D=c-a+k-1, when can obtain c for odd number, k=(2a-c+1)/2, A=D=(c-1)/2, N
=(c-1)/2.
When c is even number, k=(2a-c)/2, A=c/2, D=c/2-1, N=c/2-1；
Or when c is even number, k=(2a-c)/2+1, A=c/2-1, D=c/2, N=c/2-1.
Thus, we obtain to meet c<The optimum multiplier a of structure × N, wherein a >=b during a+b and 2b >=c, c are
During odd number, when k=(2a-c+1)/2 and N=(c-1)/2, c are even number, k=(2a-c)/2 or (2a-c)/2+1, N=c/
2-1.
A kind of specific embodiment of multiplier device that Fig. 2 provides for the present invention.In this embodiment, the position of the first multiplier X
A width of a=12, bit wide b=10 of the second multiplier Y, the first multiplier and the second multiplier meet negative correlativing relation, that is, the first multiplier and
The bit wide maximum of the product of the second multiplier is c, c=14.As can be seen that a, b and c meet following relation：A+b is more than c, and a is not
It is not less than c less than b and 2b.Because c is even number, therefore take k=(2a-c)/2=5.This device specifically includes：
Comparator 101, first selector 102, second selector 103 and multiplication unit 104.
Described comparator 101 is used for comparing high 5 of the first multiplier with 0, if unequal, send first and controls letter
Number to first selector 102 and send the first control signal to second selector 103, if equal, send second control
Signal to first selector 102 and sends the second control signal to second selector 103.
The input data at 0 end of described first selector 102 is the first multiplier X, the input at 1 end of first selector 102
Data is the second multiplier Y, and described first selector selects 0 end as input after being used for receiving the first control signal, receive
Select 1 end as input to after the second control signal, by the input data of the input after selecting by outfan export to
5th input of described multiplication unit 104.
The input data at 0 end of described second selector 103 is the low m-bit data of the second multiplier, wherein m=c-a+k-1
=6, the input data at 1 end of second selector 103 is the low n-bit data of the first multiplier, wherein n=a-k=7, described second
Selector 103 selects 0 end as input after being used for receiving the first control signal, selects 1 after receiving the second control signal
End, as input, the input data of the input after selecting is exported by outfan to the 6th of described multiplication unit 104
Input.
Described multiplication unit 104 is used for for the data of the 5th input and the 6th input carrying out output after multiplying,
The bit wide of described 5th input is 12, and the bit wide of the 6th input is maximum number 7 in 6 and 7.
In actual applications, the second selector 103 of 7 can be selected can to meet the requirement of this embodiment.
In conjunction with the consideration of logical path timing path, the logical path for making every one-level is as far as possible close, in practical application
In be optimized often through register pair sequential.It is described below that to add depositor and realizing that sequential is carried out in diverse location excellent
The embodiment changed.
Because multiplication unit logical path is long, therefore generally before being multiplied, one is deposited to two multiplier depositors
Under, after multiplication, product depositor is deposited.It is illustrated below by an embodiment.
The another specific embodiment of the multiplier device that Fig. 3 provides for the present invention, in this embodiment, the position of the first multiplier X
A width of a=12, bit wide b=10 of the second multiplier Y, the maximum of the bit wide of the product of the first multiplier and the second multiplier is c, c=
14.As can be seen that a, b and c meet following relation：A+b is more than c, and a is not less than b and 2b and is not less than c.Because c is even number, therefore
Take k=(2a-c)/2=5.This embodiment includes：Comparator 101, first selector 102, second selector 103, multiplication unit
104th, the first depositor 301, the second depositor 302 and the 3rd depositor 303.
Described first depositor 301 after being used for the first multiplier X is deposited sends the first multiplier X to first selector
0 end, the low n-bit data of the first multiplier X is sent 1 end to second selector and the high k position data by the first multiplier X
Send to comparator 101, wherein n=c-a=7, k=(2a-c)/2=5.
Described second depositor 302 after being used for the second multiplier Y is deposited sends described second multiplier Y to described the
1 end of the one selector 102 and low m-bit data of the second multiplier Y being sent to 0 end of second selector 103, wherein, m=c-a+
K-1=6.
Be used for sending the first depositor 301 high 5 of the first multiplier X compare, if not described comparator 101 with 0
Equal, then send the first control signal respectively to first selector 102 and second selector 103, if equal, send respectively
Second control signal is to first selector 102 and second selector 103.
Described first selector 102 selects 0 end as input after being used for receiving the first control signal, receives second
Select 1 end as input after control signal, the input data of the input after selecting is exported by outfan and takes advantage of to described
5th input of method unit 104.
Described second selector 103 selects 0 end as input after being used for receiving the first control signal, receives second
Select 1 end as input after control signal, the input data of the input after selecting is exported by outfan and takes advantage of to described
6th input of method unit 104.
Described multiplication unit 104 be used for by the data of the 5th input and the 6th input carry out exporting after multiplying to
3rd depositor 303, the bit wide of described 5th input is 12, and the bit wide of the 6th input is maximum number 7 in 6 and 7.
Described 3rd depositor 303 exports after being used for the data after the multiplying of described multiplication unit 104 is deposited.
When the sequential of multiplication unit is more nervous it is also possible to comparator is put into the previous cycle shift to an earlier date computing, it is used in combination
Depositor is deposited, and optimizes the logical path with comparator as starting point.It is illustrated below by an embodiment.
The another specific embodiment of the multiplier device that Fig. 4 provides for the present invention, in this embodiment, the position of the first multiplier X
A width of a=12, bit wide b=10 of the second multiplier Y, the maximum of the bit wide of the product of the first multiplier and the second multiplier is c, c=
14.As can be seen that a, b and c meet following relation：A+b is more than c, and a is not less than b and 2b and is not less than c.Because c is even number, therefore
Take k=(2a-c)/2=5.This embodiment includes：Comparator 101, first selector 102, second selector 103, multiplication unit
104th, the 3rd depositor 303, the 4th depositor 401, the 5th depositor 402 and the 6th depositor 403.
Described 4th depositor 401 after being used for the first multiplier X is deposited sends the first multiplier X to first selector
0 end and the low n-bit data of the first multiplier X is sent to 1 end of second selector, wherein n=c-a=7.
Described 5th depositor 402 after being used for the second multiplier Y is deposited sends described second multiplier Y to described the
1 end of the one selector 102 and low m-bit data of the second multiplier Y being sent to 0 end of second selector 103, wherein, m=c-a+
K-1=6.
Described comparator 101 is used for comparing high 5 of the first multiplier X with 0, if unequal, sends the first control
Signal, to the 6th depositor 403, if equal, sends the second control signal to the 6th depositor 403.
The signal that described 6th depositor 403 is used for sending comparator 101 is deposited and is divided the signal after depositing
Do not send to first selector 102 and second selector 103.
Described first selector 102 selects 0 end as input after being used for receiving the first control signal, receives second
Select 1 end as input after control signal, the input data of the input after selecting is exported by outfan and takes advantage of to described
5th input of method unit 104.
Described second selector 103 selects 0 end as input after being used for receiving the first control signal, receives second
Select 1 end as input after control signal, the input data of the input after selecting is exported by outfan and takes advantage of to described
6th input of method unit 104.
Described multiplication unit 104 be used for by the data of the 5th input and the 6th input carry out exporting after multiplying to
3rd depositor 303, the bit wide of described 5th input is 12, and the bit wide of the 6th input is maximum number 7 in 6 and 7.
Described 3rd depositor 303 exports after being used for the data after the multiplying of described multiplication unit 104 is deposited.
When front end logic is not very nervous, before the first and second selectores can also being placed on prime depositor,
Allow rear class exclusively carry out multiplier logic computing, optimize the sequential of multiplier device further.Specifically refer to the enforcement shown in Fig. 5
Example.
The another specific embodiment of the multiplier device that Fig. 5 provides for the present invention, in this embodiment, the position of the first multiplier X
A width of a=12, bit wide b=10 of the second multiplier Y, the first multiplier and the second multiplier meet negative correlativing relation, that is, the first multiplier and
The maximum of the bit wide of the product of the second multiplier is c, c=14.As can be seen that a, b and c meet following relation：A+b is more than c, a
It is not less than c not less than b and 2b.Because c is even number, therefore take k=(2a-c)/2=5.This embodiment includes：Comparator 101,
One selector 102, second selector 103, multiplication unit 104, the 7th depositor 501, the 8th depositor 502 and the 3rd depositor
303.
Described comparator 101 is used for comparing high 5 of the first multiplier with 0, if unequal, send first and controls letter
Number to first selector 102 and send the first control signal to second selector 103, if equal, send second control
Signal to first selector 102 and sends the second control signal to second selector 103.
The input data at 0 end of described first selector 102 is the first multiplier X, the input at 1 end of first selector 102
Data is the second multiplier Y, and described first selector selects 0 end as input after being used for receiving the first control signal, receive
Select 1 end as input to after the second control signal, by the input data of the input after selecting by outfan export to
7th depositor 501.
The data that 7th depositor 501 is used for that first selector 102 is sended over is deposited and by the number after depositing
According to the 5th input sending to described multiplication unit 104.
The input data at 0 end of described second selector 103 is the low m-bit data of the second multiplier, wherein m=c-a+k-1
=6, the input data at 1 end of second selector 103 is the low n-bit data of the first multiplier, wherein n=a-k=7, described second
Selector 103 selects 0 end as input after being used for receiving the first control signal, selects 1 after receiving the second control signal
End, as input, the input data of the input after selecting is exported to the 8th depositor 502 by outfan.
The data that 8th depositor 502 is used for that second selector 103 is sended over is deposited and by the number after depositing
According to the 6th input sending to described multiplication unit.
Described multiplication unit 104 be used for by the data of the 5th input and the 6th input carry out exporting after multiplying to
3rd depositor 303, the bit wide of described 5th input is 12, and the bit wide of the 6th input is maximum number 7 in 6 and 7.
Described 3rd depositor 303 exports after being used for the data after the multiplying of described multiplication unit 104 is deposited.
Refer to Fig. 6, present invention also offers a kind of method realizing multiplying, the bit wide of the first multiplier is a, second
The bit wide of multiplier is b, and the maximum of the bit wide of the product of the first multiplier and the second multiplier is c, and a+b is more than c, and a is not less than b,
2b is not less than c, and methods described includes：
S601：The high k position of the first multiplier is compared with 0, if unequal, execute S602, if equal, execute
S603.
S602：The low m position of described second multiplier and described first multiplier are made by multiplying by multiplication unit.Wherein, m
=c-a+k-1, k be more than a-b and less than a+b-c+1 arbitrary natural number.
S603：The low n position of described first multiplier and described second multiplier are made by multiplying by multiplication unit.Wherein, n
=a-k.
Can be by comparator, the high k position of the first multiplier to be compared with 0 in S601.
When described c is even number, the structure optimum of multiplication unit, area occupied during k=(2a-c)/2 or k=(2a-c)/2+1
Minimum.
When described c is odd number, during k=(2a-c+1)/2, the structure optimum of multiplication unit, area occupied are minimum.
The specific embodiment of any one multiplier device that can be provided using Fig. 1 to Fig. 5 of the present invention realizes the method.
The above is only the preferred embodiment of the present invention it is noted that ordinary skill people for the art
For member, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications also should
It is considered as protection scope of the present invention.
Claims (10)
1. a kind of multiplier device is it is characterised in that described device includes：Comparator, first selector, second selector and
Multiplication unit；
Described comparator is used for comparing the high k position of the first multiplier with 0, if unequal, sends the first control signal to the
One selector and second selector, if equal, send the second control signal to first selector and second selector；
The input data of the first input end of described first selector be the first multiplier, the second input of first selector defeated
Entering data is the second multiplier, and described first selector selects first input end as input after being used for receiving the first control signal
End, selects the second input as input, the input data of the input after selecting is led to after receiving the second control signal
Cross outfan to export to the 5th input of described multiplication unit；Wherein, the bit wide of described first multiplier is a, the second multiplier
Bit wide is b, and the maximum of the bit wide of the product of the first multiplier and the second multiplier is c, and (a+b) is more than c, and a is not less than b, and 2b is not
Less than c；
The input data of the 3rd input of described second selector is the low m-bit data of the second multiplier, the of second selector
The input data of four inputs is the low n-bit data of the first multiplier, and described second selector is used for receiving the first control signal
Select the 3rd input as input afterwards, select the 4th input as input after receiving the second control signal, will select
The input data of the input after selecting is exported by outfan to the 6th input of described multiplication unit；Wherein, m=c-a+k-
1 and n=a-k, k be more than a-b and less than a+b-c+1 arbitrary natural number；
Described multiplication unit is used for carrying out exporting after multiplying by the data of the 5th input and the 6th input, and the described 5th
The bit wide of input is a, and the bit wide of the 6th input is maximum number in m and n.
2. device according to claim 1 is it is characterised in that wherein,
When described c is odd number, k=(2a-c+1)/2, then the bit wide of described 6th input is (c-1)/2.
3. device according to claim 1 is it is characterised in that wherein,
When described c is even number, k=(2a-c)/2+1 or (2a-c)/2, then the bit wide of described 6th input is c/2-1.
4. the device according to claims 1 to 3 any one is it is characterised in that described device also includes：First deposits
Device, the second depositor and the 3rd depositor；
First multiplier is sent first defeated to first selector by described first depositor after being used for the first multiplier is deposited
Enter end, the low n-bit data of the first multiplier is sent the 4th input to second selector and the high k position by the first multiplier
Data is activation is to described comparator；
Described second depositor after being used for the second multiplier is deposited sends described second multiplier to described first selector
The second input and the low m-bit data of the second multiplier is sent to the 3rd input of second selector；
Described comparator be used for by the high k position of the first multiplier compare with 0 including：Described comparator is used for the first depositor is sent
The high k position of the first multiplier compare with 0；
Described multiplication unit is used for for the data of the 5th input and the 6th input carrying out output inclusion after multiplying：Described
Multiplication unit is used for carrying out exporting after multiplying to described 3rd depositor by the data of the 5th input and the 6th input；
Described 3rd depositor exports after being used for the data after described multiplication unit multiplying is deposited.
5. the device according to claims 1 to 3 any one is it is characterised in that described device also includes：4th deposits
Device, the 5th depositor, the 6th depositor and the 3rd depositor；
First multiplier is sent first defeated to first selector by described 4th depositor after being used for the first multiplier is deposited
Enter end and the low n-bit data of the first multiplier is sent to the 4th input of second selector；
Described 5th depositor after being used for the second multiplier is deposited sends described second multiplier to described first selector
The second input and the low m-bit data of the second multiplier is sent to the 3rd input of second selector；
Described comparator sends the first control signal and includes to first selector and second selector：
Described comparator sends the first control signal to the 6th depositor；
Described comparator sends the second control signal and includes to first selector and second selector：
Described comparator sends the second control signal to the 6th depositor；
The signal that described 6th depositor is used for that comparator is sent is deposited and the signal after depositing is respectively sent to the
One selector and second selector；
Described multiplication unit is used for for the data of the 5th input and the 6th input carrying out output inclusion after multiplying：Described
Multiplication unit is used for carrying out exporting after multiplying to described 3rd depositor by the data of the 5th input and the 6th input；
Described 3rd depositor exports after being used for the data after described multiplication unit multiplying is deposited.
6. the device according to claims 1 to 3 any one is it is characterised in that described device also includes：7th deposits
Device, the 8th depositor and the 3rd depositor；
Described first selector is used for exporting to described multiplication unit the input data of the input after selecting by outfan
The 5th input include：Described first selector be used for by select after input input data by outfan export to
7th depositor；
The data that 7th depositor is used for that first selector is sent is deposited and is taken advantage of the data is activation after depositing to described
5th input of method unit；
Described second selector is used for exporting to described multiplication unit the input data of the input after selecting by outfan
The 6th input include：Described second selector be used for by select after input input data by outfan export to
8th depositor；
The data that 8th depositor is used for that second selector is sent is deposited and is taken advantage of the data is activation after depositing to described
6th input of method unit；
Described multiplication unit is used for for the data of the 5th input and the 6th input carrying out output inclusion after multiplying：Described
Multiplication unit is used for carrying out exporting after multiplying to described 3rd depositor by the data of the 5th input and the 6th input；
Described 3rd depositor exports after being used for the data after described multiplication unit multiplying is deposited.
7. it is characterised in that the bit wide of the first multiplier is a, the bit wide of the second multiplier is b to a kind of method realizing multiplying,
The maximum of the bit wide of the product of the first multiplier and the second multiplier is c, and a+b is more than c, and a is not less than b, and 2b is not less than c, described
Method includes：
The high k position of the first multiplier is compared with 0, if unequal, by multiplication unit by the low m position of described second multiplier with
Described first multiplier makees multiplying, if equal, by described multiplication unit by the low n position of described first multiplier with described
Second multiplier makees multiplying；
Wherein, m=c-a+k-1 and n=a-k, k be more than a-b and less than a+b-c+1 arbitrary natural number.
8. method according to claim 7 is it is characterised in that wherein,
When described c is odd number, k=(2a-c+1)/2.
9. method according to claim 7 is it is characterised in that wherein,
When described c is even number, k=(2a-c)/2+1 or k=(2a-c)/2.
10. the method according to claim 7 to 9 any one is it is characterised in that the described high k position and 0 by the first multiplier
Relatively include：By comparator, the high k position of the first multiplier is compared with 0.
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| CN111381802B (en) * | 2018-12-28 | 2022-12-09 | 上海寒武纪信息科技有限公司 | Data comparator, data processing method, chip and electronic equipment |
| CN111258634B (en) * | 2018-11-30 | 2022-11-22 | 上海寒武纪信息科技有限公司 | Data selection device, data processing method, chip and electronic equipment |
| CN112286490B (en) * | 2020-11-11 | 2024-04-02 | 南京大学 | Hardware architecture and method for loop iteration multiply-add operation |
| CN113222132B (en) * | 2021-05-22 | 2023-04-18 | 上海阵量智能科技有限公司 | Multiplier, data processing method, chip, computer device and storage medium |
| CN116820387B (en) * | 2023-08-28 | 2023-12-01 | 深圳比特微电子科技有限公司 | Multiplier, multiply-accumulate circuit and convolution operation unit |
| CN117555515B (en) * | 2024-01-11 | 2024-04-02 | 成都市晶蓉微电子有限公司 | Digital ASIC serial-parallel combined multiplier for balancing performance and area |
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