JPS63303456A - Data transfer equipment - Google Patents

Abstract

PURPOSE:To generate manifold image data from a various kinds of bit constituted image element data, by performing a comparison processing in a bit unit which constitutes an image element. CONSTITUTION:A first selection circuit 18 selects and outputs either the data of a data register 12 or the data read out from a memory 21 and stored in a latch circuit 14. A comparator 19 obtains coincidence between the output of the circuit 18 and a color register 17 at every bit, and obtains the coincidence according to the bit constitution of the image element, and outputs (0) when all of the bits in the image element, and outputs (0) when all of the bits in the image element coincide, and outputs (1) in other cases. A second selection circuit 20 inputs the output of the latch circuit 14 and that of a computing element 15, and selects and outputs the output of the bit of the computing element corresponding to each case when the bit of each output of a mask register 16 and the comparator 19 shows (1), and selects and outputs the output of the bit of the latch circuit 14 corresponding to each case when neither shows (1).

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a data transfer device in a color display device that performs high-speed processing of converting the contents of a memory in units of pixels within a word in a memory that can be accessed only in units of words. It is related to.

2. Prior Art As a conventional data transfer device, for example, Japanese Patent Laid-Open No. 58-2
It is shown in Japanese Patent No. 41942.

FIG. 7 shows a configuration diagram of this conventional data transmission device, in which the original image 1 and original image 2 stored in the respective registers are connected to the background stored in the register designated for each original image. Two filters 7 that binarize based on the color 3 and the background color 4, an arithmetic circuit 9 that operates on the binary image 6 and the binary image 6 obtained in the registers, respectively, and the arithmetic circuit output data. a color restoration circuit 10 which combines the original images 1 and 2 using the
It is composed of a lot of things.

In the conventional data transfer device configured as described above, the filter 7 outputs "Q" when the data of the original images 1 and 2 match the background colors 3 and 4, and @11 when they do not match.
” and outputs binary images 6 and 6. Binary images 5 and 6 are input to the arithmetic circuit 9, which performs the arithmetic operation indicated by the arithmetic code 8 and outputs the result. In the color restoration circuit 10, according to the output of the arithmetic circuit 9, if it is "0", the original image 1
If it is "1", the pixel data of original image 2 is output.

Problems to be Solved by the Invention However, with the above configuration, it is not possible to convert the contents of the memory pixel by pixel, and therefore the image cannot be placed at an arbitrary position. Furthermore, since the bit configuration representing pixels is fixed, it is impossible to handle various types of image data. Furthermore, since two filters are used to binarize the original image, there is a problem in that the amount of hardware required is large.

In view of this, the present invention provides a data transfer device that transfers color data pixel by pixel, handles pixel data with various bit configurations, generates a variety of image data, and realizes high-speed deco transmission with less hardware. The purpose is to

Means to solve the problem A data register that holds the transfer source data, an address register that holds the transfer destination address where the above data should be stored, and a latch that holds the contents of the memory at the address indicated by the above address register. a circuit, an arithmetic unit that inputs the output of the data register and the output of the latch circuit, and performs a desired operation between the input data; and 11, which indicates that the operation result of the arithmetic unit is valid, and which bits are invalid. ``o''
a mask register shown by , a color register that stores color data specifying the color of a pixel, and a first input that inputs the outputs of the data register and the latch circuit and outputs the contents of any of them.
The output of the first selection circuit and the contents of the color register are inputted and compared bit by bit, and if all the results corresponding to the bit data constituting the pixel match, the bit indicating the pixel is selected. A comparator that outputs all data as "0" and all pit data indicating pixels as "1" in other cases, the output of the Joetsu operator, and the output of the launch circuit described above are input, and the mask register and the above are compared. Bits whose contents are both 1-1 output the input from the arithmetic unit and write to the memory indicated by the address register, and other bits output the contents of the latch circuit and write to the memory indicated by the address register. This data transfer device includes a second selection circuit for writing.

According to the above-described configuration, the present invention uses a computing unit to perform a desired operation between the contents of the data register that holds the data of the transfer source and the latch circuit that holds the data at the address indicated by the address register, and calculates the result. Output.

In addition, the contents of either the data register or the latch circuit are selected by the first selection circuit, and the data and the contents of the color register are compared bit by bit in a comparator, and the result corresponding to the pit data constituting the pixel is obtained. If they all match, all "0" is output as bit data indicating the pixel, and in other cases, all "1" is output as the bit data indicating the pixel. Set the bit that indicates that the calculation result of the above calculation unit is valid to “1”
Then, input the data set in the mask register with k "0" and the output of the above comparator to the second selection circuit, and input the bit of "both data is 1-1" into the above arithmetic unit. In other cases, the contents of the launch circuit are output and written to the memory address indicated by the address register.

The data set in the above mask register allows data to be converted pixel by pixel from memory accessed in word units, and when configuring pixels, data transfer can be performed at high speed according to the data code without much effort. This can be achieved with software.

Embodiment FIG. 1 shows a block diagram of a data transfer device in an embodiment of the present invention. In this embodiment, the unit of data handled is 16 pit data, and one pixel data is expressed with 4 bits.

In FIG. 1, 12 is a data register that stores transfer source data, 13 is an address register that holds a transfer destination address, 14 is a latch circuit that holds the contents of the memory indicated by the address register 13, and 15 is a data register 12.
An arithmetic unit 16 performs a desired operation between the contents of the arithmetic unit 15 and the contents of the latte circuit 14;
1” is invalid: 1- This is a mask register that stores OJ.

Reference numeral 17 denotes a color register that stores color data that specifies the color of a pixel. In this embodiment, one pixel is expressed as 4-pit data, and as shown in Figure 4, four sets of the same 4-pit data are stored in the color register. Store. A first selection circuit 18 selects and outputs either the data register 12 or the latch circuit 14. Reference numeral 19 inputs the outputs of the color register 17 and the first selection circuit 18, matches each bit, and sets all bits indicating the pixel to "0" according to the bit configuration of the pixel. ”, and in other cases, it is a comparator that outputs all bits indicating pixels as “1”. 2o inputs the output of the latch circuit 14 and the output of the arithmetic unit 16, and when the output bit of each of the mask register 16 and the comparator 19 is "1", selects the output of the corresponding bit of the arithmetic unit 15. If each bit is not 1-1, the second selection circuit selects and outputs the output of the corresponding bit of the latch circuit 14. 21/i memory, 22 is an address register 13.
Mask register 16. A calculation unit that changes the contents of the data register 12 and the color register 17; 22 is the first selection circuit 1;
A signal indicating which of the 8 inputs to select, and the arithmetic unit 15
This is a control unit that outputs a signal indicating the type of calculation to be performed by the comparator 19 and a signal indicating the bit length of the pixel to be compared by the comparator 19.

FIG. 2 shows a CMO8 circuit diagram of the comparator 19 in this embodiment. In FIG. 2, 24 is an XNO whose inputs are the output of the first selection circuit 18 and the output of the color register.
R circuit, 25 is a first NAND circuit 26 is a NOR circuit,
27 is an inverter circuit, 28 is a P-channel transistor, and 29 is an N-channel transistor.

FIG. 3 shows a circuit diagram of the second selection circuit 20 in this embodiment. 3o is a second NAND circuit which receives the output of the mask register 16 and the output of the comparator 19;
1 is the third NAND circuit whose inputs are the output of the NAND circuit 3o and the output of the latch circuit 14, and 32 is the third NAND circuit whose inputs are the output of the mask register 16, the output of the comparator 19, and the output of the arithmetic unit 15. 3 human powered NAND circuit, 33 is the output of the second NAND circuit 31 and the 3 human powered NAND circuit 32
This is a fourth NAND circuit that inputs the output of the .

The operation of the data transfer apparatus of this embodiment configured as described above will be described below with reference to FIG.

Prior to data transfer, the transfer source data is processed by the calculation unit 32 as 4ii! ji element (39 colors, 11 colors, 21 colors 1) data is stored in the data register 12, and the color data of the pixels is stored in the color register 17 as 4 pixels (color 19 color 1, color 19 color 1), In the 0 data transfer in which X'OF Color 3° Color 49 Color 19 Color 2) Reading Latch Circuit 14
Store in.

The arithmetic unit 15 performs the arithmetic operation indicated by the control unit 23 between the data in the data register 12 and the data in the latch circuit 14, and the result of the arithmetic unit 15 is 4 pixel data (59 colors, 69 colors).
0 output as color 71 color 7) The control unit 23 controls the first selection circuit 18 and the data register 12.
When selecting the contents of color register 17 and ratio! Articulator 19
The output of the comparator 19 becomes the output 1 of the comparator 19 in FIG. In the second selection circuit 20, based on the contents of the mask register 16 and the output of the comparator 19, the arithmetic unit 15
Either the output of the latch circuit 14 or the output of the latch circuit 14 is selected and output, resulting in output 1 of the second selection circuit 20 in FIG. In this case, the output of the comparator 19 is "1" and the mask register 1
For bits whose contents are "1", the results of the arithmetic unit 15 are output, and for the other bits, the contents of the latch circuit 14 are output.

When the control unit 23 selects the contents of the latch circuit 14 with the first selection circuit 18, the content of the latch circuit 14 is compared with the color register 1 in the comparator 19, and the output of the comparator 19 is the output 2 of the comparator 19 in FIG.
becomes.

The second selection circuit 20 selects and outputs either the output of the arithmetic unit 15 or the output of the latch circuit 14 based on the contents of the mask register 16 and the output of the comparator 19, and selects and outputs either the output of the arithmetic unit 15 or the output of the latch circuit 14. This becomes output 2 of circuit 2o. In this case, the output of the comparator 19 is "1" and the contents of the mask register 16 are "1".
”, the result of the arithmetic unit 15 is outputted,
For other bits, the contents of the latch circuit 14 are output.

It is created by the operations shown above. @2 selection circuit 20
The output 1 or 2 of is written to the memory address indicated by the address register 13, and one data transfer is completed.

The operation of the comparator 19 of this embodiment shown in FIG. 2 will be explained below.

Since one pixel is represented by 4 bits in the explanation of this embodiment, the signal 11PP4J is activated by the control section 23. We will look at the lower 4 bits below.

In the XNOR circuit 24, the 16 pins of the output of the first selection circuit 18 and the 15 bits of the output of the color register 17 are input, and if they match, it outputs "1" gold, and if they do not match, it outputs "1-0". . Similarly, the output of the XNOR circuit 24 for 14°13.12 bits is obtained. 14. Each of the outputs of the 15-bit XNOR circuit 24 is input to the NAND circuit 26. Similarly, 12 and 13 bit XNO
The outputs of the R circuits 24 are input to NAND circuits 26, respectively. Output 1 of the above two NAND circuits 26 NOR circuit 2
Enter into 6. The output of the NOR circuit 26 is 1-EPP4J
The signal is input to the other two N-channel transistors arranged in series of the N-channel transistor 29 to which the signal is input. When the first selection circuit 18 and the color register 17 match for all 12, 13, 14.15 bits, the output of the comparator 19 is CM12°CMj3, 0M14
, CMls bits are all “○”, 12, 13
, 14.15 bits, the first selection circuit 1
8 and the color register 17 do not match, the bits of the output CM12 of the comparator 19, 0M13, 0M14, and CMles are all 1-1. The above operation is similarly performed for bits 0 to 11.

The operation of the second selection circuit 2° of this embodiment shown in FIG. 3 will be explained below.

The second selection circuit 2o inputs the output of the latch circuit 14 and the output of the arithmetic unit 16, and inputs the mask register 16 and the comparator 19.
When both bits are "1", the signal is input to the three-man NAND circuit 32 and passed through the fourth NAND circuit 33.
The corresponding bit of the arithmetic unit 19 is output. When both the mask register 1θ and the comparator 190 bits are not "1", the output of the second NAND circuit 30 becomes active, and the output of the third NAND circuit 31. The corresponding pin of the latch circuit 14 is output through the fourth NAND circuit 33.

According to the operation of this embodiment, when the first selection circuit 18 selects the contents of the data register 12 and obtains the output 1 of the second selection circuit 20 shown in FIG. 6, the image data 1 shown in FIG. generate. Furthermore, when selecting the contents of the 2L relaunch circuit 14 in the first selection circuit 18 and obtaining the output 2 of the second selection circuit 2o in FIG. 6, the image data 2 shown in FIG.
generate.

However, the operation of the arithmetic unit 15 is assumed to be a write operation of the transfer source data. Also, the color data of the pixel in the color register 17 is “color 1”.
”.

As described above, according to this embodiment, color data is transmitted pixel by pixel, pixel data of the bit configuration of each crosspiece is handled, and various image data are generated, and data transmission can be completely eliminated at high speed with less hardware. .

Effects of Investigation As explained above, according to the present invention, color data is transferred pixel by pixel to a memory that is accessed only in word units, and pixel data with various bit configurations are handled to generate a variety of image data. However, high-speed data transmission can be achieved with less hardware, and its practical effects are significant.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data transfer device according to an embodiment of the present invention, and FIG. 2 is a comparator 19 of the data transfer device according to the embodiment.
3 is a circuit diagram of the second selection circuit 2o of the data transmission device of the embodiment. FIG. 4 is an explanatory diagram of data stored in the color register 17 of the data transmission device of the embodiment. FIG. 5 is an explanatory diagram of processing in the data transfer device of the embodiment, FIG. 6 is an explanatory diagram of image data generated by data transfer by the data transfer device of the embodiment, and FIG. 7 is a configuration diagram of a conventional data transmission device. It is. 1.2... Original image, 3, 4... Background color, 5, 6... Binary image IJ+, r... Filter, 8... ...Arithmetic code, 9...Arithmetic circuit, 1o...Color restoration circuit, 11...
Composite image, 12... Data register, 13...
...Address register, 14...Latch circuit,
15... Arithmetic unit, 16... Mask register, 17... Color register, 18...
First selection circuit, 19... Comparator, 20...
...Second selection circuit, 21...--Memory, 22
...Calculating section, 23...Control section, 24...
...XNOR circuit °, 25, 30, 31. 33
...NAND circuit, 26...NOR circuit, 27... Inverter circuit, 28...P channel transistor, 29...N channel transistor, 32...・Three-person NAND circuit. . Name of agent: Patent attorney Toshio Nakao and 1 other person No. 3
Figure 4 Figure 5 Figure 6 Source image≠-evening destination image≠-ta climbing≠-evening

Claims (1)

[Claims] A data register that holds the transfer source data, an address register that holds the transfer destination address where the data should be stored, a latch circuit that holds the contents of the memory at the address indicated by the address register, and the output of the data register. and an arithmetic unit that performs a desired operation between input data using the output of the latch circuit as input, and a bit where the arithmetic result of the arithmetic unit is valid is set to "1", and a bit where it is invalid is set to "0".
a mask register shown by , a color register that stores color data specifying the color of a pixel, and a first input that inputs the outputs of the data register and the latch circuit and outputs the contents of any of them.
The output of the selection circuit, the output of the first selection circuit, and the contents of the color register are input and compared bit by bit, and if all the results corresponding to the bit data constituting the pixel match, the bit data indicating the pixel is input. A comparator that outputs all bit data indicating pixels as "0" and "1" in other cases, and a comparator that inputs the output of the arithmetic unit and the output of the latch circuit, and outputs the mask register and the comparator. Bits whose contents are both "1" output the input from the arithmetic unit and write to the memory indicated by the address register, and other bits output the contents of the latch circuit and write to the memory indicated by the address register. 1. A data transfer device comprising: 2 selection circuits.