JPS63302602A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS63302602A
JPS63302602A JP13848287A JP13848287A JPS63302602A JP S63302602 A JPS63302602 A JP S63302602A JP 13848287 A JP13848287 A JP 13848287A JP 13848287 A JP13848287 A JP 13848287A JP S63302602 A JPS63302602 A JP S63302602A
Authority
JP
Japan
Prior art keywords
line
semiconductor device
signal
power
high frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13848287A
Other languages
Japanese (ja)
Inventor
Susumu Sakamoto
進 阪本
Koji Fujioka
藤岡 孝司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP13848287A priority Critical patent/JPS63302602A/en
Publication of JPS63302602A publication Critical patent/JPS63302602A/en
Pending legal-status Critical Current

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  • Microwave Amplifiers (AREA)

Abstract

PURPOSE:To operate a semiconductor device with the optimum characteristic, by blocking a high frequency component by a signal line which becomes the path of a high frequency signal and a power line, and connecting them via a communication line with prescribed length which passes A power source power. CONSTITUTION:At the input side of a high frequency semiconductor device formed with a case 1, a semiconductor chip 2, matching substrates 4 and 5, and metallic conductors 6 and 7, and the power line 15 is formed on a line substrate 8 with the signal line 10. The line 15 is formed in a shape of horizontal L that the communication line 15a with the prescribed length is communicated with the side part of the line 10 orthogonally, and is formed with a gold pattern, etc., simultaneously with the line 10. Also, at the tip part of the line 15 at a side opposite to the line 15a, a power source lead 16 made of gold plating, etc., is arranged in parallel with a signal lead 12, and is joined with soldering of the gold or a tin. Furthermore, the line 15a is grounded via a chip capacitor 19 arranged adjacently with the substrate 8 by a metallic fine line 3. Also, the output side of the device is constituted similarly. In such a way, it is possible to operate the semiconductor device with the optimum kinesis.

Description

【発明の詳細な説明】 〔産業上の利用分野] この発明は、内部に整合回路を備えた半導体装置に胸す
るものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device having an internal matching circuit.

〔従来の技術〕[Conventional technology]

バイポーラ・トランジスタ、電界効果トランジスタ等の
超高8波高出力半専体素子は、素子イン。
Ultra-high 8-wave high output semi-dedicated devices such as bipolar transistors and field effect transistors are device-in.

ビーダンスが非常に低く、素子同体の持つ広帯域高出力
特性を発揮させる広帯域整合を実現するには、l!$遊
谷濾やインダクタンス等の不要要素の介在を避けるため
に、OJ能な限り素子自体に近接させてインピーダンス
整合回路を置ける必要がある。
l! In order to avoid the intervention of unnecessary elements such as $Yuya filter and inductance, it is necessary to place the impedance matching circuit as close to the element itself as possible.

このため、超繻周反尚出力トランジスタにおいては、容
器内にインピーダンス整合回路を内蔵させた。いわゆる
内部整合型半導体装置が実現されている。
For this reason, in the ultra-striped output transistor, an impedance matching circuit is built into the container. A so-called internally matched semiconductor device has been realized.

この種の内部整合型半導体装置を、−例とし。Take this type of internally matched semiconductor device as an example.

第5図に平面図を示すものについて説明する。回内にお
いて、(υは銅に金メッキ等からなる良萼伝性の企−辱
体基体となるソース、(2)はこのケース(1)上に企
・錫のはんだ等で接合される、例えばガリクム・ヒ素電
界効果トランジスタ(GaAaF]ET )の半導体チ
ップで、N型のガリクム・ヒ素化合物半導体基板の一王
面にトランジスタ素子が形成され、そのソース部と上記
ケース(1)とが金員細線(3)により電気的に接続さ
れている。(4)および(FD)は上記半導体チップ(
2)の両側に各々隣接配置されて上記ケース(1)上に
金・錫のはんだ等で接合される入力側および出力側の整
合基板で、高誘電率を有する絶縁体上に金等の4体(6
)および(7)が形成され。
The plan view shown in FIG. 5 will be explained. In the pronation, (υ is a source that is a good calyx-conducting material base made of copper plated with gold, etc., and (2) is a material that is bonded to this case (1) with a material such as tin solder. For example, In a semiconductor chip of a gallium arsenide field effect transistor (GaAaF]ET), a transistor element is formed on one side of an N-type gallium arsenide compound semiconductor substrate, and the source part and the case (1) are connected to a thin metal wire. (3) is electrically connected. (4) and (FD) are the semiconductor chip (
2) Input side and output side matching substrates are placed adjacent to each other on both sides of the case (1) and are bonded to the case (1) using gold/tin solder. Body (6
) and (7) are formed.

これら導体(6L(ηと上記半導体チップ(2)のゲー
ト、ドレイン部とが金属細線(3)Kより電気的に接続
されている。ソース(1)、半導体チップ<2〕%整合
基板<4)e (5) 、 91合基板上の金に4尋俸
(6J @ (7)で高周波半寄体累子が形成される。
These conductors (6L(η) and the gate and drain parts of the semiconductor chip (2) are electrically connected by a thin metal wire (3)K. Source (1), semiconductor chip <2]% matching substrate <4 ) e (5), a high frequency semiparasitic crystal is formed on the gold on the 91 ply substrate with 4 fathoms (6J @ (7)).

(8Jお工び(9)は上記整合基板(4)および(5)
に隣接し、上記半導体チップ(2〕の反対側に配設され
て上記ケース(1)上に接合される入力側および出力側
の線路基板で、アルミナ・セラミック等の絶縁体の王表
rkJK真空蒸着法による金パターン等の信号伝送用と
なる信号線路(10)および(11)が形成されており
、各々、その一方に上記整合基板(4)および(5)上
の上記得体(6)お工び(7)と電気的に接続される金
属細線(3)が接合され、他方に銅に金メッキ等で形成
されて外部との電気接続用となる入力側および出力側の
侶ちり一ド(12)および(13)が接合されている。
(8J work (9) is the above matching board (4) and (5)
The input and output side line boards are adjacent to the semiconductor chip (2) and are connected to the case (1) on the opposite side of the semiconductor chip (2), and are made of an insulator such as alumina or ceramic. Signal lines (10) and (11) for transmitting signals such as gold patterns by vapor deposition are formed, and one of the signal lines (10) and (11) is formed with the above-mentioned bodies (6) and (6) on the above-mentioned matching substrates (4) and (5), respectively. A thin metal wire (3) that is electrically connected to the workpiece (7) is bonded to the other, and a metal wire (3) on the input and output sides is formed of copper plated with gold, etc., and is used for electrical connection with the outside. 12) and (13) are joined.

(14)は上記ケース(1)の上面突@ (la)に企
・錫の扛んだ等で接合されてその内部を気密封止させる
キャップで、銅に金メッキ等で形成されている。
(14) is a cap that is joined to the upper surface protrusion (la) of the case (1) with a tin plate or the like to hermetically seal the inside thereof, and is made of copper plated with gold or the like.

ところで、上記半導体装置に有する内部整合回路tit
%上記企絢細線(3)のインダクタンスと絶縁体の高誘
電率を利用したキャパシタンスとカラi iされるもの
である。
By the way, the internal matching circuit included in the semiconductor device
% It is different from the capacitance using the inductance of the above-mentioned thin wire (3) and the high dielectric constant of the insulator.

このように構成される半導体装置は、986図にその等
両回路図を示す如く、信号リード(12) (13)か
、上記半導体装置の外部に各に設けられた入力側、出力
側の外H偵′13S路と接続され、また、これら外部信
号線路に、さらに各々別に設けられたIILII!iK
供給用のtk源回路から伸Fcされる外部電源線路が接
続されて用いられるものである。それら外部における信
号@路と1@源線路とは、上記外部信号線路に影響を及
ぼさない特性に形成された上記外部−源線路に有する線
路部が上記外部信9線路に接続されるat灰になされて
いる。
The semiconductor device configured in this manner has signal leads (12) and (13), or external terminals on the input and output sides provided outside the semiconductor device, as shown in the circuit diagram in Figure 986. IILII! is connected to the H-13S path, and each of these external signal lines is further provided separately. iK
It is used by connecting an external power supply line extending Fc from a tk source circuit for supply. The external signal @ line and 1 @ source line are connected to the external signal line where the line portion of the external-source line is connected to the external signal line 9, which is formed to have a characteristic that does not affect the external signal line. being done.

また、この檀の1例えばマイクa&帯で動作する半導体
装置は、一般に、他装置間あるいは他回路間が特性イン
ピータンス50Ω(オーム)の線路で接続されるもので
、これら線路の特性に合せて恢袷−力が進行波となって
負荷に向かって進み、反射波となって反らないような最
適状態で働かせるために、上記半導体kli[の入出力
側にインピーダンス整合411!能が設けられている。
In addition, in general, semiconductor devices that operate in the microphone A & band, for example, are connected between other devices or other circuits by lines with a characteristic impedance of 50Ω (ohms), and the characteristics of these lines are adjusted. In order to operate in an optimal state where the force becomes a traveling wave toward the load and does not become a reflected wave and warp, impedance matching 411! is applied to the input and output sides of the semiconductor kli[! Noh is provided.

ところで、上記のように構成される半導体装置は、次の
ように動作される。すなわち、外st電源路より所定電
圧が供給され、各々入力側、出力側に配役された外部電
源線路から外部信号線路を経て半導体チップ(2)のド
レインに正電圧、ゲートに負電圧が4」加される。また
1例えばマイクa波借りが入力側の外部信号線路から信
5リード(12)、41ち線路(lO)を姪で、金14
細線(力と整合基板(4)とでインピーダンス整合され
て上記半導体チップ(2)に伝送される。そして、例え
ば増幅されたマイクaf信8扛、出力側の金属細線(3
)と整合基板(5)とでインピーダンス整合され、信号
線路(11) 、信号リード(13)を経て出力側に配
設された外部信号線路に伝送されるものである。
By the way, the semiconductor device configured as described above is operated as follows. That is, a predetermined voltage is supplied from the external power supply line, and a positive voltage is applied to the drain of the semiconductor chip (2) and a negative voltage is applied to the gate of the semiconductor chip (2) from the external power supply lines arranged on the input side and the output side, respectively, through the external signal line. added. In addition, for example, if the microphone A wave is borrowed from the external signal line on the input side, connect the signal 5 lead (12) and the 41 line (lO) to the gold 14
The impedance is matched with the thin wire (force) and the matching board (4) and transmitted to the semiconductor chip (2). Then, for example, the amplified microphone AF signal 8 and the thin metal wire (3) on the output side are connected.
) and a matching board (5), and the signal is transmitted to an external signal line disposed on the output side via a signal line (11) and a signal lead (13).

〔発明が解決しよりとする問題点」 従来の半導体装置は以上のように構成され、上紀牛専体
装置の4R5j’J−ド(12) (13)が、外部に
配設される外部信91%lIi回路に接続されるもので
、上記外部信9線路が伯ち伝送用となるとともに電源供
給用の線路となっている。従って、上記外部信9線路に
接続される外部電源線路は、目的の8波敗帯域で、上記
外部信5線路の特性インピーダンスに愼力影響を及ぼさ
ない特性に形成されたものでなければならない。しかる
に、上記外部亀源i賂は、形成精度等に起因する特性変
動を有するものであり、上記外部信9線路はその影響を
受けて特性インピーダンスか変化してしまうという問題
点がめった◎ この発明は、上記のような問題点を解消するためになさ
れたものでlet適な特性になされて動作上れる高信頼
の半導体装置を得ることt−目的とする。
[Problems to be Solved by the Invention] The conventional semiconductor device is constructed as described above, and the 4R5j'J-do (12) (13) of the Jokigyu proprietary device is It is connected to the 91% IIi circuit, and the 9 external signal lines are used for transmission as well as for supplying power. Therefore, the external power supply line connected to the 9 external signal lines must be formed to have a characteristic that does not affect the characteristic impedance of the 5 external signal lines in the target 8 wave loss band. However, the above-mentioned external transmitter has characteristic fluctuations due to formation precision, etc., and the above-mentioned 9 external transmission lines rarely have a problem in that the characteristic impedance changes due to the influence.◎ This invention This was done to solve the above-mentioned problems, and the purpose is to obtain a highly reliable semiconductor device with suitable characteristics and improved operation.

〔問題点を解決するための手段] この発明に係る半導体装置Iri、高周波半導体素子と
外部回路とが接続されて高尚波信号の通路となる信号線
路と、上記高周波半等体素子に電源を供給する電源線路
とを備えるとともに、これら両者か高尚波成分は阻止し
、かつ電源電力に通過させる所定の長さの連絡線路を介
して接続される構成になされたものである。
[Means for Solving the Problems] A semiconductor device Iri according to the present invention supplies power to a signal line to which a high frequency semiconductor element and an external circuit are connected and which serves as a path for a high frequency signal, and to the high frequency semi-isomorphic element. In addition, both of these are connected via a connecting line of a predetermined length that blocks high-frequency components and allows the power source power to pass through.

〔作用J この発明における半導体装置は、信号線路とともKik
!線路を有し、まな、これら両者を接続させる連絡線路
は所定の特性に形成されて、上記信号線路が上記電源線
路によって%その特性インピーダンスに影響を受けるこ
ともなく、高信頼の信号伝送が行われる機能を有する。
[Function J] The semiconductor device according to the present invention has a signal line as well as a Kik
! The communication line that connects the two is formed to have predetermined characteristics, and the signal line is not affected by the characteristic impedance of the power supply line, allowing highly reliable signal transmission. It has the function of

〔発明の実施例」 この発明の一実施例を図について説明する。なお、従来
の技術の説明と重飯する部分は、適宜その説明を省略す
る。第1図はこの発明の一実施例を示す平面図であり、
同図が第5図に示すものと異なる点は以下の点である。
[Embodiment of the Invention] An embodiment of the invention will be described with reference to the drawings. It should be noted that the explanation of parts that overlap with the explanation of the conventional technology will be omitted as appropriate. FIG. 1 is a plan view showing an embodiment of the present invention.
This diagram differs from that shown in FIG. 5 in the following points.

すなわち、まず、クース(1)、半導体チップ(2)、
整合基板(4L(5)、金属等体(6L (7)で形成
される高8波半萼体素子の入力側において、称路基板(
8)上に信18線路(lO)とともKi&!源1路(1
5)が形成されているもので、この電源線路(15)は
、線路長11の連絡線路(15a)が上記信ら線路(l
O)の両部に直角に連接された横り字形状を有し、 上記信号線路(lO)と同時に真空蒸着法にょる企パタ
ーン等で形成される。また、上記連給N路(15a)と
反対側の上記電源線1M (15)の先端部には、銅に
金メッキ等からなる電源リード(16)が信号リ−F 
(12)と平行に配設されて、金・錫のはんだ等で接合
されて込る。さらに、上記連絡線%(15a)は、金端
細線(3)に工す上記線路基板(8)に−振して配設δ
nたチンフコンデン4P″(19)と電気的に接に;!
れ、高周波的に接地される構成を有している。
That is, first, Koos (1), semiconductor chip (2),
On the input side of the high 8-wave half-calyx element formed of a matching substrate (4L (5) and a metal body (6L (7)), a matching substrate (
8) Ki&! with signal 18 line (lO) on top! source 1 route (1
5) is formed, and this power supply line (15) has a connecting line (15a) with a line length of 11 connected to the above-mentioned power line (l).
It has a horizontal shape connected at right angles to both parts of the signal line (IO), and is formed in a planned pattern using a vacuum evaporation method at the same time as the signal line (IO). Further, a power lead (16) made of copper plated with gold or the like is attached to the tip of the power line 1M (15) on the opposite side to the continuous feed N path (15a).
It is arranged parallel to (12) and joined with gold/tin solder. Furthermore, the connecting wire % (15a) is arranged by δ
Electrically connected to the 4P''(19);!
It has a configuration in which it is grounded at high frequencies.

次に、上記高鞠波半導体素子の出力側において、上記入
力側におけると同様な構成になされ、かつ、上記半導体
チップ(2) kc qして対称状の構造を有するもの
である。
Next, the output side of the high frequency semiconductor element has the same configuration as the input side, and has a symmetrical structure as the semiconductor chip (2).

ところで、上記のように構成される半導体装置は、ドレ
インに印加される止−圧が出力側Vこある電源リード(
L8)工り、またゲートに印加される負電圧が入力側に
ある電源リード(16>より各々供給され、さらに、例
えばマイクロi信号が入力側の信号り一ド(L2)から
入力されると、この信8Fi信55線路(10)を経て
金属細線(3)と整合基板(4)とでインピーダンス整
合されて半導体チップ(2)に伝送される。そして1例
えば増幅され九マイクarL信号は、出力側の企jI1
4縄線(3)と盛合基板(5)とでインピーダンス整合
され、信5線路(ti)を経て出力側の信号リード(1
3)より外部に伝送されるものである◎さて、上記半導
体装置に2いて、ここでま丁。
By the way, the semiconductor device configured as described above has a power supply lead (
L8), and the negative voltage applied to the gate is supplied from the power supply lead (16) on the input side, and furthermore, for example, when the micro i signal is input from the signal lead (L2) on the input side. The signal is impedance matched by the thin metal wire (3) and the matching substrate (4) and transmitted to the semiconductor chip (2) via the 8 Fi signal 55 line (10).Then, for example, the amplified 9 microphone arL signal is transmitted to the semiconductor chip (2). Output side plan jI1
The impedance is matched between the 4 rope wires (3) and the multilayer board (5), and the output side signal lead (1) is passed through the 5 signal lines (ti).
3) It is transmitted to the outside. ◎Now, let's talk about the above semiconductor device.

入力側にある線路長t1の分布定政憎路の上記連絡線路
(15)における電圧、電流、人力インピーダンスにつ
いてみると、第2凶に等価回路を示す如く、受端に負荷
インピーダンスZRが接続きれた受端短析の場合として
表わされ、受端から送端側に回って任意点j Kおける
上記6値は、次の一般式で末められる。すなわら、 ■!=マHcosβ/+JRc工Hsin/l    
              −(1)なお、 Rc:
線路の特性抵抗tVR’受端における電圧、工R:受端
における電流、λ:波長、β:N路の位相定数である。
Looking at the voltage, current, and human power impedance in the connection line (15) of the distribution line with line length t1 on the input side, the second problem is that the load impedance ZR is not connected to the receiving end, as shown in the equivalent circuit. The above six values at an arbitrary point jK going from the receiving end to the sending end can be concluded by the following general formula. In other words, ■! =Ma Hcosβ/+JRc Engineering Hsin/l
-(1) In addition, Rc:
The characteristic resistance of the line tVR' is the voltage at the receiving end, R is the current at the receiving end, λ is the wavelength, and β is the phase constant of the N path.

ここで、受端短絡であることからs ZR” ’ sま
たvR=oとなり、上記(3)式にこれらを代入すると
Here, since the receiving end is short-circuited, s ZR'' s and vR=o, and when these are substituted into the above equation (3).

Zl= JRctanβt             
 −(5)が得られる。そして、任意点l=λ/41に
上記(lバ2)(4J (5)式に代入すると次表の結
果となる。
Zl= JRctanβt
-(5) is obtained. Then, by substituting the arbitrary point l=λ/41 into the above equation (lbar2)(4J (5)), the results shown in the following table are obtained.

表1 すなわち、上表よりl=λ/4の点では、入力インピー
ダンスZ/が無限大(理論上)となって見かけ上亀圧V
/=ROよりが印加されているのみの状態が得られる。
Table 1 In other words, from the above table, at the point l = λ/4, the input impedance Z/ becomes infinite (theoretically), and the apparent tortoise pressure V
/=A state in which only RO is applied is obtained.

そこで、上記−実施例のものを、第3図に等師回路を示
す如く、上記信号線路(10)に接続される上記連絡線
路(15a)が、線路長11をλ/4で、かつ高インピ
ーダンスの線路に形成されれば上記と同様の状態が得ら
れる。従って、上記借り線路(lO)と上記連iP&保
路(15a)との連接部では、高同波的に終端が開放さ
れたものとなり、上記借り線路(10) kCオケル”
イクロ波インピーダンスに影響シないものとなる。
Therefore, in the above-mentioned embodiment, as shown in FIG. 3, the connection line (15a) connected to the signal line (10) has a line length 11 of λ/4 and a high If it is formed in an impedance line, the same state as above can be obtained. Therefore, at the connecting part between the borrowed line (10) and the connected iP & protection line (15a), the termination is open in terms of high frequency, and the above borrowed line (10) kC Okel"
It has no effect on microwave impedance.

次に、上記出力側において、上記入力側におけると同様
に考えられ、上記借ち線路(11)に接続される上記連
絡線Wz (17a)ti、線路長12がλ/4の高イ
ンピーダンス線路に形成されて構成されるものであり、
上記と同様に動作されるものである。
Next, on the output side, the connection line Wz (17a)ti connected to the borrowed line (11) is considered to be the same as on the input side, and the line length 12 is a high impedance line of λ/4. formed and constituted,
It operates in the same way as above.

なお、上記連絡線路(15a) (17a)は、線路長
が(2n+1)・λ/4.(n=1,2・・・の整数)
としても上記と同様の効果を有する。
The connecting lines (15a) and (17a) have line lengths of (2n+1)·λ/4. (n = integer of 1, 2...)
It has the same effect as above.

このように、信9線路(10) (11)が形成される
線路基板(8) (9)上に所定特性の連絡線路(15
a) (17a)を有する電源線路−(15) (17
)をともに、設は九半瑯体装置としたので、外部回路又
#i装Aに直接接続させるだけで超高周波側らに影響を
及はすことなく電源供給されて動作し、しかも上記信号
線路(10) (11)と上記電源線路(15) (1
7)とが同時に、かつ高精度に形成されたものが得られ
るため、信頼性の高いものとなる。ま念、上記半導体装
置は、それ自体の寸法を大きくすることなく、内部に上
記借”141[(10) (11) 、!= 七4 K
上Etin源1fl路(15) (17)カ形成される
ため、外部における電源供給用の長い線路が不要となっ
て、上記半導体装置が搭載される装置の小型化がはから
れる効果も期待できる。
In this way, the communication lines (15) having predetermined characteristics are formed on the line substrates (8) (9) on which the nine signal lines (10) (11) are formed.
a) Power line with (17a) - (15) (17
), both of them are installed in a nine-piece device, so just by connecting them directly to the external circuit or #i equipment A, they can be powered and operated without affecting the ultra-high frequency side, and the above signals can be operated. Lines (10) (11) and the power line (15) (1)
7) can be formed at the same time and with high precision, resulting in a highly reliable product. Please note that the above semiconductor device has the above-mentioned capacity inside it without increasing its dimensions.
Since the upper Etin source 1fl path (15) (17) is formed, there is no need for a long line for external power supply, and it is expected that the device in which the above semiconductor device is mounted can be miniaturized. .

ところで、上記と他の’f<k例として、第4図にキャ
リア型の半導体装置の斜視図を示す如く、所定特性を存
する絶縁体からなる基板(22) (23)上に整合n
 (24) (25)と線路i (26) (27)と
がともに形成され、全1ii4J!1体基体となる良導
仮性のベース(21)上に配設されたものとすれば、さ
らに部品数が削減されて収扱いが容易となる等のほか、
余分なスペースが削除されたものとなって半導体装置自
体がさらrc小梨化できるものとなる。
By the way, as an example of the above and other f<k, as shown in FIG. 4, which is a perspective view of a carrier type semiconductor device, a matching n
(24) (25) and line i (26) (27) are formed together, totaling 1ii4J! If it is arranged on a temporary base (21) with good conductivity, which serves as a single body, the number of parts will be further reduced, making it easier to handle, etc.
With the extra space removed, the semiconductor device itself can be further converted into an RC model.

なお、上記一実施例の説明において、半導体チップ(2
)rま、ガリクム・し素電界効果トランシスタノモノを
示したが、インジクム・リン等の他の化合物半導体基板
を用いた電界効果トランジスタやバイポーラ・トランジ
スタ等であっても良い。
Note that in the description of the above embodiment, the semiconductor chip (2
) Although a gallium phosphorus field effect transistor is shown, a field effect transistor or a bipolar transistor using another compound semiconductor substrate such as indicium phosphorus may also be used.

また、金属4体基体(1)は、キャリア型(キャップな
し)やキャンプ付のものに限定されるものではなく、そ
れらのいずれであっても良く、チップのマクント方式(
アップサイドアンプ又はアップサイドダウン)にも限定
されるものではない。
In addition, the four-metal base (1) is not limited to a carrier type (without a cap) or a type with a camp, but may be any of them,
(upside amplifier or upside down).

さらに、電源線路(15) (17)は、入力側および
出力側とも、信9線路(io) (u)に対して各1個
を同じ側に形成させたものを示したが、これに限定され
ず、必要な0住を有する形状、個数、位置等に形成され
たものとしても良く、上記と同様の効果を有するもので
ある。
Furthermore, power supply lines (15) and (17) are shown in which one each is formed on the same side for the nine signal lines (io) and (u) on both the input side and the output side, but this is not limited to this. Instead, they may be formed in a shape, number, position, etc. having the necessary zero position, and the same effect as described above can be obtained.

[発明の幼果] 以上のようにこの発明によれば、高周波半導体素子と接
続されて高@波信号を通過させる信9線路と、上記高周
波半4体素子−C電源を供給させる電ぷ線路とを備え、
これら両者が所定の特性の遡II&線路を介して接続さ
れる構成とし念ので、高周波信号の伝送に影響を及ぼす
ことなく電源供給がなされて前作できる、高信頼の半導
体装置が得られる効果を有する。
[Effects of the Invention] As described above, according to the present invention, the signal line 9 is connected to a high frequency semiconductor element and passes a high @ wave signal, and the power line is connected to a high frequency semiconductor element and passes a high @ wave signal, and a power line that supplies the high frequency half quadrilateral element-C power. and
Since both of these are connected via trace II & lines with predetermined characteristics, it is possible to supply power without affecting the transmission of high-frequency signals, making it possible to obtain a highly reliable semiconductor device that can be used for previous production. .

【図面の簡単な説明】[Brief explanation of drawings]

4s1図はこの発明の一実施例を示す部分破′rT乎面
凶、第2因は第1図に示すものの連絡線路の等価回路説
明図、第3図は第1図に示すものの等画回路図、第4図
はこの発明の他の一実施例を示す斜視図、第5凶は従来
の半導体装置を示す部分破断乎曲図、第6図は第5図に
示すものの等価回路図である。 凶において、(2)は半導体チップ、(3)は金属細線
、(4)および(5) Fi入力側および出力側の整合
基板。 (8)および(9) r1入力側および出力側の線路基
板、(10)および(11)は入力側および出力側の信
号線路、 (15)および(17)は入力側および出力
側の電源線路、 (15a)および(17a)Fi入力
側および出力側の連絡線路、 (22)および(23)
if入力側および出力側の基板、(U)および(25)
は入力側および出力側の整合部、(26)νよび(27
) r1入力側および出力側の線路部である。 なお1図中同一符5jは同一、又は相当部分を示す。
Figure 4s1 is a partially broken diagram showing one embodiment of this invention; the second cause is an explanatory diagram of an equivalent circuit of the connection line shown in Figure 1; Figure 3 is an equivalent circuit diagram of the one shown in Figure 1. Figure 4 is a perspective view showing another embodiment of the present invention, Figure 5 is a partially cutaway diagram showing a conventional semiconductor device, and Figure 6 is an equivalent circuit diagram of the one shown in Figure 5. . (2) is a semiconductor chip, (3) is a thin metal wire, (4) and (5) is a matching substrate on the Fi input side and output side. (8) and (9) R1 input and output side track boards, (10) and (11) are input and output side signal lines, (15) and (17) are input and output side power supply lines. , (15a) and (17a) Fi input side and output side connection line, (22) and (23)
if input side and output side boards, (U) and (25)
are input and output matching parts, (26) ν and (27
) This is the line section on the r1 input side and output side. Note that the same reference numerals 5j in FIG. 1 indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】 (1)高周波半導体素子と、この高周波半導体素子と外
部回路とを接続させて高周波信号の通路となる信号線路
と、この信号線路に接続され、高周波成分は阻止し、か
つ電源電力は通過させる所定の長さの連絡線路と、この
連結線路を介して上記高周波半導体素子に電源を供給す
る電源線路とを備えた半導体装置。 (2)連絡線路は、高周波領域において(2n+1)×
波長/4、(ただし、n=0、1、2、・・・の整数)
であることを特徴とする特許請求の範囲第1項記載の半
導体装置。(3)信号線路と連絡線路と電源線路とは、
同一絶縁基板上に形成されたものであることを特徴とす
る特許請求の範囲第1項または第2項記載の半導体装置
。 (4)高周波半導体素子に含まれて信号線路に接続され
る整合回路と信号線路と連絡線路と電源線路とは、同一
絶縁基板上に形成されたものであることを特徴とする特
許請求の範囲第1項または第2項記載の半導体装置。
[Scope of Claims] (1) A high-frequency semiconductor element, a signal line that connects the high-frequency semiconductor element and an external circuit and serves as a path for high-frequency signals, and a signal line that is connected to the signal line and blocks high-frequency components; A semiconductor device comprising: a connecting line of a predetermined length through which power source power passes; and a power line supplying power to the high frequency semiconductor element via the connecting line. (2) The connecting line is (2n+1)× in the high frequency region
Wavelength/4 (however, n = integer of 0, 1, 2,...)
A semiconductor device according to claim 1, characterized in that: (3) What are signal lines, communication lines, and power lines?
3. The semiconductor device according to claim 1, wherein the semiconductor device is formed on the same insulating substrate. (4) A claim characterized in that the matching circuit, signal line, communication line, and power supply line included in the high-frequency semiconductor element and connected to the signal line are formed on the same insulating substrate. The semiconductor device according to item 1 or 2.
JP13848287A 1987-06-02 1987-06-02 Semiconductor device Pending JPS63302602A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13848287A JPS63302602A (en) 1987-06-02 1987-06-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13848287A JPS63302602A (en) 1987-06-02 1987-06-02 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS63302602A true JPS63302602A (en) 1988-12-09

Family

ID=15223111

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13848287A Pending JPS63302602A (en) 1987-06-02 1987-06-02 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS63302602A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018123064A1 (en) * 2016-12-29 2018-07-05 三菱電機株式会社 Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018123064A1 (en) * 2016-12-29 2018-07-05 三菱電機株式会社 Semiconductor device

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