JPS63300545A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63300545A JPS63300545A JP62136769A JP13676987A JPS63300545A JP S63300545 A JPS63300545 A JP S63300545A JP 62136769 A JP62136769 A JP 62136769A JP 13676987 A JP13676987 A JP 13676987A JP S63300545 A JPS63300545 A JP S63300545A
- Authority
- JP
- Japan
- Prior art keywords
- plastic
- lead frame
- passages
- semiconductor device
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 238000000034 method Methods 0.000 claims description 13
- 238000005452 bending Methods 0.000 abstract description 4
- 238000012935 Averaging Methods 0.000 abstract 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 238000010137 moulding (plastic) Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
本発明は、半導体装置のプラスチック封止に際し給送さ
れる融溶プラスチックが半導体素子に衝突する領域に、
融溶プラスチックの各流路の抵抗を平均させる遮蔽部材
が付加されているリードフレームを使用してプラスチッ
ク成形し、融溶プラスチック流路の抵抗をバランスさせ
、バブル等が残留することがないようにしてプラスチッ
クパッケージの成形をする半導体装置の製造方法である
。DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention is directed to a region where molten plastic fed during plastic sealing of a semiconductor device collides with a semiconductor element.
Plastic molding is performed using a lead frame that has a shielding member that averages the resistance of each flow path of the molten plastic to balance the resistance of the flow paths of the molten plastic and prevent bubbles from remaining. This is a semiconductor device manufacturing method that involves molding a plastic package.
（産業上の利用分野〕
本発明は、半導体装置の製造方法の改良に関する。特に
、プラスチックパッケージの製造方法の改良に関する。(Industrial Application Field) The present invention relates to an improvement in a method for manufacturing a semiconductor device.In particular, the present invention relates to an improvement in a method for manufacturing a plastic package.
半導体装置は、半導体装置本体を外部環境から保護する
等のため、何らかのパッケージに入れて使用されるが、
経済的利益が大きいため、プラスチックパッケージが広
く使用されている。Semiconductor devices are used in some kind of package to protect the semiconductor device itself from the external environment.
Plastic packaging is widely used because of its great economic benefits.
半導体装置は、外形寸法を益々縮少することが求められ
ており、また、使用材料を節減する要求も大きい、しか
も、半導体チップ、ボンディングワイヤ、リードフレー
ム等は、電流容量・特性等の関係から、縮少には限界が
あるので、リードフレームに凹部を設けるか、曲げを加
え、第２ａ図、第２ｂ図に示すように、リードフレーム
に取り付けられボンディングがなされている半導体素子
の全体がモールドの中心に位置するような構造とされる
場合が一般である０図において、１は半導体素子であり
、２はボンディングワイヤであり、３はリードフレーム
であり、４がプラスチックパッケージである。Semiconductor devices are required to further reduce their external dimensions, and there is also a strong demand to reduce the amount of materials used.Moreover, semiconductor chips, bonding wires, lead frames, etc. are becoming increasingly smaller due to current capacity, characteristics, etc. Since there is a limit to shrinkage, the entire semiconductor element attached to the lead frame and bonded can be molded by providing a recess or bending the lead frame, as shown in Figures 2a and 2b. In the figure, 1 is a semiconductor element, 2 is a bonding wire, 3 is a lead frame, and 4 is a plastic package.
〔発明が解決しようとする問題点］
このように、リードフレームに凹部を設けたり、曲げを
加えたりしである場合、プラスチックパッケージを形成
するためには、成形用モールドを、第３図に６１．６２
をもって示すようにし、融溶プラスチックは矢印Ａ、Ｂ
、Ｃ，Ｄをもって示すように圧入するが、図より明らか
なように、矢印Ｂに沿う融溶プラスチ７クの流露抵抗よ
り矢印Ｃに沿う流路抵抗が大きいので、結果的にリード
フレーム３の裏面にバブル５が残留してリードフレーム
が露出側ることがあり、絶縁耐力の低下や水分等の侵入
による信頗性の低下が問題になっていた。[Problems to be Solved by the Invention] As described above, in the case where the lead frame is provided with a recess or bent, in order to form a plastic package, the mold must be placed at 61 in Fig. 3. .62
The melted plastic should be indicated by arrows A and B.
, C, and D, but as is clear from the figure, the flow path resistance along arrow C is greater than the flow resistance of the molten plastic 7 along arrow B, so as a result, the lead frame 3 Bubbles 5 may remain on the back surface, leaving the lead frame exposed, resulting in problems such as a decrease in dielectric strength and a decrease in reliability due to intrusion of moisture and the like.
この問題点を解消する手法として、第４図、第５図に、
６３．６４．６５．６６をもって示すような変形した構
造のモールドを使用する手法や、溶融状態の樹脂の粘度
を低くして流路抵抗を制御する手法が知られているが、
前者はモールドが複雑になり、製作・保守が困難であり
、後者は工業的に実行が困難であるという欠点があり、
いづれも、現実的に必ずしもすぐれた手法とは言い難い
。As a method to solve this problem, as shown in Figures 4 and 5,
63, 64, 65, 66, methods of using a mold with a deformed structure, and methods of controlling flow path resistance by lowering the viscosity of the molten resin are known.
The former has the disadvantage that the mold is complicated and difficult to manufacture and maintain, and the latter is difficult to implement industrially.
In reality, it is difficult to say that either method is necessarily an excellent method.
本発明の目的は、この欠点を解消することにあり、絶縁
耐力にすぐれ、信鯨性の高いプラスチックパッケージを
をする半導体装置の製造方法を徒供することにある。An object of the present invention is to eliminate this drawback, and to provide a method for manufacturing a semiconductor device having a plastic package with excellent dielectric strength and high reliability.
Ｃ問題点を解決するための手段〕
上記の目的は、リードフレーム（３）に半導体素子（１
）を取り付け、該半導体素子（１）と該リードフレーム
（３）とをボンディングワイヤ（２）をもって接続し、
ａｉｌＩＩ溶プラスチックをもって封止する半導体装置
の製造方法において、前記リードフレーム（３）には、
プラスチック成形に際し給送される融溶プラスチックが
前記半導体素子（１）に衝突する領域に、融溶プラスチ
ックの各流路に対する抵抗を平均させる遮蔽部材（３１
）が付加することによって達成される。Means for Solving Problem C] The above purpose is to attach a semiconductor element (1) to a lead frame (3).
), and connect the semiconductor element (1) and the lead frame (3) with a bonding wire (2),
In the method for manufacturing a semiconductor device in which the semiconductor device is sealed with ail II melted plastic, the lead frame (3) includes:
A shielding member (31) is provided in a region where the molten plastic fed during plastic molding collides with the semiconductor element (1) to average the resistance to each flow path of the molten plastic.
) is achieved by adding
本発明に係るプラスチックパッケージの製造方法におい
ては、リードフレーム３に、融溶プラスチック流路の抵
抗を平均化する遮蔽部３１が付加されているので、半導
体素子１の表、裏で融溶プラスチックが均等に注入去れ
ることになり、バブル等が残留することはない。In the method for manufacturing a plastic package according to the present invention, the lead frame 3 is provided with a shielding portion 31 that averages out the resistance of the molten plastic flow path, so that the molten plastic is spread on the front and back sides of the semiconductor element 1. This allows for even injection and removal, and no bubbles remain.
以下、図面を参照しつ＼、本発明の実施例に係る半導体
装置の製造方法について、さらに説明する。Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be further described with reference to the drawings.
第１ａ図参照
図示するように、リードフレーム３の形成時にその端部
を折り曲げて融溶プラスチック流路の抵抗を平均化する
遮蔽部３１を付加し、これに半導体素子１を取り付け、
ボンディングワイヤ２を取り付けた後、モールド６７．
６８を使用してプラスチック成形をなす、融溶プラスチ
ックは、矢印Ａにそって供給された後、融溶プラスチッ
ク流路の抵抗をバランスさせる遮蔽部３１に衝突して、
矢印Ｂ、Ｃにそって分散して流れるが、上記の遮蔽板３
１の存在により、矢印Ｂ、Ｃの融溶プラスチック流路の
抵抗が均等であるので、半導体素子１の周囲のいずれの
領域にも均一に融溶プラスチックが流れる。そのため、
バブル等が残留することはない。As shown in FIG. 1a, when the lead frame 3 is formed, a shielding part 31 is added to the lead frame 3 by bending its end to equalize the resistance of the molten plastic flow path, and the semiconductor element 1 is attached to this.
After attaching the bonding wire 2, the mold 67.
After the molten plastic is fed along the arrow A, it hits the shield 31 that balances the resistance of the molten plastic flow path.
Although the flow is dispersed along arrows B and C, the above shielding plate 3
1, the resistance of the molten plastic flow paths indicated by arrows B and C is equal, so that the molten plastic flows uniformly to any area around the semiconductor element 1. Therefore,
No bubbles remain.
第１ｂ図参照 第１ｂ図は本発明の別の実施例を示す図である。See figure 1b FIG. 1b shows another embodiment of the invention.
遮蔽板３１は、第１ａ図に示すように注入口側に付加す
るのみならず、第１ｂ図に示すように側面にも付加すれ
ば、側面に廻り込んだ融溶プラス千ツクに対しても、同
様の効果を得ることができる。If the shielding plate 31 is attached not only to the inlet side as shown in Fig. 1a, but also to the side as shown in Fig. 1b, it will protect against melted plastic that has gone around the side. , a similar effect can be obtained.
また、遮蔽板３１は、第１ａ図に示すように、リードフ
レーム３を折り曲げて製造することが容易であるが、第
１ｃ図に示すように、ブロック状部材３２を設けること
で融溶プラスチック流路の抵抗を平均化してもよい。The shielding plate 31 can easily be manufactured by bending the lead frame 3 as shown in FIG. The road resistance may be averaged.
以上説明せるとおり、本発明に係る半導体装置の製造方
法においては、融溶プラスチック流路の抵抗を平均化す
る遮蔽部が付加されているリードフレームが使用されて
いるので、プラスチック成形に際し、半導体素子の上、
下の融溶プラスチック流路の抵抗がバランスしており、
バブル等が残留することはない、そのため、絶縁耐力に
すぐれ、信幀性の高いプラスチックパッケージを有する
半導体装置を製造することができる。As explained above, in the method for manufacturing a semiconductor device according to the present invention, a lead frame is used which is provided with a shielding part that averages out the resistance of the molten plastic flow path. upon,
The resistance of the melted plastic flow path below is balanced,
No bubbles or the like remain, so it is possible to manufacture a semiconductor device having a plastic package with excellent dielectric strength and high reliability.
第１ａ図は、本発明の一実施例に係るプラスチックパッ
ケージの製造方法を説明する図である。
第１ｂ図は、本発明の他の実施例に係るプラスチックパ
ッケージの製造方法を説明する図である。
第１Ｃ図は、本発明の別の実施例に使用されるリードフ
レームの側面図である。
第２ａ図、第２ｂ図は、従来技術に係るプラスチックパ
ッケージの断面図である。
第３図は、従来技術に係るプラスチックパッケージの製
造方法の欠点を示す図である。
第４図、第５図は、改良された従来技術に係るプラスチ
ックパッケージの製造方法の説明図である。
ｌ・・・半導体素子、
２・・・ボンディングワイヤ、
３・・・リードフレーム、
３１・・・遮蔽部材、
４・・・プラスチックパッケージ、
５・・・バブル、
６１〜６８・・・モールド。
第１ｃ図
本発明
第１ｂ図
本発明
第１ｃ ｇＪ
従来技術
第２ｂ図
従来技１１！つ又、り１、
第３図FIG. 1a is a diagram illustrating a method of manufacturing a plastic package according to an embodiment of the present invention. FIG. 1b is a diagram illustrating a method of manufacturing a plastic package according to another embodiment of the present invention. FIG. 1C is a side view of a lead frame used in another embodiment of the invention. 2a and 2b are cross-sectional views of a plastic package according to the prior art. FIG. 3 is a diagram showing the drawbacks of the prior art method of manufacturing a plastic package. 4 and 5 are explanatory diagrams of an improved method of manufacturing a plastic package according to the prior art. 1... Semiconductor element, 2... Bonding wire, 3... Lead frame, 31... Shielding member, 4... Plastic package, 5... Bubble, 61-68... Mold. Figure 1c Present invention Figure 1b Present invention 1c gJ Prior art Figure 2b Prior art 11! Tsumata, Ri1, Figure 3
Claims (1)
前記半導体素子（１）と該リードフレーム（３）とをボ
ンディングワイヤ（２）をもって接続し、融溶プラスチ
ックをもって封止する半導体装置の製造方法において、 前記リードフレーム（３）には、プラスチック成形に際
し給送される融溶プラスチックが前記半導体素子（１）
に衝突する領域に、融溶プラスチックの各流路に対する
抵抗を平均させる遮蔽部材（３１）が付加されてなる ことを特徴とする半導体装置の製造方法。[Claims] A semiconductor element (1) is attached to a lead frame (3),
In the method for manufacturing a semiconductor device, the semiconductor element (1) and the lead frame (3) are connected with a bonding wire (2) and sealed with molten plastic. The molten plastic fed is the semiconductor element (1)
A method of manufacturing a semiconductor device, characterized in that a shielding member (31) is added to a region where the molten plastic collides with the flow path to average the resistance of the molten plastic to each flow path.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62136769A JPS63300545A (en) | 1987-05-29 | 1987-05-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62136769A JPS63300545A (en) | 1987-05-29 | 1987-05-29 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63300545A true JPS63300545A (en) | 1988-12-07 |
Family
ID=15183083
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62136769A Pending JPS63300545A (en) | 1987-05-29 | 1987-05-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63300545A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0394432A (en) * | 1989-06-30 | 1991-04-19 | Sanken Electric Co Ltd | Manufacture of resin-sealed electronic component |
| JPH0446549U (en) * | 1990-08-23 | 1992-04-21 | ||
| JP2010103411A (en) * | 2008-10-27 | 2010-05-06 | Shindengen Electric Mfg Co Ltd | Semiconductor device and method of manufacturing the same |
-
1987
- 1987-05-29 JP JP62136769A patent/JPS63300545A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0394432A (en) * | 1989-06-30 | 1991-04-19 | Sanken Electric Co Ltd | Manufacture of resin-sealed electronic component |
| JPH0446549U (en) * | 1990-08-23 | 1992-04-21 | ||
| JP2010103411A (en) * | 2008-10-27 | 2010-05-06 | Shindengen Electric Mfg Co Ltd | Semiconductor device and method of manufacturing the same |
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